Showing papers on "Chip published in 1969"

Secure spread spectrum communication system

Abstract: A communication system is protected against jamming by modifying a conventional spread spectrum communication system by inserting errors, in the form of digital noise, into the pseudo-noise digital code used to generate the spread spectrum carrier. A bidirectional system is provided so that when jamming occurs, as a consequence of breaking the corrupted spread spectrum code, the pseudo-noise digital code and/or the percent of errors is changed in a prearranged manner to compensate for the jamming and/or reduce the likelihood of breaking the corrupted spread spectrum code. A conventional correlation receiver is employed to recover the intelligence.

Construction of monolithic chip and method of distributing power therein for individual electronic devices constructed thereon

Abstract: To eliminate parasitic voltage drops to electrodes of semiconductor devices built on a semiconductor chip or wafer, due to the use of an element of a voltage and current supply conductor in common for several such semiconductor devices, a separate path is diffused for each electrode, onto such chip or wafer as a built-up post of the basic semiconductor material of the chip or wafer, and the back surface of the chip or wafer is used as a relatively wide area surface as a voltage supply bus, which may also be connected to a metal base for the double purpose of establishing that surface at some selected known potential and providing a good heat sink for the chip or wafer. Generally, the potential of the metal base may be placed at ground, but need not be.

Chip select circuit for multichip random access memory

Abstract: A random access read-write memory comprises memory sections formed on a plurality of chips. The decoding of the chip select signal inhibits the write command signal from all but the selected chip, thereby permitting new data to be written only at the selected chip.

An Accumulator Chip

Abstract: A large-scale integrated-circuit chip has been designed under the sponsorship of the Air Force Avionics Laboratory. The chip was developed as part of a logic synthesizer effort of the Design Automation group at Litton Systems, Inc., Guidance and Control Systems Division. It was designed as a type or category to be multiply used with one other gating type chip whose format is prescribed by the logic synthesizer. A major goal of this effort will be to design a complete digital system by design-automated techniques using only these two types of chips in a large-scale array.

Thermal impedance of ceramic packages using beam-lead IC chips

Abstract: A three-dimensional analytical approximation for the thermal impedance of a beam-lead IC package is obtained by calculating the thermal resistance of the individual elements and solving by the electrothermal analog technique. For a single chip package, thermal impedance values are presented for both a centrally located 0.005 inch diameter junction area and a source evenly distributed over the active surface of the chip under the following mounting conditions: a) package with external leads heat-sinked; b) package with ceramic base heat-sinked; c) chip thermally isolated on Al 2 O 3 substrate. Also, variations in the thermal impedance of the package with changes in the chip component dimensions are shown graphically. For arrays of beam-lead chips on small ceramic substrates, curves are presented for the upper and lower boundaries of maximum chip power as a function of the number of chips appliqued to the substrate. The results indicate that the relatively low power levels which are characteristic of most logic-type beam-lead devices create no thermal problems when packaged individually. However, for large chip arrays the ability of a particular substrate to dissipate the heat generated may be a limiting factor even for these seemingly insignificant power levels.

30-circuit monolithic chip with 750-PS loaded-circuit delay per stage

Abstract: A high-speed 30-circuit silicon chip using non-saturating emitter-coupled logic circuits with 750-ps loaded delay per stage using 3-level metalization will be described. The chip contains 210 transistors and 196 resistors.

A triple-channel micropower operational amplifier

Abstract: One method of increasing the amount of circuit functions using bipolar devices is to simplify the design of the monolithic chip. This paper describes such a new integrated circuit. The circuit has three independent, micropower, high- gain operational amplifiers on the monolithic chip. Open-loop voltage gain as high as 100 dB has been achieved with a power dissipation of under 300 /spl mu/W. The gain and power dissipation are externally controlled byout board components. Complete performance characteristics along with analysis are presented.

Thermal Impedance of Ceramic Packages Using Beam-Lead IC Chips

Abstract: A three-dimensional analytical approximation for the thermal impedance of a beam-lead IC package is obtained by calcu- lating the thermal resistance of the individual elements and solving by the electrothermal analog technique. For a single chip package, thermal impedance values are presented for both a centrally located 0.005 inch diameter junction area and a source evenly distributed over the active surface of the chip under the following meunting condi- tions: a) package with external leads heat-oinked; b) package with ceramic base heat-sinked; c) chip thermally isolated on AI,O, sub- strate. Also, variations in the thermal impedance of the package with changes in the chip component dimensions are shown graphically. For arrays of beam-lead chips on small ceramic substrates, curves are presented for the upper and lower boundaries of maximum chip power as a function of the number of chips appliqued to the sub- strate. The results indicate that the relatively low power levels which are characteristic of most logic-type beam-lead devices create no thermal problems when packaged individually. However, for large chip arrays the ability of a particular substrate to dissipate the heat generated may be a limiting factor even for these seemingly insignificant power levels?