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Showing papers on "Chip published in 1970"


01 Jan 1970
TL;DR: The final author version and the galley proof are versions of the publication after peer review that features the final layout of the paper including the volume, issue and page numbers.
Abstract: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

22 citations


Patent
19 Aug 1970
TL;DR: In this paper, a dynamic MOS memory array chip is disclosed which utilizes four-device cells, all of which are gated to a charging potential and all of the word lines are pulsed simultaneously so that all cells in the array can be refreshed together.
Abstract: A dynamic MOS memory array chip is disclosed which utilizes four-device cells. During the refresh cycle, all of the bit/sense line pairs are gated to a charging potential and all of the word lines are pulsed simultaneously so that all cells in the array can be refreshed together. The refresh pulse level applied to all of the word lines is lower than the select pulse level applied to any one of the word lines during a read or write operation.

17 citations


Patent
Paul Robert Schroeder1
19 Mar 1970
TL;DR: In this article, a row and column access circuit for an integrated circuit memory chip each includes crossunders to accommodate intersecting circuits along about half of the extent of such circuit on the chip and no crossunders for the remainder of its extent.
Abstract: Metalized row and column access circuits for an integrated circuit memory chip each includes crossunders to accommodate intersecting circuits along about half of the extent of such circuit on the chip and no crossunders for the remainder of its extent. The distribution of crossunders along each circuit is such that the bulk of the included crossunders are in the part of the circuit more remote from the circuit-driving point than is the part which is essentially free of crossunders. Metalized bit circuits for the chip are arranged so that they always extend physically parallel to access circuit parts which are free of crossunders so that the bit circuits are entirely free of crossunders. Schematic and actual layouts for a cell used in such a memory chip are shown.

15 citations


Patent
19 Aug 1970
TL;DR: In this paper, a bipolar driver for a dynamic MOS memory array chip is described, where a high-level pulse is generated if a read or write operation is to be performed on a cell in the array, followed by an intermediate level pulse if during the same cycle all cells of the array are refreshed.
Abstract: A bipolar driver for a dynamic MOS memory array chip. The drive signal which is generated consists of a high-level pulse if a read or write operation is to be performed on a cell in the array, followed by an intermediate level pulse if during the same cycle all cells in the array are to be refreshed. A pulse generator is normally operative to apply a high-level potential to an output terminal under the control of an input decoder. When a refresh pulse is to be generated, the pulse generator is made to energize its output terminal independent of the operation of the decoder, but a diversion of current in the pulse generator at this time causes the potential at the output terminal to be at a lower level.

11 citations


Patent
01 May 1970
TL;DR: In this article, the authors proposed a semiconductor orthogonal memory system in which a grid of row and column chip select conductors, and a grid-of-row and column data conductors are coupled to an array of memory modules.
Abstract: A semiconductor orthogonal memory system in which a grid of row and column chip select conductors, and a grid of row and column data conductors, are coupled to an array of memory modules. Common address bits are extended to all modules. The memory is several (eight, in the illustrative embodiment) times faster than the processor with which it operates, and accordingly three of the address bits are cycled during each read or write processor operation. This results in a sequence of eight bits on each row or column data conductor; the number of utilizable bit storage locations in each module is thus increased by a factor of 64. Each module can include several chips, each of which may be divided into multiple segments. In the case of two chips, and two segments per chip, the same number segment in the same number chip in all modules of the selected row or column of modules can be identified by doubling the number of chip select conductors otherwise required and by utilizing one of the address bits to distinguish between the two segments on each chip. This technique increases the number of utilizable bit storage locations in each module to 256. The overall arrangement allows the number of bits in an orthogonal word to be significantly greater than the number of bits in a normal word, without requiring wire linking of the entire bit-storage array and without requiring the array as a whole to be dimensioned to match the entire orthogonal memory.

10 citations


Patent
29 Jul 1970
TL;DR: In this article, a machine-practiced method for determining partial memory chip categories was proposed, where each address bit of each bad cell on the chip was examined, and two respective partial chip categories were eliminated depending on its value.
Abstract: A machine-practiced method for determining partial memory chip categories. In the case of 128-cell chips having seven address bits, there are fourteen partial memory chip categories; permanently addressing any one of the seven address lines with a 1 or a 0 produces an effective 64-cell chip, any cell of which can be selected depending upon the address bits extended to the other six address lines. Each address bit of each bad cell on the chip is examined. Depending on its value, one of two respective partial chip categories is eliminated. After all cells have been processed in this manner, the partial chip categories which have not been eliminated are those applicable to the chip.

9 citations


Journal ArticleDOI
TL;DR: In this article, a basic equation for the design of chip breaker has been derived both analytically and experimentally, and the characteristic feature of this equation is that one can design a chip breaker if only the Brinell hardness and feed to be used are known, and that one series of four step chip breakers thus designed can cover ordinary commercial cutting conditions and work materials.
Abstract: Chip hazard has been recognized to be one of the most serious problems in metal cutting industry, especially in transfer or numerically controlled machines, and hence systematized manufacturing areas.Here in this report a basic equation for design of chip breaker has been derived both analytically and experimentally.The characteristic feature of this equation is that one can design a chip breaker if only the Brinell hardness and feed to be used are known, and that one series of four step chip breakers thus designed can cover ordinary commercial cutting conditions and work materials.The algorism of this chip breaker system has been implemented for the automatic programming system for numerically controlled machines.

8 citations


Patent
Jack O Field1
19 Mar 1970
TL;DR: In this paper, the authors describe how to time share certain pads on an integrated circuit chip between several signals by providing shift registers for these pads and having each shift register receive, in parallel, the data bits provided by several of the logic circuits on the chip.
Abstract: Input and output circuitry is described which enables one to time share certain pads on an integrated circuit chip between several signals. This may be accomplished by providing shift registers for these pads and having each shift register receive, in parallel, the data bits provided by several of the logic circuits on the chip. Each shift register thereafter provides a signal which represents the data in serial order, and this signal is applied through the pad to a pad on a second chip. The signal is thereafter applied to a shift register on the second chip, and the data bits appear at its outputs in parallel. The data bits are thereafter applied to logic circuits on the second chip.

6 citations


Book ChapterDOI
01 Jan 1970
TL;DR: In this paper, it was shown that the radius of chip curvature is directly proportional to the uncut chip thickness when the chip flows without interference and that at sufficiently high rake angles the chip curvatures can become negative.
Abstract: SUMMARY Previously proposed mechanisms which have been advanced to account for chip curl are considered and of these, that suggested by Albrecht (viz. that chip curvature arises because of non-colinearity between the lines of action of the resultant cutting force acting on the workpiece and of the resultant cutting force acting on the tool) is pursued. Using previously formulated cutting mechanics, the bending moment due to non-colinearity is shown to be proportional to the square of the uncut chip thickness when the chip flows without interference. Treating the chip as a plastically deformed beam subjected 10 such a moment, the radius of chip curvature is shown to be directly proportional to the uncut chip thickness. Experiments designed to minimize interference to chip flow produce values of chip radii of curvature which, when corrected for spring back, are proportional to uncut chip thickness. The influence of cutting speed, cutting fluids, rake angle and obstruction to free flow of the chip are examined and, in particular, it is shown that at sufficiently high rake angles the chip curvature can become negative.

5 citations


Patent
H Chang1
31 Dec 1970
TL;DR: In this article, a structure for cylindrical, single wall magnetic domains using a plurality of magnetic chips to achieve large size devices, such as long shift registers, is presented, where magnetic chips are pieced together and domain propagation from one chip to another is effected by an interaction between domains located on adjacent chips.
Abstract: A structure for cylindrical, single wall magnetic domains using a plurality of magnetic chips to achieve large size devices, such as long shift registers. The magnetic chips are pieced together and domain propagation from one chip to another is effected by an interaction between domains located on adjacent chips. The domains themselves are not able to cross the boundary between adjacent chips. Propagation means in one chip brings domains representing information bits in that chip closely enough to a second chip that these domains will magnetically interact with other domains in the second chip, causing the domains in the second chip to then propagate as information bits. Consequently, a large device is comprised of a number of smaller segments which cooperatively interact. This overcomes the constraint of bit capacity limitation due to the dimensions of magnetic chips. This also facilitates the combined use of chips with different properties as designed for different functions.

4 citations


Proceedings ArticleDOI
Barrie Gilbert1
01 Jan 1970
TL;DR: In this paper, an integrated circuit that generates vertical and horizontal signals to display high-quality alphameric symbols on a CRT was discussed, each symbol, composed of seven srokes, may have virtually any length and angle.
Abstract: An integrated circuit that generates vertical and horizontal signals to display high-quality alphameric symbols on a CRT will be discussed. Each symbol, composed of seven srokes, may have virtually any length and angle. The complete generator-an analog read-only memory-is fabricated on a 65-mil square bi-polar chip.

Proceedings ArticleDOI
01 Jan 1970
TL;DR: The Cogar 1024-bit MOS read-write memory chip is fully decoded, has a 100ns access time, and is only 125 × 125 mils in size as discussed by the authors.
Abstract: The Cogar 1024-bit MOS read-write memory chip is fully decoded, has a 100-ns access time, and is only 125 × 125 mils in size. This small size is made possible by the use of a 4-device memory cell and dimensional tolerances as small as 0.15 mil. The chips are fabricated from a 2.25-inch-diameter wafer that consists of a low-resistivity p-type substrate covered by a high-resistivity p-type epitaxial layer. This epitaxial layer provides not only for precise control of surface impurity concentration, but also provides means for a reach-through type of gate protection device. In addition, the low-resistivity substrate tends to minimize unwanted noise voltages due to pulse currents flowing through the substrate.