Showing papers on "Chip published in 1971"

A high-performance N-channel MOS-LSI using depletion-type load elements

Abstract: A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.

Integrated circuit chip repair tool

Abstract: An integrated circuit chip repair tool for bonding or removing reflow soldered chips on multi-chip substrates having chip pickup means to move chips toward or away from a substrate, flame heating means to apply a concentrated source of heat to a single chip without overheating adjacent chips, infrared temperature sensing means to measure the temperature of a heated chip and control means responsive to the temperature of the heated chip to automatically discontinue heating by extinguishing the flame and to automatically activate the chip pickup means.

Method for manufacturing wire bonded integrated circuit devices

Abstract: A lead frame for a semiconductor device has a semiconductor chip supporting pad and a plurality of lead fingers with terminal bonding portions near the chip supporting pad. The bonding portions of the lead fingers and the chip supporting surface of the pad are non-coplanar. In using this lead frame in fabricating a device, the non-coplanar elements are forced into and held in coplanar relationship, the connector wires are bonded between the lead fingers and the chip, and the frame is then released to permit it to return to its non-coplanar configuration. The connector wires are thus lifted to a greater angle with respect to the semiconductor chip surface and short circuits at the edge of the chip tend to be eliminated.

Package for integrated circuit chip

Abstract: An improved microcircuit package is provided for integrated circuit chips, or the like, and which greatly simplifies the manner in which electrical connections may be made between the contacts on the chip and the terminal electrodes and other connections of the microcircuit. The package of the invention comprises a substrate of glass ceramic, polymide, or the like, having adhesive electric conductors formed on its surface, which conductors make connection between the contacts on the integrated circuit chip and the terminal electrodes, merely by pressing the chip over the adhesive electric conductors, the conductors serving additionally to hold and position the chip in the flat pack.

Integrated circuit structure having a unique surface metallization layout

Abstract: A planar monolithic integrated circuit chip containing an isolation region of one conductivity type extending completely around the edge or periphery of the chip in order to insure that there are no exposed P-N junctions on an edge surface of the chip. Such an isolation region extends for at least a minimum distance from the edge of the chip, said distance being determined so as to minimize the risk of any edge defects in the chip resulting from dicing and handling from extending beyond the isolation region into the body of the chip. An insulative layer over the planar surface of the chip supports a metallization pattern for interconnecting the devices in the integrated circuit and for distributing a plurality of voltage supplys at different levels to the devices. The metallization pattern is arranged so that only metallization connected to the voltage supply at the same level as the peripheral isolation region is located on the portion of the insulative layer between the chip edge and the minimum distance of the isolation junction from the edge.

Heat sinking of semiconductor integrated circuit devices

Abstract: A semiconductor device of the type in which a semiconductor chip is mounted on a lead assembly having a chip mounting portion, thermal conductors, and electrical conductors. The chip has some elements which generate heat, which are located in one zone of the chip, and others which are sensitive to spatial thermal gradients, which are located in a different zone of the chip. The chip mounting portion of the lead assembly has an area substantially free of spatial thermal gradients and the zone of the chip containing the sensitive elements is mounted adjacent to this area.

Modeling and Radiation Effects Study of an LSI/MOS Logic System

Abstract: This paper presents the results of a comprehensive modeling and radiation effects study of a p-channel enhancement mode LSI/MOS test chip (TC) specifically designed to allow measurement of discrete device type parameters and responses for circuits constructed from similar devices on a common chip. Particular emphasis was given to the development of accurate models of the individual devices and to the demonstration of the use of these models in predicting the radiation responses of the circuits on the chip. Ionization dose and neutron effects were determined for each of the parameters used in the model which contained the basic Sah equations modified to include channel length modulation effects, the body effect, and the electric-field-dependence of channel mobility. Average values of these parameters were then used in predictions of pre- and post-radiation responses for circuits.

Apparatus and method for determining partial memory chip categories

Abstract: A machine-practiced method for determining quarter-partial memory chip categories. In the case of 1024-cell chips having ten address bits, there are 180 quarter-partial memory chip categories; permanently addressing any two of the 10 address lines with 1''s or 0''s, or combinations thereof, produces an effective 256-cell chip, any cell of which can be selected depending upon the address bits extended to the other eight address lines. The method allows a rapid determination of the applicable quarter-partial chip categories after all of the cells on the chip are first tested and the bad cells are identified. One way to identify the bad cells is to use a test sequence which has the minimum length required to test for all dynamic failure modes of interest. Apparatus is also disclosed for testing the cells at a slower rate, but with a minimum of tester complexity.

Design Considerations for Semiconductor Ramdom Access Memory Systems

Abstract: Random access semiconductor memory systerm components available today reflect a broad spectrum of engineering, financial and managerial judgment. Each of the products was intended to satisfy the performance and cost goals of a particular segment of the memory market. The decisions which were made regarding technology to be used, chip density, package density, package type, electrical performance and environmental performance, reflect the weighted factors of market segment need versus investment required. The resulting product is in many cases a compromise. For example, a lower chip density may result in lower cost per bit at the chip level due to higher yields. However, higher chip densities, inherent when decoding is on the chip, may be required due to the lack of a package with enough leads to accommodate a non-decoded chip. The assumption is that need to capitalize a new package production line represents higher financial risk than that which results from the lower yields at the chip level.

A Ferroelectric-Piezoelectric Random Access Memory

Abstract: A two-dimensional ferroelectric memory array is combined with a piezoelectric interrogation technique to provide a memory device with nonvolatile storage, random access, non- destructive readout and compatibility with integrated circuits. Binary information is stored as either a positive or negative polari- zation state in ferroelectric ceramic material and is read out by sensing the polarity of the piezoelectric response of the material. Calculations and experimental results are presented for a 5 word X5 bits per word prototype device for which a complete logic and driving circuit has been designed and used. Switching characteris- tics, disturb pulse sensitivity, and changes with temperature are presented. Calculations show that word-to-word capacitive coupling will affect the maximum size of the memory and will probably limit the number of words per chip to approximately 25. No such limit exists on the number of bits per word.

A semiconductor integrated circuit chip structure protected against impact damage from other chips during chip handling

Abstract: A semiconductor integrated circuit chip structure is provided in which one or more bumper projections extending from the active surface of the chip and spaced from the electrical contact projections on said surface functions to protect said active chip surface from impact damage caused by other chips which randomly contact the chip surface during handling procedures particularly when such handling procedures involve placing the chips in random contact with each other in a vibratory article feeding apparatus, such as a vibratory bowl.

Design, development, fabrication and delivery of register and multiplexer units

Abstract: Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated The CMOS standard cell array technique was selected and implemented Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation One of the chip types, multiplexer register type 1, is fabricated on a 0143 x 0123 inch chip It uses nine standard cell types for a total of 54 standard cells This involves more than 350 transistors and has the functional equivalent of 111 gates The second chip, multiplexer register type 2, is housed on a 012 x 012 inch die It uses 13 standard cell types, for a total of 42 standard cells It contains more than 300 transistors, the functional equivalent of 112 gates All of the hermetically sealed units were initially screened for proper functional operation The static leakage and the dynamic leakage were measured Dynamic measurements were made and recorded At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1 At 5 V these units shifted data at a 66 MHz rate The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C