Showing papers on "Chip published in 1972"

Mounting leads and method of fabrication

Abstract: A beam terminal for a semiconductor chip which does not cantilever outwardly from the chip, and which extends no further than the boundary thereof. The beam terminal is adherent to the chip at one position, allowing the remainder thereof to flex with applied stress. The beam terminalled chip thus may be handled using economical mass production techniques.

Method of testing mosfet planar boards

Abstract: A technique of testing a MOSFET planar board in which each of the chips on the planar board can be electronically isolated for individual testing. In MOSFET technology there are two off chip inverters between the output logic blocks and the pins. These are the preoff chip inverter and the off chip inverter. A NOR gate is formed by adding an additional input line to each of the preoff chip inverters of each of the chips on the board, and the output of each of the chips which are not to be tested are driven to logical ones by application of a positive logical level to this input line while no input is applied to the NOR gates on the outputs of the chip which is to be tested. In this manner, all inputs to the chip to be tested are at a one or high logical level, and for test purposes each input to the chip can be brought to a low logical level or left at a high logical level in accordance with the test pattern to be applied. Its output or reaction to the input test patterns is monitored in the normal manner by the chip tester. Through utilization of this technique, the same test patterns which might number three thousand can be applied to the chip such that even though it remains on the planar board it can be tested equivalent to new. In this manner, each chip can be tested and a defective chip on a planar board isolated without mechanically isolating the chips by breaking chip interconnections.

Object handling fixture, system, and process

Abstract: A system for handling an oriented array of objects, such as integrated circuit chips, includes a fixture in which the chips are held in place by vacuum means. A chip placement tube is capable of reciprocal motion normal to the plane of the fixture to move a chip unidirectionally from its position in the array for placement on a substrate. The system further includes means for positioning a substrate precisely with respect to a chip in the array to allow its direct placement from the array. This fixture and system allows the precise orientation and alignment of semiconductor chips in a wafer to be maintained for laser dicing and chip positioning on a substrate without requiring reorientation. When combined with testing and inspection apparatus and a suitable memory, the system further allows handling and processing of chips to be minimized.

Monolithic memory using partially defective chips

Abstract: A monolithic memory which uses both good chips and partially defective chips. For a selected group of chips, for example those mounted on an array card, the defects are limited to the same sector of each chip. When an address signal corresponds to the address of the defective chip sector, logic circuitry translates the address signal to an address at an all-good chip. The data is then written into or read out of the good chip sector instead of a defective chip sector. Provision of a programmable circuit on each array card allows sets of chips, each set having defects in a different sector, to be mounted on different array cards, thereby insuring profitable usage of substantially all partially defective chips.

Chip-forming cutting tool

Abstract: In a chip-forming machining operation improved results accrue from imparting to the chip - in the course of its formation - a longitudinally extending bulge or thickened portion which significantly stiffens the chip and desirably modifies its form. Locating the bulge adjacent the central part of the chip influences a ring-shaped form of chip, while locating the bulge adjacent an edge of the chip results in a cylindrical form of chip having a fairly constant radius of curvature and a great relatively constant pitch. The cutting tool which provides this stiffened chip has a groove or concavity at the locus where the thickened portion of the chip is desired.

Charge-coupled-device analogue matched filters

Abstract: Charge-coupled-device shift registers are used to construct filters matched to both a 13-chip Barker-coded p-n sequence and a chirp signal with a time-bandwidth product of 10. The letter describes the design and fabrication of the devices, and presents preliminary operational characteristics of the filters. A 5 MHz chip rate for the Barker code filter is demonstrated

Ac performance test for large scale integrated circuit chips

Abstract: After the circuit elements are formed in a large scale integrated circuit chip, but before the chip is personalized by a final metallization step in which the circuit elements are electrically interconnected in desired final circuit configuration, all of the circuit elements are temporarily interconnected in a recirculating test loop by a preliminary metallization step. Operating power is then applied to the circuit elements, and the frequency of the resultant selfoscillation of the loop is observed as an indication of the AC performance of the chip. If the chip passes the AC performance test, the temporary recirculating loop connections are interrupted, and the circuit elements are personalized by the final metallization step.

Thermal Chip Evaluation of IC Packaging

Abstract: In order to experimentally evaluate the thermal effects of changes in integrated circuit (lC) packaging, a thermal chip was designed and tested. The thermal chip replaces a working chip in an lC package. It provides a method for measurement of temperatures on a chip where the heat input simulates that of a working chip. Temperature distribution can be obtained by making measurements at 16 locations on the chip. It further provides simulation of the distribution of heat input on a working chip by providing 16 locations for individually controlled heat input. (In fact, there are 32 transistors, grouped in 16 closely spaced pairs, each of which can be powered individually to act as either a "thermometer" or as a heat source thereby giving flexibility to match a working power array). An important feature of this design is the ability to obtain a chip temperature distribution when the chip is encapsulated or mounted facedown. Chip-to-substrata thermal resistances for filled and unfilled epoxy bonding materials were measured. Chip-to-coolant thermal resistances for face-mounted and beck-mounted multibond chips (with beam-type leads) are included. The thermal chip was found to be an effective tool for measuring the temperature distribution on a chip under different power, packaging, and cooling configurations.

Fabrication and operation of a self‐contained bubble domain memory chip

Abstract: This paper describes the fabrication and operation of a 52‐bit bubble domain memory chip designed to test the concept of on‐chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble. All other functions are performed by a permalloy overlay driven by an external rotating field. The metallurgy consists of 200 A evaporated permalloy for magnetoresistive sensors. 4000 A electroplated permalloy for propagation etc., and 6000 A electroplated copper for control lines.

Code translator employing sequential memories

Abstract: The introduction of single wall domains (magnetic bubbles) into coded positions of a pair of domain recirculating loops enables the provision of control signals at anyone of a number of possible time slots with relatively few external wiring connections. The transfer of a domain from each loop of the pair to a control loop responsive to the presence of a domain in a reference stage in each loop permits the formation of a twobubble code in the control loop for determining the timing of the signals. The three loops define a practical translator which can be integrated into a single domain chip.

Apparatus for determining partial memory chip categories

Abstract: There is disclosed an apparatus for determining partial memory chip categories. In the case of 128-cell chips having seven address bits, there are fourteen partial memory chip categories; permanently addressing any one of the seven address lines with a 1 or a 0 produces an effective 64-cell chip, any cell of which can be selected depending upon the address bits extended to the other six address lines. Each address bit of each bad cell on the chip causes a latch to be set as soon as it is determined that the cell is bad. Depending on its value, one of two respective partial chip categories is eliminated. After all cells have been tested the partial chip categories which have not been eliminated are those applicable to the chip, and they can be determined immediately from the settings of the latches.

Electrical component having an attached lead assembly

Abstract: A ceramic chip capacitor is dipped in conductive termination paint so that there is a complete band of the conductive material all the way around the end of the chip and on the end surface. Leads having a nailhead type end that has larger overall dimensions than the end of the chip are soldered to the conductive end termination of the chip. A solder fillet forms all the way around the chip to the nailhead lead and extends over the edge of the chip producing a mechanical saddle all around the chip that provides an advantageously strong bond therewith.

Half good chip with low power dissipation

Abstract: A memory array chip constructed from field effect transistors (FET) which is particularly suitable for use in systems wherein only a portion of the total memory capacity of a chip is used. The chip contains two or more separate memory arrays, each substantially isolated from the others. If one of the arrays is not to be utilized, power may be removed therefrom.

Reliability and organization of a 108‐bit bubble domain memory

Abstract: This paper describes the conceptual design of a highly reliable 108‐Bit Bubble Domain Memory for the Space Program. The Memory has random access to blocks of closed‐loop shift registers, and utilizes self‐contained bubble domain chips with on‐chip decoding. Tradeoff studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit‐per‐chip basis. The final design, has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a “16‐adjacent” code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (≤ 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 μsec to an 800‐word block and an additional 4 msec (average) to a word.

The inverting cell concept for MOS dynamic RAMS

Abstract: Power consumption can be reduced and refreshing simplified using a unique memory array with one extra run of cells, A 2048-bit chip has access time of 360 ns at less than 150 mW dissipation.

A single-chip television IF system

Abstract: This paper describes the integration of a composite television IF system onto one chip in a 24-lead DIL package. The video IF amplifier, synchronous detector, video amplifier with noise inversion, and gated AGC functions are included together with a limiting amplifier and quadrature detector that can be used as a sound detector or AFC generator. The problems associated with stabilizing the high gains required and incorporating all of the IF function into 24 pins are discussed and the solutions described.

Digital system for reclocking pulse code modulation circuits

Abstract: Time division multiplexed pulse code modulated digital character signals received from a transmission medium are demultiplexed and converted into respective delta modulation signals in accordance with a first set of time base information derived from the pulse code modulated signals. This operation removes pulse code character and time division frame time restrictions. The delta modulated signals are recoded to a predetermined pulse code modulated format, such as differential pulse code modulation, in accordance with a second set of time base information for appropriate further processing or transmission.

A 150 NSEC access, 1024 word by 1 bit p-channel switched capacitor RAM

Abstract: IGFET switched-capacitor memory cells form the heart of a fully decoded dynamic. 1024-word by 1-bit p-channel random access memory. With 10V drive circuitry, chip access time is measured to be 150 nsec and cycle time is 300 nsec. On-chip power dissipation at a 300 nsec cycle is 100 mW (100 mW per bit) and is correspondingly lower at lower speeds. Refresh power at 100°C is less than 1 µW/bit.

Testing bond strength of semiconductor device assemblies

Abstract: A test method and apparatus for stressing beams leaded semiconductor device structures bonded to substrates is disclosed. A diffuser in close proximity to the chip surface causes a lower pressure on top of the chip than on the bottom because of gas flow out of the diffuser from the enclosing pressurized chamber. This creates a net force on the chip tending to lift it from the substrate. Varying the space between the chip and diffuser surfaces allows stepless control of the stress level applied to the chip, analogous to centrifuging. The force applied to the chip is typically increased to a predetermined value which is defined, using an established calibration technique, by the chamber pressure and the gas flow rate. However, forces great enough to remove the chip from the substrate may be generated if desired. This test method is also suitable for stressing a plurality of chips simultaneously.