Showing papers on "Chip published in 1973"

Flexible carrier and interconnect for uncased ic chips

Abstract: A printed circuit lead frame that functions as a carrier of an integrated circuit (IC) uncased chip for initial handling and testing and later as a means for bonding the chip''s contacts to printed circuitry on a supporting substrate is disclosed. The lead frame includes a flexible insulating sheet member having a plurality of inner via holes arranged in a pattern to match that of the terminal contacts on the associated chip and a plurality of outer via holes arranged in a pattern to match that of the terminal pads on the supporting substrate member. Gold bumps in each of the inner and outer via holes extend beyond the bottom surface of the sheet member to make a conductively bonded contact with the associated terminal contacts on the associated chip and the associated terminal pads on the supporting substrate member while printed circuit leads affixed to the top surface of the sheet member conductively intercouple associated pairs of inner and outer gold bumps to complete the electrical coupling of the associated chip to the supporting substrate member.

An 8-k bit random-access memory chip using a one-device FET cell

Abstract: Describes the design, fabrication, and testing of an 8192-b p-channel fully-functional random access memory. Novel features of this device are discussed. Among these are the following: inversion layer capacitor one-device cell; the use of a high speed buffer to maximize data transfer; and a minimization of cell pitch limitations through the use of a unique word system circuit design. Performance, power, and yields are also discussed.

Digital integrated circuits

Abstract: In order to eliminate the expense of dicing an integrated circuit into chips, testing the chips, selecting, packaging and retesting the chips, the wafer is left undiced and each chip includes switching and control circuits which enable a chip to be linked to any one of its neighbours. A chain of good chips is built up by sending control signals down the existing part of the chain (which starts with one chip) to cause a new chip to be added to the chain. Test signals are then used to ascertain if the added chip is good. If it is the next chip is added; if not, the chip is disconnected and the control signals utilised to select another neighbouring chip as the added chip. Faulty chips are thus simply by-passed by the chain which is built up of good chips only to form a long shift register for example. Grids of power and clock lines are provided to all chips and a fast data line grid may be used for accessing all chips in a content addressable memory application.

Injection-coupled memory: A high-density static bipolar memory

Abstract: The design of a new static bipolar memory comparable with dynamic FET storages in density, but superior in performance and power dissipation is discussed. The concept of direct minority carrier injection is utilized for both the cell current supply and the coupling to the read/write lines. This has led to an extremely high degree of device integration resulting in a cell size of 3.1 mil/SUP 2/ using a standard buried layer process with 5-/spl mu/ line dimensions and single layer metallization. Investigations on exploratory chips containing small arrays have fully verified the feasibility. The cells have been operated at an extremely small d.c. standby power of below 100 nW. For a 4K b chip of about 160/spl times/150 mil/SUP 2/, an access time around 50 ns can be projected from the measurements simulating a 64/spl times/64 bit array. An extrapolation of the memory cell layout with oxide isolation and self-aligned N/SUP +/ contacts has resulted in a 1.1-mil/SUP 2/ cell with 5-/spl mu/ line dimensions.

Monolithic capacitor having corner internal electrode terminations

Abstract: A monolithic ceramic capacitor has its alternate internal electrodes terminating in opposite corners of the ceramic chip, so as to facilitate the application of external metal terminations by automatic metallizing equipment. This internal electrode arrangement, especially useful in a square-shaped ceramic chip, eliminates the need for chip orientation prior to the introduction of the chip to automatic metallizing equipment. The finished chip, when metallized in either of the two possible orientations, is physically and electrically identical.

Multi-chip calculator system having cycle and subcycle timing generators

Abstract: An electronic protable calculator implemented in integrated circuit semiconductor technology utilizes cycle and subcycle timing generators on both the arithmetic chip and on the memory chip. One output terminal conveys both an internal operating condition of the arithmetic to other semiconductor calculator chips in the system including to the memory chip, and also conveys timing synchronization for the cycle and subcycle timing generators on the memory chip. The arithmetic chip also has means for generating a multi-bit command signal comprising a first set of bits representing internal conditions of the arithmetic chip and a second set of bits selectively representing a memory address location dependent upon bits in the first set.

Microwave power transistor chip carrier

Abstract: A low-cost mounting assembly for a microwave power transistor chip used in hybrid circuits, which minimizes package parasitics while allowing adequate heat transfer from the transistor chip to a heat sink formed from insulating material. The assembly can be formed entirely by silk screen techniques which materially reduces its cost.

1024 bit bubble memory chip

Abstract: A 1024-bit bubble memory chip having a storage density of 15 × 106bits/in2has been designed, fabricated, and tested The chip organization consists of two identical, independent, 512-bit major-minor-loop configurations All device functions have been operated at the chip level at 500 kHz The bubble chip has been mounted in a ceramic module assembly containing a sense amplifier chip, the in-plane field coils, and the permanent-magnet bias field All device functions have been operated at the module level at 100 kHz, and the nonvolatility capability has been established

Bingo type chip dispenser

Abstract: An open based plastic tube carries the disc-like chips stacked therein and these are prevented from discharge through the base by a pair of small projections on the inner wall near the base. Manipulative pincer-type means engage through the side walls of the tube just above the base and when these are actuated, the prongs engage between the lowermost chip and the one next above thereby forcing the lowermost chip past the projections so that it discharges through the base. When the manipulative means is released, gravity moves the stack of chips down the tube so that the next chip is ready for dispensing. An alternative embodiment has a pair of pivotal jaws in the base thereof with legs extending downwardly below the base so that the tube can be pressed upon a supporting surface thereby discharging one chip at a time each time the tube is depressed.

A static random-access memory with normally-off-type Schottky barrier FET's

Abstract: A large-scale integrated memory with lower power consumption and high operating speed has been developed and evaluated. A fully decoded 256-b static random-access memory chip was fabricated by using the Enhancement-type Schottky Barrier gate FET's, having a threshold voltage of 0.1 V, obtained by ion-implantation. The memory chip was successfully operated with an access time of less than 150 ns, and with active power consumption of 15 mW/chip. A single power supply of -1.3 V and current mode logic input levels are additional features of the memory chip.

A Programmable Surface Acoustic Wave Matched Filter for Phase-Coded Spread Spectrum Waveforms (Short Papers)

Abstract: A programmable surface acoustic wave (SAW) matched filter for biphase-coded spread spectrum waveforms has been constructed using a temperature-stable ST-cut quartz tapped delay line (TDL) and silicon-on-sapphire integrated control circuits. Construction is hybrid with wire stitch bond interconnections between the acoustic and microelectronic portions of the device. The SAW TDL operates at 120-MHz center frequency with 100-ns spacing between adjacent taps for a 10-MHz chip rate. The output of each tap can be individually switched to a load with 0 or 180/spl deg/ phase shift by the silicon-on-sapphire integrated control circuits. The high-speed capability of silicon-on-sapphire integrated circuits allows programming (code changing) to be achieved with a serial data input at 10-MHz rates, while the low temperature coefficient of ST-cut quartz allows satisfactory operation over a wide temperature range (-25/spl deg/C to +85/spl deg/C).

Dynamic random access memory including circuit means to prevent data loss caused by bipolar injection resulting from capacitive coupling

Abstract: A dynamic random access memory utilizing MOSFET transistors formed on a single semi-conductor chip is described. The random access memory utilizes 1,024 binary storage cells arrayed in rows and columns. Each row of cells has a read line and a write line. Each column of cells has one data line used for both read and write functions. Each cell is comprised of a write transistor and a pair of read transistors. The write transistor couples a capacitive storage node to the data line and is controlled by the write line.

A monolithic light-emitting-diode display

Abstract: A monolithic 5 × 7 array of planar diffused p-n junctions in GaAs 1-x P x (x≃0.38) has been built for a light-emitting diode (LED) alphanumeric readout. A character formed by this readout is 0.246 cm high and 0.170 cm wide. The monolithic chip has all p-n junctions, n-contacts, p-contacts, interconnections and terminal metallurgy on the epitaxial layer which represents a departure from the conventional methods of making LED arrays, namely wire bonding discrete chips with contacts on two sides in a hybrid configuration. Each LED in the array is connected to one of the terminals arranged around the periphery of the chip and individually addressed by direct current from a driver on a silicon control chip. For each character position in a display there is one monolithic LED chip and one monolithic silicon control chip solder joined to terminals on a glass plate and interconnected by Cr-Cu-Cr lines evaporated onto the glass substrate. The display is addressed by serial information provided from an ROM which is read into a 35-stage shift register on the control chip which controls the drivers. Thus with two standard parts, any N-character display can be fabricated with considerable reduction in handling since no discrete elements or wire bonds are used.

Multi-chip latching circuit for avoiding input-output pin limitations

Abstract: A multi-chip latching circuit comprising first and second chips each including a respective latching circuit and a third chip including a logic circuit which functions as an OR circuit for rising input signals and as an AND circuit for falling input signals. The output signals from the first two chips provide the input signals to the third chip. The three chips, in combination, act as a single composite latching circuit responsive to a plurality of set signal inputs and a plurality of reset signal inputs. The total number of set and reset signal inputs, are divided between the first and second chips with one chip receiving at least one set signal and its associated reset signal and the other chip receiving the remainder of the total number of set and reset signal inputs. There is no direct signal connection between the first and second chips.

Acoustic Signal Processing Devices.

Abstract: : ING, Correlation techniques, Transmitter receiversAcoustic surface waves, Lithium niobatesThe objective of this program was to develop the analytical and experimental techniques required to implement phase coded filters with surface wave delay lines. The scope of the program was also extended to apply this technology to the development of a transceiver system that would demonstrate the principles of spread spectrum communications. This report includes an analysis of the various error sources in surface wave delay lines and their impact on the correlation properties of bi-phase coded waveforms. Response characteristics of an improved set of 127 chip delay lines made on lithium niobate substrates is also reported. The development of an experimental spread spectrum transmitter/receiver system is discussed in detail and the problems encountered in developing the 508 tap phase coded delay lines used in this system are also reviewed. The report concludes with recommendations for future transceiver designs using surface wave delay lines as the prime signal processing elements. (Author)

Drum printer control

Abstract: Control of a drum printer by signals from an LSI/MOS calculator chip. Drum generated signals and control signals generated on a second LSI/MOS chip operating in synchronism with the calculator chip selectively provide for actuation of a line of print hammers. Further, two channels coupling the calculator chip to the control chip provide for flow of coded character words and function words for printing of both functions and characters on a given line. Further, control of the printer is accomplished by observing which digit time in the calculator chip a specific dedicated flag is set.

The Effects of Package Parasitic on the Stability of Microwave Negative Resistance Devices

Abstract: The results of investigations of the effect of parasitic package elements on the behavior of negative resistance smpliliers are presented. Three different package styles were considered. Also two different lead configurations were used, The packages were all mounted in 7-mm coaxial transmission line. The impedance of packages with and without leads was mea- sured from 4 to 18 GHz using a manual network analyzer. These data were used as the basis for calculations to determine the values of elements in a simple three-element equivalent circuit model of the package. Using the equivalent circuit model experimentally derived for each package style, the impedance seen by the chip through the package to a 50-Q load was calculated. Broad-band curves of the impedance seen by the chip are presented. The experimentally derived model of the package permits matching of chip and package for stabMy. T RANSFERRED electron (TE) and IMPATT devices operated as amplifiers are now being considered as possible replacements for traveling-wave tubes in ap- plications where moderate power output, reasonable noise performance, and solid-state reliability are needed. Stability, or freedom from oscillation, is often important to the system designer, Stable active devices are important to the amplifier builder as well, because the impedance of a stable device can be measured directly. Knowledge of the device impedance facilitates accurate circuit design. Establishing experimentally the proper conditions for stability is difficult, given the broad-band negative resistance characteristics of TE or IMPATT devices. An important factor affecting the stability of the negative resistance device is the microwave impedance of the package in which the device is mounted. The purpose of this paper is to help the amplifier designer choose a device package which provides the RF con- ditions for stable operation. The paper consists of two main parts. First, the effects of the RF circuit, and especially the package, on negative re- sistance chip stability are discussed. Experimental data on a variety of package styles and lead configurations were ac- cumulated during the course of this work. These data are used to provide a picture of the broad-band impedance seen by the active chip at its terminals. The broad-band impedances seen by the chip determine the suitability of certain package styles for use over specific frequency ranges. The second part of the paper presents the results of ex- perimental attempts to stabilize TE devices based on the information obtained in the study of package characteristics.