Showing papers on "Chip published in 1975"

Semiconductor integrated circuit devices

Abstract: A power bus element for use in large scale integrated circuits is described. Each bus element consists, for example, of a chip of silicon having two levels of metallization thereon, one acting as an earth (or ground) return plane and the other providing power voltages. Dependent contacts on the chip make selective contact with metallization over the surface of the semiconductor wafer on which the chip is mounted. A power distribution line consists of a number of such bus elements linked together.

Fabrication of a miniature 8K‐bit memory chip using electron‐beam exposure

Abstract: A fully‐ion‐implanted miniature 8192‐bit random‐access memory chip has been fabricated using electron‐beam lithography with minimum linewidth between 1 and 1.5 μm and advanced Si FET technology. Device structure, processing steps, mask transfer, and reactive ion etching processes capable of fabricating device structures in the micrometer and submicrometer dimensions are described. With a minimum linewidth of 1.25 μm, the memory chip occupies an area of 1.1×1.6 mm with an array density of 5 million bits/in.2 (0.8 million bits/cm2). A typical readout access time of 90 ns was measured on a functional chip.

Plural memory controller apparatus

Abstract: A general purpose digital computer whose architecture provides a set of pointer registers at each memory chip to perform stack operations previously performed on the CPU chip. Bidirectional lines interconnect the CPU chip and the memory chips for transmission and reception of data and control signals. Each memory chip has a circuit for incrementing or decrementing the pointer registers in response to a control signal without the transmission of a data signal from the CPU chip to perform a series of stack operations in the memory chip. Addressable registers are provided in each memory chip for identifying the memory chip (PAGE), storing a mode vector (MODE), and counting the number of times the memory controller was addressed (TIME).

Multilayer ceramic multi-chip, dual in-line packaging assembly

Abstract: A multilayer ceramic, multi-chip, dual in-line packaging assembly comprises a ceramic substrate with a pair of semiconductor chip receiving cavities therein. A metalization pattern partially embedded within the substrate provides electrical paths for semiconductor chip devices joined thereto to external circuitry. Semiconductor chips are joined to exposed pads within the chip receiving cavities. Metalization spaced from and positioned beneath the semiconductor chip devices completes interconnections between semiconductor chip devices. Exposed finger areas are spaced from one another and about the semiconductor chip receiving cavities. Embedded lines extend from the finger areas to external circuitry and interconnection means extend between finger areas. Finger areas on one side of a chip receiving cavity are offset with respect to the finger areas on the opposite side of the same chip receiving cavity but aligned with the finger areas on an adjacent chip receiving cavity to minimize crossover connections as well as the electrical coupling. An identical bonding design for each cavity also results. A lead frame is brazed to the substrate at its edges. A lid is bonded to the top surface of the substrate to hermetically seal chips within the chip receiving cavities thereby completing assembly of the package.

General purpose computer or logic chip and system

Abstract: A general purpose logic chip may be replicated for use to construct both the arithmetic unit and the control sections of a computer or other digital data processing or logic circuitry. The chip includes a number of features which when taken together permits its use for a wide variety of data processing functions, including as noted above, the basic arithmetic logic unit and associated functions in addition to micro-operational code control functions. The chip includes a 4-bit arithmetic unit and four registers associated with the arithmetic unit for handling inputs or outputs to and from the arithmetic logic unit. Mode code terminals are provided to implement micro-program control logic circuitry permitting several of the chips to operate on "bytes" or sets of bits of long digital numbers in parallel, without additional circuitry. A random access memory having 16 words, 4 bits each, is provided with alternative addressing circuits to be conveniently accessed either as a "first-in, last-out stack" or as a random access memory register file, or both. Required timing and control are developed within the chip and associated memories to minimize the need for special or additional control circuitry. Additional flexibility is provided for multiple multiplexing circuitry and circuit implementation permitting direct connection of leads from several of the chip outputs. A number of chips of this single type of chip are employed in the implementation of a large class of computer and other data processing systems, employing input/output functions, memory process functions, as well as arithmetic and central processing unit functions.

The characteristics and decodability of the universal product code symbol

Abstract: Described are the coding and symbol of the Universal Product Code. The symbol code structure, format, encodation technique, and characteristics with their technical tradeoffs are discussed. The symbol is analyzed and evaluated. Decodability is shown to depend on the structure of the code and symbol, the size of the symbol, the precision with which the symbol is printed, the technique of scanning employed, the accuracy with which measurements are made, the decoding logic, and the physical operation of scanning. The relationship between the scan pattern of a fixed head scanner and symbol size is shown.

High density semiconductor chip organization

Abstract: A semiconductor chip layout including a plurality of logic cells arranged in columns. A cell may encompass one of two different magnitudes of area in the chip; and each column contains only cells having the same area. The layout is particularly appropriate for level sensitive logic systems which utilize both combinatorial as well as sequential networks. The combinatorial (combinational) networks are less orderly and require a greater number of selectable input connections, hence more area, than the sequential circuits. The wide and narrow columnar architecture allows a much greater circuit packing density on a chip, resulting in a substantial increase in the number of circuits for a given chip area. Performance is also increased because of the reduced area required by the sequential circuits.

Random access memory read/write buffer circuits incorporating complementary field effect transistors

Abstract: Disclosed is a Read/Write Buffer circuit for a random access memory integrated circuit chip based upon complementary enhancement mode field effect transistor technology.

Semiconductor chip carrier and testing fixture

Abstract: An improved carrier for semiconductor chips is described. The carrier includes a base, a substrate including electrical conductors and a rectangular aperture for receiving the semiconductor chip mounted on the base. A transparent cover is installed over the chip and is retained there by a resilient metallic clip.

Companded pulse-code modulation voice codec using monolithic weighted capacitor arrays

Abstract: Monolithic arrays of binary-weighted MOS capacitors may be used in nonlinear as well as linear A/D and D/A converters A proposed design for a standard 15-segment approximation to the /spl mu/255 law coder for pulse-code modulation (PCM) telephony is presented here Analysis and simulation suggest that a per-channel voice coder should be realizable in a single MOS chip The decoder is similar to the coder

Method and apparatus for programming microprocessors

Abstract: A method and apparatus for programming microprocessors which require machine code program instructions wherein black and white code strips are selectively pasted on a sequential instruction frame along a preprinted address code column, each code strip including a parallel trailer wherein the english equivalent of the instruction is displayed. A photoelecric, parallel reader is mounted on the frame for translation across the frame to sequentially load both the address code and the pasted on binary coded instructions into a static random access memory chip for the microprocessor. The technique thus provides for selective alteration of such program sequences by removing selected instruction strips and replacing such strips with other coded strips as required to modify the routine.

Programmable latch and other circuits for logic arrays

Abstract: This specification describes means that permit the variation of circuits, particularly latch circuits, used in programmable logic array chips (PLAs). The latch circuits are changeable to enable the selection of one of three different latch configurations to be used or in combination on the same PLA chip. The differences in the circuit configurations of the different types of latches occur only in metallization pattern of the chip so that chips with different latch configurations can be manufactured with a minimum of different processing steps.

Standardizable low-pass voice band hybrid circuit filters for pulse code modulation (PCM) communication systems

Abstract: A standardizable design approach to realize the voice band low-pass filters for a variety of pulse code modulation (PCM) communications systems is described. This design concept incorporates cascaded RC active filter sections, thick and thin film hybrid technologies, and functional tuning to allow the use of the same hybrid design for both transmit and receive filters, for a range of input and output requirements. Tuning, sensitivity analyses, and implementation tradeoffs are described. Thick film implementations, using NPO chip capacitors, with the new high stability resistor inks as well as thin film implementation, using the usual tantalum integrated thin film technology are presented. Very stringent requirements have been successfully met using state-of-the-art hybrid technologies.

MOS integrated circuit chip for display panels

Abstract: An MOS integrated circuit chip for both addressing and driving display devices in display panels. The chip includes low-level logic devices for receiving and manipulating data for energizing a selected number of devices in the display panel. An output driver portion is coupled to the display devices and energizes the devices in response to the data received by the input logic. The output driver portion includes a transistor in which the drain region extends deeper into the substrate than the source region of the transistor, as well as the remainder of the active regions in the integrated circuit chip. Accordingly, the integrated circuit chip can withstand a high breakdown voltage at its driver output, while also providing high density logic devices thereby minimizing discrete components and their associated separate electrical interconnections.

Low power mos ram address decode circuit

Abstract: An MOS random access memory chip utilizes a column decode circuit scheme in which a signal derived from a chip select input of the random access memory chip is coupled to the gate of a switching device of dynamic IGFET NOR gates utilized to accomplish the column decoding function. This prevents the bit sense column selection conductor from being affected when an internal column selection clock signal is generated. This results in a substantial savings in power dissipation which would be required if it were necessary to provide circuitry to disable the internal column selection clock generator circuit during an unselected memory cycle.

Voltage level adaption in MOSFET chips

Abstract: A particular voltage level in an integrated MOS chip is maintained by defining that level as an integral multiple of drain-to-gate voltage thresholds and by actively controlling that level in response to deviations therefrom Plural MOSFET elements are connected in circuit so that their drain-to-gate capacitances are serially effective across internal signal lines (eg busses) for bias so as to establish a reference level to be compared with the actual voltage on these signal lines; and through feedback the signal level as applied from outside of the chip to these lines or busses is reduced to obtain the desired multiple threshold voltage as operating voltage on these lines for use by other elements in the chip

Single chip magnetic bubble processor

Abstract: A magnetic bubble processor comprising components for causing the movement of magnetic bubbles and a single chip having a layer of magnetic material in which magnetic bubbles can be moved. The chip comprises an input circuit for conveying electrical data and instructions into the processor and a generator responsive to the input data and instructions for producing magnetic bubbles representing bits of information. Paths are provided on the chip for routing magnetic bubbles within the processor as well as a memory organization accessible for the storage and retrieval of magnetic bubble information. The chip also includes magnetic bubble logic for performing mathematical operations and for providing magnetic bubble output information representing the results thereof. Further, the chip includes a magnetic bubble decoder for deciphering information and providing magnetic bubble output signals determinative of operations the processor is to perform and a magnetic bubble circuit responsive to the decoder output signals for controlling the routing of magnetic bubble information along predetermined paths within the processor, the storage and retrieval of information in the memory, and for instructing the logic as to which mathematical or logical operations are to be performed. A magnetic bubble detector on the chip converts the output of the logic from magnetic bubble information into discrete processor electrical output signals. The converted information is conveyed out of the processor by an output circuit on the chip. Thus, complex programs involving mathematical and logical operations using magnetic bubble data and instructions may be performed on one chip with a minimum of external circuitry and control required.

Fault-tolerant CCD memory chip

Abstract: The invention comprises a CCD memory chip. A CCD chip is comprised of a plurality of arrays, each of which is in turn comprised of a plurality of CCD registers. A serial addressing system may be used to determine which of the arrays is accessed. Fault-tolerance with respect to defective arrays is achieved by the combination of having only the address circuits for properly functioning arrays form the bits of an N-bit addressing shift register, (whereas the address circuits for improperly functioning arrays are shorted such that they do not form a bit of the N-bit address shift register,) and disabling the voltage delivered to a faulty array. The control circuitry includes the address circuitry and further includes means for controllably providing power to the array components. A plurality of arrays comprises a chip having pads for connecting the chip to the rest of the system.

A MOS monolithic chip for high-speed flexible FFT microprocessors

Abstract: This paper will describe a single type of monolithic circuit chip - used as an arithmetic unit - operating in place of multitude of general purpose chips which reduces by an order of magnitude the size, cost, and complexity of the FFT and its derivatives.

Single decoder bubble domain chip organization

Abstract: A unique arrangement of magnetic bubble domain devices is utilized to provide an advantageous chip arrangement. One or more storage registers are associated with a controlling path whereby information, for example in the form of magnetic bubbles, is transferred into or out of the storage registers. The controlling path includes replicate/transfer switches for permitting the bubbles to be transferred into or out of the storage register. A generator and an annihilator are provided for producing or destroying magnetic bubble domains. A single decoder is utilized to determine the action to be taken by the controlling path and, thus, the overall operation of the storage register within the chip. A multiple input detector is connected to receive the information from each of the storage registers and to produce a chip output signal. Electrical means are utilized to control the selective operation of the various components of the controlling path.

Block oriented random access bubble memory

Abstract: A block oriented random access memory (BORAM) magnetic bubble domain system which provides increased throughput of information and reduced access or read time for the same information as compared to existing major-minor or decoder accessed chip organizations which it is designed to replace.

被削材種および切削速度と切りくず生成現象との関係:切りくず生成現象に関する実験的研究(第1報)

Abstract: Orthogonal cutting of eight kinds of the work materials including cast irons, steels and copper alloy was experimentally photographed at the cutting speeds ranging from 10 mm/min to 200 m/min, in order to organize systematic knowledge on the formation, separation and the final shape of the chip. The results of these tests were as follows:The chip formation phenomenon exhibits characteristic variation of its type at various cutting speeds, inherently to the cut metal. Various steels and the brass show similar tendency of chip formation whereas cast irons behave differently. When the cutting speed is increased, the chip formation mechanism changes from crack type to shear type, and from shear type to flow type. The shape of the chip meantime changes from the powder or fragmental chip to the spiral chip, and from the spiral chip to the helical or tangled chip. At low speed, the chip is mostly separated from the workpiece at the point of the tool tip, while, at high speed, it is separated at the place far from the tool tip.

BEAMOS—A new electron beam digital memory device

Abstract: BEAMOS, for Beam Addressed Metal Oxide Semiconductor, is a new technology for auxiliary memories based on an electron beam which reads and writes data on a simple unstructured MOS chip. Its performance features include large bit capacity (> 30 \times 10^{6} bits/module), rapid access time (<30 microseconds), high data transfer rates, nonvolatile storage and low cost in comparison with memories of comparable performance. The memory component is rugged, all electronic, and relatively insensitive to temperature and vibration, making it especially attractive for military applications. Its fast access time should provide considerable performance improvement in both commercial and military computer systems.

Single-mask bubble memories: Bit/Chip organization with decoding

Abstract: Progress in element and chip design of single-mask bubble chips, based on drive-field operation, is reported. Three new elements, which have been successfully operated, are presented. (i) The replicator copies bubble streams for one propagation direction; when used in combination with the sense of rotation of the drive field it can serve as a bit generator. (ii) The λ-creator can selectively shift a bit over one propagation period. It can be applied in a decoder organization which permits rapid access to stored information. (iii) A current-controlled splitter-type generator was designed, which takes current pulses of about 60 mA for creating new bubbles.

High Data Rate Magnetic Memory Devices.

Abstract: : This report presents the results of a system and cost study made to determine the feasibility of developing a bubble domain BORAM chip using existing device components. Due to the short access time requirements the major-minor loop chip organization cannot be used and due to the lack of a decoder of the necessary type with adequate margins, an alternative chip scheme is proposed in which parallel access to storage loops is achieved via separate transfer switches. The feasibility of realizing such a chip is examined from the viewpoint and preliminary designs are proposed. Estimates of the system costs and optimum chip capacity are made based upon a simple yield model for bubble devices. (Author)