Showing papers on "Chip published in 1977"

Performance Evaluation for Phase-Coded Spread-Spectrum Multiple-Access Communication--Part II: Code Sequence Analysis

Abstract: An analysis of the code sequence parameters that are most important to the communication performance of an asynchronous phase-coded spread-spectrum multiple-access communication system is presented. Previously known bounds and computational techniques for such parameters are surveyed. Some new results on mean-square correlation are included.

The chip layout problem: an automatic wiring procedure

Abstract: This paper describes an automatic system for routing the metal connections on integrated circuit chips. The system contains three major sections: global wiring, vertical channel assignment, and horizontal bilateral channel allocation. Since its initial development in 1972, this system has been used successfully at IBM in the physical design of bipolar logic chips.

Semiconductor transducer packaged assembly

Abstract: A semiconductor transducer chip is flip-chip bonded to a semiconductor interface chip, which is mounted on the ceramic package. Thermal coupling between the package and the transducer chip is minimized by the small contact area between the transducer chip and interface chip. Micron size spacing between the spring membrane in the transducer chip and the interface chip produces squeeze film damping of the spring membrane.

Standardized digital logic chip

Abstract: A standardized large scale integrated (LSI) array of standard logic cells on a single complementary metal oxide semiconductor (CMOS) chip. The pattern chosen for the layout of the standard logic cells provides very high cell density and, in combination with the "roadways" provided for power and data interconnects and the availability of "cross unders" within any cell chosen, very high utility ratios of the available cells. The standardized logic chip may be used to implement a large variety of logic circuit designs by the simple expedient of a single custom mask design for the metallization pattern for each unique use.

Spread Spectrum and Time Division Multiple Access Satellite Communications

Abstract: Although time division multiple access (TDMA) satellite communication provides the highest traffic capacity per satellite and offers efficient transmission of a wide variety of services, it suffers from network timing and ranging requirements and message security. On the other hand, spread spectrum multiple access (SSMA) satellite communication is suited for reliable random access and tactical transmission systems. Orthogonal functions such as Rademacher, Haar, and Walsh, or pseudonoise sequence coding of amplitude and phase of the analog message or code division of baseband signals, frequency and time hopping are among the several methods employed for spread spectrum communications. A combination of TDMA and SSMA can be used for asynchronous and reliable transmission of digital or analog signals.

Signature encoding for integrated circuits

Abstract: The present disclosure describes an improved integrated circuit chip which includes in addition to the logic circuits for performing its design function, an additional circuit for providing a unique reference pattern in digital form useful for test purposes. This reference pattern is automatically read by the tester and gives information as to the type of chip and its final signature. The former indicates to the tester an appropriate test routine such as a pseudo-random binary sequence; and the latter, the predetermined digital pattern which will be present on all of the input and output terminals of a properly functioning integrated circuit chip at the conclusion of the test. Since each chip signature is read by the tester itself, no reference to signatures customarily recorded in tables or inscribed on circuit schematics is required by the test technician.

Electrical connections for chip carriers

Abstract: Packaging and interconnecting means for a plurality of microcircuit chips contained in chip carriers comprises a chip carrier socket which is dimensioned to receive a plurality of chip carriers in stacked relationship, one on top of the other. Vertically extending conductors in the socket are contacted by the leads from the chip carriers. In accordance with one embodiment, the several chip carriers are electrically and physically identical and the conductors are shared by all of the chips, excepting one dedicated conductor for each chip carrier. Alternatively, the chips in the chip carriers can be electrically dissimilar in which case only limited numbers of the socket conductors are shared and connections among the several chip carriers in the stack are achieved by interrupting the conductors in the chip carrier socket.

Semiconductor integrated circuit device

Abstract: PURPOSE:To reduce the power consumption of the entire part of a semiconductor integrated circuit device, by composing high, medium and low speed operation circuits to be formed on one chip with one basic circuit and increasing and reducing the resistivity of the basic circuit according to each speed

In-situ test and diagnostic circuitry and method for CML chips

Abstract: An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an "Open" Input Detector to detect open connections or connections that are becoming open between one chip and another; an Output Short Detector to monitor shorts at any chip output; and a Signature Test and Diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a Test and Diagnostic Pin.

Spread Spectrum Multiple Access Communications Experiment Through a Satellite

Abstract: The purpose of this paper is to demonstrate that spread spectrum performance characteristics under different conditions of limiting and audio channel SNR degradation with close separation of carrier frequencies are similar to that of sinusoidal signals. Experiments also show that simultaneous transmission of acceptable spread spectrum and TV signals are feasible.

Design and characterization of a real-time correlator

Abstract: The design and characterization of a real-time correlator/electrically programmable transversal filter is presented, based on a novel functional multiplying structure in a standard single-level MOS LSI process. The analog information is sampled and held at fixed sites on the chip and the tap weights slide past them; the taps are digitized into 7 bits which control the selection of seven binary area-ratioed MOS capacitors per tap position. The rotation of the tap weights can reduce the effect of tap-weight errors but contributes to fixed pattern noise. Experiments using cascaded chips to build longer filters show excellent transfer-function agreement with theory. Dynamic range of the device is limited primarily by fixed pattern noise. This problem has been modeled and at present about a 45-dB dynamic range has been obtained for the heaviest doped chips when driven by input-signal amplitudes which allow better than 1-percent harmonic distortion. With improvements suggested, significant increases are expected in the dynamic range of the device.

Individual chip joining machine

Abstract: An individual chip joining machine is designed primarily to bond a single chip to a multi-chip substrate. The machine includes an X-Y table for moving a substrate to locate a chip site beneath a probe. The probe serves to pick up a chip and either place it on the substrate or remove it therefrom and further serves to heat the chip to join it to the substrate by solder reflow or to melt the solder and allow the chip to be removed. The probe is mounted on a Z direction placement mechanism that also includes means to allow the probe to be backed off a fixed distance from a chip, once the chip has been placed on the substrate preparatory to joining thereto. A second heater heats the substrate to a bias temperature, this heating being controlled through use of a surrogate substrate having a thermocouple attached thereto.

Engine chip detector

Abstract: A transistorized engine chip detection system including a milliammeter to give a visual indication of chip buildup and a full light to operate at a critical preset level, utilizing a voltage divider network, a decrease in resistance in the chip detector will cause an increase in current flow, and subsequent lighting of a warning light. A short circuit or large chip would turn light on and give full scale meter reading, broken or unplugged harness turns light on and gives zero meter reading.

Four phase to two phase correlator

Abstract: A four phase to two phase correlator is incorporated within the demodulator section of a spread spectrum modem to process a received RF signal modulated by a transmitted PN code and a digital data signal The correlator includes a first modulator for combining the channel 1 and channel 2 R code signals with the received RF input signal to generate a first channel 1 RF signal and a first channel 2 RF signal The first channel 1 RF signal is modulated by the transmitted PN code signal, the channel 1 R code signal and the digital data signal The first channel 2 RF signal is modulated by the transmitted PN code signal, the channel 2 R code signal and the digital data signal A second modulator combines the channel 1 and channel 2 PN code signals and the channel 1 and channel 2 R code signals with a first unmodulated RF signal to generate a second channel 1 RF signal which is modulated by the channel 1 PN code signal and by the channel 1 R code signal, and a second channel 2 RF signal which is modulated by the channel 2 PN code signal by the channel 2 R code signal A third modulator combines both channels of the first and second RF signals to generate a third RF signal which is modulated only by the digital data signal

Method and devices for localizing flat chips on a carrier plate

Abstract: Small reference marks near two corners of a circuit chip in the form of optical gratings in which the grating lines of both reference marks are parallel are illuminated alternately by a laser beam which is projected in the location the reference marks would have if the chip is properly located. Detectors are arranged to pick up the first secondary maximum of each diffraction pattern when the chip is properly located on its carrier plate. Failure of the detectors to respond indicates a chip that must be removed. With a beam-splitting arrangement producing four closely bunched light spots, straddling each of the reference marks, and an appropriate number of detectors, directional error signals are obtainable by which mechanical correction movements can be controlled for automatic localization of the chip. The gratings may be produced at the same time as the integrated circuit as among the surface features of the chip or they may be impressed into the solder beads at the corners of the chip by which the chip is made fast to the carrier plate.

Data processing unit

Abstract: PURPOSE:To provide a semiconductor chip which has capability as much as mini computer has by overcoming the restriction given for numbers of pin on the semiconductor chip, and also overcoming the restriction given for a size of chip

Production method of semiconductor device

Abstract: PURPOSE:In order to prevent the adhering of resins on each electrode section being projected on the outside of mold resin layer, in the production method of a semiconductor being plastically molded with its installing portion of IC chip being installed on a leadframe

Output address decoder with gating logic for increased speed and less chip area

Abstract: A Y address decoder used in conjunction with an X-Y matrix array, high density read-only memory unit, that reduces the number of series FET stages in the electrical path needed to evaluate the logic state of an addressed cell location of such a read-only memory unit. The reduction is achieved by gating logic in which the signal stored in the evaluated cell location, is derived from the output terminals of a tier of decoders, the appropriate decoder being connected directly to an output driver by a gate-controlled switch. The gate signal to render each such switch conductive is generated by an AND-OR circuit in repsonse to a unique Y address code, thereby obviating the otherwise time-consuming requirement for the evaluation signal to flow through additional tiers of decoders.

An experimental system for power/timing optimization of LSI chips

Abstract: An experimental system of programs is described which places logic gates on a chip, globally wires the gates and then optimizes the power required to drive them. Further power reductions are realized by using power-oriented placement improvement techniques. A companion paper describes how the optimization is accomplished by using the timing requirements of the chip as constraints and assigning delays to the logic gates so that these constraints are met and the power is minimized.

Air temperature sensor connection assembly

Abstract: A fast response fluid temperature sensor is disclosed which consists of a silicon temperature sensing semiconductor chip mounted on an extremely thin fin having a high surface area to mass ratio The fin and chip combination are mounted in a frame assembly, with the thermal conductivity of the frame assembly being high and the specific heat being low for maximum heat transfer from the fluid being sensed to the silicon chip The chip and fin assembly are illustrated as being open to the free flow of fluid around the assembly, no insulating material being provided between the fluid media being sensed and the fin and chip assembly, and a protective cage is formed around the fin and chip assembly Suitable connection is made between one electrical terminal of the chip and the fin and between the other electrical terminal of the chip and the external circuitry, with various modified forms of such connections being illustrated

Automatic chip or button placer

Abstract: A device for storing in a column chips or buttons or the like, and dispensing the same through the bottom of the device, by a selection of either of two different means one of which is a depressible finger piece and the other a depressible plunger actuated by placing the device against a table top or other flat object.

One chip direct drive and keyboard sensing arrangement for light emitting diode and digitron displays

Abstract: A circuit having two modes of operation for driving either one of a light emitting diode or a gas discharge tube (digitron) display from a single semiconductor chip. Respective voltages are supplied to the chip to enable the circuit to selectively operate in either of the light emitting diode or digitron modes.

High Temperature Thermal Characteristics of Microelectronic Packages

Abstract: This paper describes results of the computer-analysis pottion of a research program which was conducted to study the thermal characteristics of microcircuits in high temperature environments. A special IC chip, bonded to an alumina chip carrier, was modeled for these simulations. It was found that thermal resistance values and thermal time constants nearly double when the chip carrier temperature is increased from 70 to 257°C. For a chip power dissipation of 1.5 W, the peak junction temperature increased from 138 to 385°C, an increase of 247°C, while the chip carrier only increased by 187°C. The thermal time constant of the junction peak temperature rise, measured relative to the chip carrier, increased from 15 to 26 µs over the same temperature range.

Fast response temperature sensor

Abstract: A fast response fluid temperature sensor is disclosed which consists of a silicon temperature sensing semiconductor chip mounted on an extremely thin fin having a high surface area to mass ratio. The fin and chip combination are mounted in a frame assembly, with the thermal conductivity of the frame assembly being high and the specific heat being low for maximum heat transfer from the fluid being sensed to the silicon chip. The chip and fin assembly are illustrated as being open to the free flow of fluid around the assembly, no insulating material is provided between the fluid media being sensed and the fin and chip assembly, and a protective cage is formed around the fin and chip assembly. Suitable connection is made between one electrical terminal of the chip and the fin and between the other electrical terminal of the chip and the external circuitry, with various modified forms of such connections being illustrated.

Tunable extended range chip capacitor

Abstract: A tunable, extended range, multilayered ceramic chip capacitor for incorporation into a plurality of substrate designs of micro-miniature circuitry and hybrid integrated circuits, comprising a multilayered ceramic chip capacitor; said chip having an electrode pattern as both upper and lower electrode layers embedded within the dielectric, forming a homogeneous chip capacitor structure. The capacitance range of the said chip capacitor is extended by the addition of a rotor plate positioned over a portion of said electrode pattern by a rotor contact spring which also provides a rotor contact terminal, such that said rotor plate may be rotated over the stator portion of said electrode pattern to provide a precisely tunable extended range of capacitance, a stator terminal spring to provide means to grip said extended range chip capacitor and means for circuit connection.

Heat dissipation construction of multichip mounting substrate

Abstract: PURPOSE: To improve the heat dissipation efficiency of a multichip mounting substrate by providing metalstuds through a wiring substrate, providing a required IC chip to one end thereof and mounting a fin to the other end. COPYRIGHT: (C)1978,JPO&Japio

Inverted transistor circuits for monolithic integrated circuit application

Abstract: A plurality of inverted transitor current mirror and pull down circuits are disclosed which are suitable for providing current mirroring and base pull down functions in a variety of integrated circuit applications The use of the inverted transistor as a current mirror is also utilized in gaining and/or level shifting any differential or single-ended analog or digital signal The use of a multiple emitter inverted transistor for providing multiple pull down reduces to a fraction the chip area otherwise required by the use of multiple transistors