Showing papers on "Chip published in 1978"

Multiple word/bit line redundancy for semiconductor memories

Abstract: Multiple word/bit line redundancy techniques at the chip level are shown to be powerful enough to obtain good yields for chips with much higher rates of faults/chip than without redundancy. This is possible because, in many instances, chips which are rejected as being bad still have a high percentage of usable bits on them. The redundancy techniques described consist of putting spare decoders and spare word and bit lines on a chip in order to be able to replace defective lines of the chip with good lines while still maintaining the same address. Based on a first-pass design of a 16K chip, a significant improvement in the number of usable bits per wafer appears possible. The leverage for improvement is shown to be strongly dependent upon the type of cell, the layout, and the technology used.

Orthogonal spread spectrum time division multiple accessing mobile subscriber access system

Abstract: A time division multiple access mobile communications system employing frency division multiplexing and perfect noise codes to enable utilization of the system. A central node, or repeater, is employed, with all transmissions to it being performed at a first frequency, and with the frequency division multiplexing being such that all re-transmissions from the central node are performed at a second, different frequency. The noise codes employed are of a type termed code mates having correlation functions which upon detection provide an impulse autocorrelation function. The described arrangement enables random access, or direct call-up, to be accomplished with total non-interference between users. Large improvements in signal-to-noise power ratio and in signal-to-jamming power ratio will be seen to result.

Method and circuit for checking integrated circuit chips

Abstract: Method and circuit for checking integrated circuit chips without the use of external checking circuits. Chips are fabricated with an error-checking circuit on each chip. Data from data processing logic on each chip is outputted via a first path to one input of its respective checking circuit and via a second path to an output pin or pins. The output pin on each chip is also connected via a third path to the other input of its checking circuit. The input and output pins of each chip are wired in parallel. A separate check input pin is provided to each integrated circuit chip. On one chip this pin is activated, making this first chip the checker. On the other chip, the check input pin is deactivated. On the chip which is the checker, the output from the data processing logic is prevented from being passed externally via the first path, but is allowed to enter the checking circuit via the second path. The output from the other chip, which is wired in parallel with the first chip, enters the error-checking circuit on the first chip via the third path. The outputs from the first chip and the second chip are thus checked with respect to each other in the error-checking circuit, and if they do not check properly an error output is generated, indicating that one of the data processing logic circuits is faulty.

Master image chip organization technique or method

Abstract: Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions. In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance.

System for chip joining by short wavelength radiation

Abstract: Defective chips are removed from a substrate package. The package is cleaned. Replacement chips with solder bearing elements are replaced in the position(s) of the defective chip(s). Silicon chips are less damaged by heating with light wavelengths substantially shorter than infrared radiation, when the radiation is directed upon the upper chip surface and the lower chip surface carries circuitry and solder balls. Radiation is absorbed by the upper chip surface and converted there directly to heat, protecting the circuitry below. An argon-ion laser beam confined to a given chip is directed upon the upper surface of the chip to be soldered in place. A thin laser beam can be scanned under computer control across a chip to heat the areas of a chip above solder balls. Automatic temperature control of the chip can be provided by a heat detector or chip condition detector and a program controller in a feedback loop controlling laser power.

A Monolithic 14-bit D/A Converter

Abstract: A monolithic 14-bit D/A converter using "dynamic element matching" to obtain high accuracy and good long-term stability is described. The chip, with a size of 3.1×3.2 mm, contains all elements needed except the output amplifier and a digital input latch.

Measurement and Generation of Error Correcting Codes for Package Failures

Abstract: Error correcting codes have been successfully employed to correct errors associated with failures in computer memories. A typical code which has found wide application is the binary Hamming code. This code corrects single bit errors. With the advent of large-scale integration (LSI) storage array technology, the likelihood of errors which exceed the correction and detection capability of such a code is significant. A serious and heretofore unanswered question is the error detection capability of a given code which is implemented and decoded for single error correction, particularly when a storage array chip or card carrying multiple bits from the codeword has failed. In order to identify this capability, a new reliability parameter called package detectability is defined. This paper also presents a method for computing package detectability. The analysis has been performed on a number of codes in order to optimize the packaging for maximum detectability. In addition, a class of distance 3 codes with maximal b-bit package detectability is given.

Logic chip test system with path oriented decision making test pattern generator

Abstract: A path oriented decision making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines. For each designated possible chip fault, consisting of a stuck-high or stuck-low voltage at a node of the chip logic network, the generator provides a test pattern of signals to be applied to the input pins of each chip, so that the resulting signal at an output pin indicates whether the fault is present in the chip.

Test circuitry for module interconnection network

Abstract: This specification deals with testing of a network of electrical interconnections between chips mounted on an insulative substrate of a module and between the chips and the input and output pins of the module. Each of the mounted chips contains masking circuits which can be activated to prevent controlling signals from the outputs of logic circuits on the chip from being transmitted off the chip and into the interconnection network. Also each of the chips contains emitter follower circuits that logically connect all the chip input terminals to a common output terminal of the chip. In testing the mask circuits are activated. Then potential levels are selectively applied to a plurality of test points in the interconnection network and differences in potential level between these test points and/or between the points and one or more of the common terminals are determined.

Integrated optical spectrum analyzer: an imminent `chip'

Abstract: Discusses the developments of integrated optics and in particular the fabrication of a spectrum analyzer-a key circuit in electronic warfare.

An experimental 64-bit decoded Josephson NDRO random access memory

Abstract: The design and testing of an experimental fully decoded 64-bit Josephson NDRO (nondestructive readout) RAM chip are described. Tree decoders were used to access the memory cells. The basic memory cell was a ring cell containing a single write gate. The chips were built in a coarse 25 /spl mu/m technology since neither speed nor density were stressed in this study. An access time of 4 ns with full margins and of 2.3 ns with reduced margins were demonstrated. The corresponding full memory cycle times were 5 and 3.5 ns, respectively. Good agreement with computer simulations was obtained throughout.

Speech synthesis integrated circuit device

Abstract: Disclosed is an integrated circuit device or chip which digitally synthesizes human speech using a linear predictive filter. This device may be implemented using conventional processing techniques. For instance, when implemented in conventional P-channel MOS technology, the disclosed device or chip has an active area of approximately 45,000 square mils.

Magnetic domain packaging

Abstract: A magnetic bubble device is provided comprising a substrate, a device chip and interconnecting conductors for connecting the device chip to the substrate and for supporting the device chip on the substrate so that by providing a hole in the substrate and turning over the device chip, the active surface of the device chip is arranged substantially co-planar with the top surface of the substrate, thereby enabling a reduced height device to be obtained.

A fully integrated five-gyrator filter at video frequencies

Abstract: An experimental single-chip silicon integrated-circuit filter is described for use in color television receivers. It comprises five gyrator resonators operating in the range 4-6 MHz. This chip provides all the selectivity required to separate the sound, luminance, and chrominance components from the composite video signal, and is tuned by a single bias potential applied to the p-n junction capacitors on the chip. The chip replaces an equivalent LC filter of about 20 discrete components (coils, capacitors, and resistors) which are bulky, are relatively expensive, and suffer from the need for individual screening and alignment. The theory of gyrators related to providing fully integrated selectivity at high frequency is outlined. Performance boundaries in terms of Q-factor, frequency setting accuracy, noise, distortion, and temperature are considered. Design aspects are discussed, first for a gyrator and then for the complete experimental filter chip.

Fast Synchronization in a Spread-Spectrum System Based on Acoustoelectric Convolvers

Abstract: A wideband PN spread-spectrum modem has been implemented using a pair of acoustoelectric convolvers as programmable matched filters in combination with digital delay and coincidence gating. The convolvers provide the capability for fast synchronization of a burst-format message during a short 13-bit preamble. The spreading code is different for every preamble and data bit of a message. (Conventional receivers often require long synchronization times for non-repeating preamble codes or require the same code to be repeated for every preamble bit.) Efficient algorithms have been developed for coarse synchronization and bit alignment of the received signal and reference in each convolver. The modem achieves coarse synchronization to a precision of one PN chip using only four preamble bits with an effective correlation loss only 1.5 dB from ideal. Alignment of the coded bits within the convolver interaction region for subsequent DPSK data detection is achieved by shifting the reference time base. Fine synchronization of the receiver for a data sampling precision of one-eighth of a PN chip is completed at the end of the 13-bit preamble. Message data modulation is DPSK and spreading modulation is MSK. Receiver performance in the presence of wideband interference has been measured to be within 1.5 dB of theoretical predictions.

Reliability Evaluation and Failure Analysis for Multilayer Ceramic Chip Capacitors

Abstract: Reliability evaluation tests for multilayer ceramic chip capacitors mounted on a hybrid IC were implemented. Failure modes, failure mechanisms, and drift of characteristics were analyzed. Humidity acceleration as well as voltage and temperature accelerations were investigated to estimate the chip capacitor reliability. The chip capacitor reliability proved to be high and adequate for the service period of the communication system.

Means for coupling incompatible signals to an integrated circuit and for deriving operating supply therefrom

Abstract: An on-board integrated circuit chip signal source which allows operation of the chip from previously incompatible and excessively high amplitude signal sources, and as well powers the chip from such sources as the input signal, a clock, etc. The invention utilizes a 3 plate capacitor, with the bottom plate formed of a heavily doped region of the silicon substrate. Signal is applied between the outside plates of the capacitor and a proportion of the signal is received between the center plate and one of the outside plates. A diode clamp connected between the center plate and a reference potential fixes the derived peak and average signal levels.

A 300 kbit bubble memory chip with planar structure

Abstract: A 300 kbit bubble memory chip has been designed based on 3 μm bubble technology. Nominal circuit period is 14 μm and chip size is 9.8 mm×9.6 mm. A gap‐tolerant design is fully employed, such as, asymmetric half‐disk propagation pattern, half‐disk transfer gate, a novel asymmetric‐chevron stretcher, etc. The chip is fabricated using a new planar process solving step‐coverage problems to achieve good process yield. A typical bias field margin of 18 Oe is obtained at 55 Oe with a triangular wave drive.

Spread Spectrum Acquisition and Tracking Performance for Shuttle Communication Links

Abstract: The spread spectrum acquisition and tracking performance for the Shuttle S -band and Ku -band communication links are analyzed and compared to test results. The S -band link requirements are more severe than those of the Ku -band links, hence, different despreader designs were developed for the two systems. The S -band despreader acquires pseudonoise code lock by examining all possible code phases in half chip steps while the Ku -band despreader acquires pseudonoise code lock by continuously sweeping a tau-jitter loop. Both despreaders employ a tau-jitter loop for code tracking. The code tracking performance is computed for the tau-jitter loop and compared to that of the more complex delay lock loop.

High-Frequency Measurement of Q-Factors of Ceramic Chip Capacitors

Abstract: No reliable instrumentation systems have been available for the measurement of capacitor properties, particularly Q-factor, in applications requiring operation in the 100-1000 MHz range. The production of large numbers of multilayer ceramic chip capacitors for such special use is a very recent development. The need for reliable measurement equipment is increasing both for purposes of device evaluation and device development. A high-Q transmission line has been constructed, and a mathematical system has been devised for employing that line in a resonant mode to determine capacitor parameters, and particularly Q-factor, at the range up to and including microwave frequencies. The device produces accurate reliable data. The equipment can be reproduced and the system can be used in analysis and evaluation with a degree of confidence not possible in the past.

LSI Processor for Digital Signal Processing and Its Application to 4800 Bit/s Modem

Abstract: This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the type A \times B + C \rightarrow D and the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10-5at S/N = 17.6 dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.

A two-chip CMOS CODEC

Abstract: A staightforward answer to the per-channel CODEC question has been obtained by a CMOS chip pair operating on the capacitive charge redistribution technique. Designed especially for the D4 channel bank, but ideal for various PCM telephone systems and other applications, the compressing A/D converter and expanding D/A converter produce the standard digital approximation to the μ-255 characteristic without the requirement of external components; all analog and digital functions are integrated. The advantages of the per-channel over the shared CODEC are manifest; the configuration separating the two asynchronous conversions maximizes versatility and ease of application.

A modular, high-speed serial pipeline multiplier for digital signal processing

Abstract: Describes the design and implementation of a 44 Mbit/s serial pipeline multiplier that exploits an efficient algorithm with a novel circuit architecture. The multiplier, intended for use with signed-magnitude coefficients and two's complement data of arbitrary length, produces products automatically rounded and truncated to the same length as incoming data. The circuit's design focuses on the bit-cell, a unit of circuitry associated with one bit of the coefficient word, from which multipliers of arbitrary complexity may be constructed. A practical realization of this multiplier contains four bit-cells, each of which dissipates 20 mW, as well as all associated data, coefficient, and control registers necessary for its operation. The total power dissipation for the chip is 140 mW. The physical implementation of the multiplier employs buried-collector bipolar devices and two-level aluminum metallization to obtain a compact chip 120 mil/SUP 2/. Descriptions of the circuit's arithmetic architecture, design, performance, and use are given in detail.

Design and characterization of 3 μm bubble memory chips utilizing Y‐Y patterns

Abstract: Major‐minor organized bubble memory chips have been developed utilizing 14 μm period Y‐Y propagation circuits. First type is a 75 kbit memory chip consisting of four major‐minor units for high performance demands. Designed access time and data rate for 300 kHz drive are 0.3 nsec and 2×600 kbits/sec, respectively. Second type is a single unit major‐minor 78 kbit memory chip for medium access time use. Main chip design features are as follows: (1) 14 μm Y shaped Permalloy circuits are used throughout the chip, except for the 18 μm chevron stretcher. (2) Y‐Y transfer gates have been tailored in order to adapt to Y patterns. (3) A thin film Permalloy detector is used for the sake of large output (15 mV/2 mA) amd O‐π phase detection. The 3 μm bubble chips are fabricated on (YSmTmCa)3(FeGe)5O12 garnet films. Wafers are processed through 3 evaporation steps and 5 masks. Total 20 Oe operating bias margin is obtained at 300 kHz for 50 Oe drive field.

Electronic circuit device

Abstract: PURPOSE: To increase the mounting density, by lapping a plurality of lead frames connecting electronic circuit elements via electric insulators, molding it with resin, and using the projected lead chips as external terminals with cutting off. CONSTITUTION: The conduction plate is punched out to obtain the lead frames 12, 13, and the semiconductor ship 8 is die-bonded to the element setting lead chip 6 of one frame 12, and the chip 9 is made with the lead chip 7 of another frame 13, respectively by using conductive resin. Next, the chip 8 and the wire connection lead chip 14 of the frame 12, and the chip 9 and the lead chip 15 are bonded respectively by using the wire 10. After that, the frames 12 and 13 are lapped via the electric insulator 5, they are contained in the metal mold to inject the epoxy resin by remaining the tip of the lead pieces 6, 7, 14 and 15, and low pressure molding is made. Thus, the chips 8 and 9 are unifiedly composed and the resin mold 1 can be obtined. COPYRIGHT: (C)1979,JPO&Japio

Integrated injection logic for a linear/digital LSI environment

Abstract: The dc and transient performance of Integrated Injection Logic (I2L) structures in a linear/digital LSI environment is analyzed and modeled. The analysis is based on a functional modeling approach and uses a one-dimensional regional computer device analysis program which includes heavy doping effects and doping level mobility dependence. The computed results are used to evaluate the performance of I2L structures in five bioplar technologies. Means of decreasing the effective epitaxial layer thickness and decreasing the effective epi-resistivities of the I2L part of the chip, without affecting the breakdown voltage of the linear part, are given and evaluated. The computed results are compared to experiments.

A microprocessor-compatible high-speed 8-bit DAC

Abstract: The increasing use of microprocessors in systems which receive or generate analog signals has created a need for data converters which interface to those processors. A D/A converter which includes all registers and logic required for 8-bit microprocessor interface, and can be fabricated with a standard bipolar linear process is described. The system interface timing is specified such that the converter appears as a memory location to the microprocessor. It can be programmed to operate in a wide variety of modes and can interface with the fastest MOS and TTL microprocessors. The converter offers high-speed multiplying operation and an output current mode multiplexer. Status latches are provided to store multiplexer and code select commands. Nonsaturating multilevel logic operating nearly in the linear region provides gate delays of less than 5 ns when fabricated on the same chip with precision linear functions.