scispace - formally typeset
Search or ask a question

Showing papers on "Chip published in 1981"


Journal ArticleDOI
TL;DR: Numerical results indicate that appropriate use of multiaccess coding can provide utilization-delay characteristics superior to that of ALOHA.
Abstract: Analytical techniques for performance evaluation of synchronous random access packet switching in code division multiple access (CDMA) systems are presented. Steady-state throughput characteristics using several packet generation models are obtained. A number of example random access CDMA systems are compared in terms of their throughput versus offered traffic and utilization-delay characteristics. Numerical results indicate that appropriate use of multiaccess coding can provide utilization-delay characteristics superior to that of ALOHA. System stability is evaluated using a general finite user model, and the dynamic behavior of some example random access CDMA schemes is investigated.

328 citations


Patent
John Francis Gogal1
08 Apr 1981
TL;DR: In this paper, a double cavity semiconductor chip carrier (100) is described, which comprises a multilayer ceramic sandwich structure having a pair of semiconductor receiving cavities in the opposite faces thereof.
Abstract: A semiconductor device including a double cavity semiconductor chip carrier (100) which comprises a multilayer ceramic sandwich structure having a pair of semiconductor chip receiving cavities in the opposite faces thereof. The package enables mounting and electrical interconnection of a pair of semiconductor integrated circuit chips in a package of the same size as that for a single chip and having somewhat greater thickness. External terminals (93) on an outside face of the carrier are connected selectively by metallization paths (44, 53, 55, 83) integral with the carrier to chip mounting pads (41, 51) and to internal terminals (28) within the carrier. The internal terminals are disposed peripherally with respect to the chip cavities and adapted for interconnection with chip contact pads (26). Thus, a pair of unlike semiconductor integrated circuits can be interconnected in accordance with different patterns within a single package.

207 citations


Patent
14 Aug 1981
TL;DR: In this paper, the power and ground leads are connected in a bus structure around the chip at the center of the chip carrier with the chip being secured to a chip carrier over a thermal pad formed within the bus structure.
Abstract: A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected in a bus structure around the chip at the center of the chip carrier with the chip being secured to the chip carrier with the bus structure over a thermal pad formed within the bus structure. A decoupling capacitor is located in close proximity to the chip on the substrate to assure low reaction due to switching.

124 citations


Patent
Maurice Thomas Mcmahon1
02 Jul 1981
TL;DR: In this paper, the Level Sensitive Scan Design (LSSD) discipline is used for chip-in-place test and interchip wiring test of the package, which is also required that the capability of scanning data into and out of package SRLs (shift register latches) must be satisfied.
Abstract: Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package. The intent of the design rules is to design chips such that each chip can be "isolated" for testing purposes through the pins (or other contacts) of a higher level package containing such chips. It is also required that the "Level Sensitive Scan Design" (LSSD) discipline, or rules, be followed for each chip and for the package clock distribution network. Further, the LSSD Rules which ensures the capability of scanning data into and out of the package SRLs (shift register latches) must be satisfied for the total package.

72 citations


01 Mar 1981
TL;DR: A chip for performing the 2-D (two-dimensional) convolution in signal and image processing that consists of essentially only one type of simple cells, which are mesh-interconnected in a regular and modular way, and achieves high performance through extensive concurrent and pipelined use of these cells.
Abstract: : This paper describes a chip for performing the 2-D (two-dimensional) convolution in signal and image processing. The chip, based on a systolic design, consists of essentially only one type of simple cells, which are mesh-interconnected in a regular and modular way, and achieves high performance through extensive concurrent and pipelined use of these cells. Denoting by u the cycle time of the basic cell, the chip allows convolving a kxk window with an nxn image in O(sq m)(u/k) time, using a total of cu k basic cells. The total number of cells is optimal in the sense that the usual sequential algorithm takes O(sq m)(sq k)(u) time. Furthermore, because of the modularity of the design, the number of cells used by the chip can be easily adjusted to achieve any desirable balance between I/O and computation speeds. (Author)

70 citations


Patent
16 Nov 1981
TL;DR: In this paper, a method and apparatus for simulating custom chips to be used in a data processing system is presented, where each chip is simulated by a chip simulator that includes a mother board and a plurality of baby boards mounted and interconnected on the mother board.
Abstract: A method and apparatus for simulating custom chips to be used in a data processing system. Each chip is simulated by a chip simulator that includes a mother board and a plurality of baby boards mounted and interconnected on the mother board. Each baby board has circuit components mounted thereon for performing the circuit function of one cell of the chip. Chip simulators are interconnected in an interconnecting apparatus that supports the mother boards in parallel and spaced apart relation. Chip simulators that represent all of the chips found on a single printed circuit board in the system are interconnected at the interconnecting apparatus so that design errors which are only evident when the chips are interconnected can be tested for and detected prior to fabrication of the chips.

54 citations


Patent
14 Aug 1981
TL;DR: In this paper, the chip is hermetically sealed within the ceramic cap which is bonded to the chip carrier and a dielectric sliver which rests above a glass filler and bonding agent which fills the space between the interdigitated pattern and the sliver.
Abstract: A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected to an interdigitated lead array at the center of the chip carrier with the chip being secured to the chip carrier above the interdigitated pattern. The chip is bonded to a dielectric sliver which rests above a glass filler and bonding agent which fills the space between the interdigitated pattern and the sliver. The chip is hermetically sealed within the ceramic cap which is bonded to the chip carrier. Power and ground connections are made, from the chip directly to a pair of buses surrounding the interdigitated pattern rather than to leads extending outwardly to the edge of the chip carrier.

54 citations


Patent
03 Dec 1981
TL;DR: In this article, an automatic mounting apparatus for electrical chip components comprises a parts feeder including a plurality of hoppers with the chip components therein, and a parts applicator including means for picking up the chip component and movable in orthogonal directions in programmed sequence.
Abstract: An automatic mounting apparatus for electrical chip components comprises a parts feeder including a plurality of hoppers with the chip components therein, and a parts applicator including means for picking up the chip component and movable in orthogonal directions in programmed sequence to transport the chip components successively from the parts hopper to a printed circuit board for automatic mounting thereon within a minimum time.

47 citations


Patent
07 Dec 1981
TL;DR: In this paper, the authors propose a back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field effect transistor (FET) and the negative threshold voltage (NVR) of a second FET.
Abstract: A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.

38 citations


Journal ArticleDOI
TL;DR: A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described, using a silicon-gate CMOS process to implement the critical circuits in CMOS technology.
Abstract: A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described. The associated switched-capacitor filters and reference voltage are also implemented on the chip, using a silicon-gate CMOS process. The DAC and ADC used incorporate a binary-weighted capacitor array and a string of equal-valued resistors. The circuit operators from a/spl plusmn/5 V supply and it consumes 65 mW in normal operation and 5 mW in the power-down condition. The implementation of the critical circuits in CMOS technology is discussed in detail.

35 citations


Patent
Douglas Wayne Westcott1
05 Oct 1981
TL;DR: In this article, an integrated circuit chip having an embedded array is manufactured with additional test circuitry directly on the chip, such that the performance of the array may be physically tested from the input/output pins by an external chip tester while the array remains embedded.
Abstract: An integrated circuit chip having an embedded array (10) which is not directly accessible from the primary input/ output chip pins is manufactured with additional test circuitry directly on the chip, such that the performance of the array may be physically tested from the input/output pins by an external chip tester while the array remains embedded. Because of the added test circuitry (12, 14, 16, 18, 22, 24, 26), tests are not limited to the original chip architecture, and a variety of array tests may be made by an external tester without redesigning the chip architecture.

Patent
Paul S. Henry1
01 Jul 1981
TL;DR: In this paper, a decoder for use in a spread spectrum radio receiver which is capable of directly demodulating an L-length frequency-hopped, Q-level frequency shift keyed radio-frequency received signal into a baseband signal was presented.
Abstract: The present invention relates to a decoder for use in a spread spectrum radio receiver which is capable of directly demodulating an L-length frequency-hopped, Q-level frequency shift keyed radio-frequency received signal into a baseband signal wherein a desired user's message signal is decoded into a sequence of tone bursts at a fixed frequency over each L-length sequence. Spectral analysis is performed on the resultant baseband signal either during each chip interval or once at the end of each L-length sequence to permit subsequent detection of a desired user's correct received message signal.

Proceedings ArticleDOI
29 Jun 1981
TL;DR: A model of fault distribution for a chip that adapts itself to the various characteristics of the chip and the fault model and can be easily determined for any given field reject rate is proposed.
Abstract: At present, the relationship between fault coverage of LSI circuit tests and the tested product quality is not satisfactorily understood. Reported work on integrated circuits predicts, for an acceptable field reject rate, a fault coverage that is too high (99 percent or higher). This fault coverage is difficult to achieve for LSI circuits. This paper proposes a model of fault distribution for a chip. The number of faults on a defective chip is assumed to have a Poisson density for which the average value is determined through experiment on actual chips. The procedure, which relates the model to the chip being studied, is simple; one or more fabricated chip lots must be tested by a few preliminary test patterns. Once the model is characterized, the required value of fault coverage can be easily determined for any given field reject rate. The main advantage of such a model is that it adapts itself to the various characteristics of the chip (technology, feature size, manufacturing environment, etc.) and the fault model (e.g., stuck-type faults). As an example, the technique was applied to an LSI circuit; realistic results were obtained.

01 Jan 1981
TL;DR: An offset-quaternary direct-sequence spread-spectrum multiple-access communication system is analyzed, which considers the effect of the choice of chip waveforms on the bandwidth, the signal-to-noise ratio at each user's receiver, and the constant-envelope character of the transmitted signals.
Abstract: : An offset-quaternary direct-sequence spread-spectrum multiple-access communication system is analyzed. This analysis considers the effect of the choice of chip waveforms on the bandwidth which the system utilizes, the signal-to-noise ratio at each user's receiver, and the constant-envelope character of the transmitted signals. (Author)

Journal ArticleDOI
D.G. Marsh1, B.K. Ahuja1, T. Misawa, M.R. Dwarakanath, P.E. Fleischer, V.R. Saari 
01 Aug 1981
TL;DR: In this paper, a complete PCM codec using charge redistribution and switched-capacitor techniques is described, implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area.
Abstract: A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the chip allows asynchronous operation, a variable PCM data rate from 100 kbit/s to 4.096 Mbit/s, /spl mu//A law operation via pin selection, and gain selection at either of two levels in each direction.

Proceedings ArticleDOI
01 Aug 1981
TL;DR: In this article, a single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques, which achieve low power dissipation and small 16 pin package.
Abstract: A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements.

Journal ArticleDOI
01 Aug 1981
TL;DR: A second generation LSI codec has been implemented with switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated.
Abstract: A second generation LSI codec has been implemented. In this chip, switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated. The authors describe the codec and summarizes its characteristics.

Journal ArticleDOI
J.M. Mikkelson1, L.A. Hall, A.K. Malhotra, S.D. Seccombe, M.S. Wilson 
01 Oct 1981
TL;DR: An overview of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency is given in this paper.
Abstract: An overview is given of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency The technology utilizes 15-/spl mu/m lines and 10-/spl mu/m spaces on all critical levels, and provides tungsten dual layer metallization The device and interconnect structure for this 8-mask process is outlined as a sequence through the process flow Linewidth and alignment statistics are given for the optical reduction-projection step-and-repeat lithography used in this technology

Patent
12 Jan 1981
TL;DR: In this paper, a plurality of CML integrated circuit chips with input and output gates connected in a circular access linkage loop with each chip having an interface mechanism comprising an interface register and a bypass arrangement between the input gate and the output gate so that information may flow from a transmitter output gate to a receiver input gate uni-directionally, (clockwise or counter-clockwise) through the loop by means of the bypass with minimal delay.
Abstract: A plurality of CML integrated circuit chips with input and output gates connected in a circular access linkage loop output-to-input with each chip having an interface mechanism comprising an interface register and a bypass arrangement between the input gate and the output gate so that information may flow from a transmitter output gate to a receiver input gate uni-directionally, (clockwise or counter-clockwise) through the loop by means of the bypass with minimal delay. Utilizing this circular access linkage loop together with a junction box, a number of access loops can be joined together to increase the number of chips which can be linked together. Also disclosed is a multiplexing scheme utilizing the circular access linkage loop for increasing the gate per pin ratio and for higher speed communication between chips.

Patent
28 Sep 1981
TL;DR: In this article, a spread spectrum waveform encoded altimeter is presented, where a plurality of individual detectors are used to detect an early chip or signal and another pair of detectors are provided to detect a late signal or signal.
Abstract: The present invention provides a spread spectrum waveform encoded altimeter. Spread spectrum carrier wave signals which are transmitted and later received are processed in a novel edge detecting apparatus which includes a plurality of individual detectors. A pair of detectors are provided to detect an early chip or signal. Another pair of detectors are provided to detect a late chip or signal. There is also provided a pair of edge chip detectors for detecting the center or locked on chip signal. Logic circuits are employed to sum the voltage signals from the detectors and to provide a control signal capable of adjusting a tracking generator to enable it to lock on to the received signal. An altimeter counter is provided which is started by a unique chip in the transmitted signal and stopped when the same unique chip is detected in the receiving and tracking loop.

Journal ArticleDOI
TL;DR: A fully integrated 32-bit VLSI CPU chip utilizing 1 /spl mu/m features is described, which provides the functions of an advanced mainframe CPU.
Abstract: A fully integrated 32-bit VLSI CPU chip utilizing 1 /spl mu/m features is described. It is fabricated in an n-channel silicon gate, self-aligned technology. The chip contains about 450000 transistors and executes microinstructions at approximately one per 55 ns clock cycle. It can execute a 32-bit binary integer add in 55 ns, a 32-bit binary integer multiply in 1.8 /spl mu/s, and a 64-bit floating point multiply in 10.4 /spl mu/s. The instruction set provides the functions of an advanced mainframe CPU. Because the implementation of such a complex device poses an organizational as well as a technical challenge, the design philosophy that was adopted is summarized briefly. Careful attention was paid to designer productivity, and design flexibility and testability.

Patent
09 Apr 1981
TL;DR: In this paper, a bridge circuit is proposed to derive a power potential from an externally transmitted signal, with or without regulation, using a single CMOS integrated circuit, which can operate at carrier frequencies as high as several megahertz.
Abstract: There is disclosed a bridge circuit which finds particularly advantageous use in medical prostheses which can be programmed externally and which can transmit telemetry signals. The entire circuit is implemented on a single CMOS integrated circuit. Depending upon the values of two control bits, the bridge circuit functions to derive a powering potential from an externally transmitted signal, with or without regulation. Externally transmitted programming signals are detectable, and telemetry signals can be transmitted from the chip as well. There is no active switching of bridge devices during power rectification mode, and instead they are biased on continuously. This allows the rectifier to operate at carrier frequencies as high as several megahertz. All of this is achieved by using conventional CMOS processing techniques, without requiring any extra diffusion steps.

ReportDOI
19 Aug 1981
TL;DR: It is argued on the basis asymptotic analysis that a constant corridor width is preferred even though such lattices cannot make full use of the processor elements for most complex interconnection patterns, e.g., universal interconnection structures like the cube connected cycles and shuffle exchange.
Abstract: : The main question under study is how wide the corridor width should be for the switch lattice of the Configurable, Highly Parallel (CHiP) computer. (The CHiP computer family is introduced and its use for parallel algorithm composition is motivated.) It is argued on the basis asymptotic analysis that a constant corridor width is preferred even though such lattices cannot make full use of the processor elements for most complex interconnection patterns, e.g., universal interconnection structures like the cube connected cycles and shuffle exchange, and for certain 'simple' ones, e.g., certain planar graphs. (Author)

Journal ArticleDOI
TL;DR: A charge redistribution codec fabricated by NMOS technology is presented which uses only one capacitor array, thereby resulting in improved accuracy, speed, and chip area utilization, which eliminates the need for off-chip autozero circuitry.
Abstract: A charge redistribution codec fabricated by NMOS technology is presented which uses only one capacitor array, thereby resulting in improved accuracy, speed, and chip area utilization. The realization of this scheme requires precision voltage references which are described. A description of a codec complete with logic to interface a full duplex PCM link is included. The chip has provision for asynchronous transmit/receive, direct and microcomputer control and internal power down. The introduction of an improved method for offset correction eliminates the need for off-chip autozero circuitry.

Patent
12 Feb 1981
TL;DR: In this article, a central processor for an electronic organ in the form of a single, forty pin integrated circuit chip employing multiplexed technology and trinary and tri-level inputs to obtain maximum usage from each pin.
Abstract: A central processor for an electronic organ in the form of a single, forty pin integrated circuit chip employing multiplexed technology and trinary and tri-level inputs to obtain maximum usage from each pin. The solo manual keys, chord keys, rhythm pattern switches and other control functions are multiplexed externally of the chip, fed into the chip as a time division multiplexed four bit byte over four pins, and demultiplexed internally of the chip. The solo manual information is multiplexed internally of the chip to form a single serial data stream, is combined with solo fill note data generated within the chip and then brought out over a single pin for external demultiplexing. The twelve tones of a musical octave are brought into the chip over twelve pins together with various static control signals, are decoded by tri-level decoders internally of the chip, and then utilized to generate the tones of the chords, also internally of the chip. Chord tone generation is accomplished by selecting the musical fifth tone in an internal ROM, dividing this tone by a factor of three to produce the fundamental and generating the third and seventh tones also through the use of internal ROMs. Keying of the chord tones is accomplished by internal digital sustain keyers which provide an output over a single pin. There is also provided internally of the chip the capability for producing bass patterns, note patterns and rhythm percussion patterns. By suitable controls, the chip may be adapted for use in a large organ configuration, where various of the timing controls are generated externally, and in a small organ configuration, where these controls are generated internally of the chip.

Patent
19 Jan 1981
TL;DR: A synchronization system for a spread spectrum communication receiver generates a receiving code sequence which is identical to an input code sequence and then varies the timing of the receiving code sequences using a correlator until the two code sequences are correlated as mentioned in this paper.
Abstract: A synchronization system for a spread spectrum communication receiver generates a receiving code sequence which is identical to an input code sequence and then varies the timing of the receiving code sequence using a correlator until the two code sequences are correlated.

Patent
28 Jan 1981
TL;DR: In this paper, a chip carrier with a plurality of conducting fingers that terminate at its underside is described, and a lid is placed over the carrier and the chip is hermetically sealed inside the cavity of the carrier.
Abstract: A hermetic plastic package for a semiconductor integrated circuit chip includes a chip carrier provided with a plurality of conducting fingers that terminate at its underside. The carrier includes a pedestal onto which a semiconductor chip is bonded and wires are connected between the bonding pads on the chip and associated fingers on the carrier. A lid is placed over the carrier and is hermetically sealed with the chip inside the cavity of the carrier. The finger terminations on the underside of the carrier are connected to a plurality of leads which have inner portions that extend outward in a direction parallel to the underside of the carrier and end portions that are bent substantially perpendicular to the underside of the carrier configuration. The chip carrier and the inner portions of the leads that lie parallel to the underside of the chip carrier are encased in a plastic or epoxy compound.

Patent
12 Jun 1981
TL;DR: Voltage pulser circuits are utilized to selectively, alternately supply high voltage to, or ground the high voltage input of plasma panel driver chips as mentioned in this paper, which greatly reduces the amount of power which must be dissipated in the driver chip.
Abstract: Voltage pulser circuits are utilized to selectively, alternately supply high voltage to, or ground the high voltage input of plasma panel driver chips. High voltage is supplied to a driver chip only when the driver chip must perform an addressing pulse. The grounding operation, which is induced by shorting the high voltage input of a driver chip to the ground input of the chip, greatly reduces the amount of power which must be dissipated in the driver chip. The use of the voltage pulser circuit also allows full slew rate control of the output pulse which the driver chips supply to the plasma panel.

Proceedings ArticleDOI
01 Jan 1981
TL;DR: Two sense amplifiers capable of sensing 0.5mV haversine waves and two output amplifiers with 1-12mA outputs combined with a 4b microprocessor on a CMOS 35,600 square mil chip to produce a single chip, implantable pacer, with eight programmable modes, will be reported.
Abstract: Two sense amplifiers capable of sensing 05mV haversine waves and two output amplifiers with 1-12mA outputs, combined with a 4b microprocessor on a CMOS 35,600 square mil chip, to produce a single chip, implantable pacer, with eight programmable modes, will be reported

Journal ArticleDOI
TL;DR: The SLCTM-96 subscriber loop carrier system is a digital subscriber carrier system serving up to 96 single-party customers that employs a custom NMOS lsi chip providing a full-access, time-slot interchange function.
Abstract: The SLCTM-96 subscriber loop carrier system is a digital subscriber carrier system serving up to 96 single-party customers. The system can be configured with an optional plug-in which digitally concentrates two standard, 1.544 megabit, serial pulse-code modulation (PCM) bit streams into a single stream, thereby concentrating 48 customers onto a single T1 digital line. The concentrator employs a custom NMOS lsi chip providing a full-access, time-slot interchange function. It has microcomputer controllers at the two ends of the system to control time-slot assignments. The development of the concentrator involved challenges in chip design, software design, and performance testing.