Showing papers on "Chip published in 1983"

Design and implementation of a single-chip 1-D median filter

Abstract: The design and implementation of a VLSI chip for the one-dimensional median filtering operation is presented. The device is designed to operate on 8-bit sample sequences with a window size of five samples. Extensive pipelining and employment of systolic data-flow concepts at the bit level enable the chip to filter at rates up to ten megasamples per second. A configuration for using the chip for approximate two-dimensional median filtering operation is also presented.

Spread spectrum correlator for recovering CCSK data from a PN spread MSK waveform

Abstract: In a spread spectrum communications system employing cyclic code shift keying as its primary modulation, the transmission waveform is spread for transmission security by modulo-2 adding a pseudo-noise sequence to the CCSK data symbols prior to phase modulating onto a carrier signal for transmission. If the transmission modulation is minimum shift keying (MSK) the two components of the data stream are applied to the carrier with a differential encoding step implicit in the modulation scheme. This differential encoding characteristic makes stripping of the PN spread function prior to CCSK demodulation difficult at the receiving end. In order to demodulate this waveform in an optimum manner, an array correlator, the adjacent correlator stages of which have one chip relative time displacements of their CCSK reference waveform, is employed. In effect the array correlator becomes a parallel array of matched filters matched to each cyclic shift of the incoming waveform. By modulo-2 addition of the PN spreading waveform with the time displaced CCSK reference waveform in each stage of the correlator, the correlator can be made to match all versions of the spread symbol being received.

Laser written chip identification method

Abstract: A system of identifying each chip with identification data that is both human and machine readable. The chip identification is then used in sorting, storing, testing, assembling and failure analysis. The identification usage at these process steps eliminates chip part number mix-up and placement. It provides data used for quality control.

On-chip monitor

Abstract: Level sensitive scan design (LSSD) scan strings on an integrated digital logic circuit chip (24) are employed for multiple functions of providing control parameters to logic blocks (110) on the chip (24), and for providing reconfiguration messages to reconfiguration logic (225) on the chip, in addition to the normal function of transferring test data to various portions of the chip. This reduces the number of input/output pads on the integrated circuit chip which must be dedicated to these functions.

Mounting one integrated circuit upon another

Abstract: In an integrated circuit assembly a memory chip 3 is mounted on a logic chip 1. A first set of contact pads 2 on the logic chip 1 are electrically joined to corresponding contact pads 4 on the memory chip 3 to secure the chips to one another in face-to-face relationship and to provide interconnections between the chips. A further set of contact pads 5 on the logic chip 1 are provided for external connections to the integrated circuit assembly. The assembly may be contained in a protective package 7, 8 or may be mounted on an etched metal film using a tape assisted bonding technique.

Plastic package with lead frame crossunder

Abstract: Proposed is a new way to distribute power off chip using a specially designed lead frame. The support paddle of the lead frame is split electrically and provides at least two conductor members that are arranged to cross under the chip after the chip is bonded to the paddle. Power and/or ground can be distributed to two or more edges of the chip by providing bonding sites at or near the extremities of the crossunders. The chip itself is electrically isolated from the crossunder members.

Compact NMOS building blocks and a methodology for dedicated digital filter applications

Abstract: Building blocks for digital filters are discussed. They require 0.7 mm/SUP 2/ or 3 mm/SUP 2/ per pole-zero for a dedicated and a partly programmable realization, respectively. They are realized in 6 /spl mu/m NMOS technology, with 16-bit words and working at bit rates up to 10 Mbit/s. With the exclusion of data conversion, scaling will make them competitive with switched capacitor realizations for 3 /spl mu/m technology, in terms of silicon area and speed. These compact results are achieved due to proper minimization in the design. The experience with the above designs is then generalized into a methodology for custom digital filters. An important concern is a hardware-minimization scheme over all design levels (algorithm, bit-serial architecture, and layout style) with efficient IC implementation and performance in mind. It leads to the possibility of an automated design. The design is supported by computer aided design tools for design verification on all levels, and for file management as well as layout. A formal design of a third-order elliptical wave digital filter demonstrates the concept. The resulting chip area is 1.8 mm/SUP 2/ in 6 /spl mu/m NMOS. The simulated maximum bit rate is 5 MHz (corresponding to 312 kHz sampling rate), with a power consumption of 18 mW.

Monolithic fast fourier transform circuit

Abstract: A fast Fourier transform circuit formed on a single chip, including a fast multiplier-accumulator circuit which, in the preferred embodiment, employs a modified form of Booth's algorithm, an adder circuit, a read-only memory for storing FFT twiddle factors, and a random access memory for holding a set of input complex quantities and for receiving intermediate and final results in an in-place FFT operation. In the preferred embodiment, the FFT twiddle factors are stored in Booth's code for greater speed of operation. Control and timing circuitry on the same chip generates control signals and address codes in order to perform a sequence of butterfly computations by repeated use of the multiplier-accumulator and adder circuits, to generate FFT coefficients in the random access memory.

Integrated circuit chip wiring arrangement providing reduced circuit inductance and controlled voltage gradients

Abstract: The area circumscribed by the current path on an integrated circuit chip is diminished, to thereby reduce the inductance of the chip and the likelihood of inductively generated errors, by disposing the bonding pads, through which the current source and current sink are respectively connected to logic gates, physically adjacent to one another. A further reduction in the area of the current loop is obtained by locating power and ground busses adjacent to one another relative to the logic gates. These two busses can be superposed one over the other on different metallic layers of the chip, so that the space between them is only the thickness of the isolation layer which separates the two metallic layers. The distribution of voltage to the logic gates is made uniform by varying the widths of the busses along their lengths in accordance with the currents they carry, and by ensuring that the total length of the current path for the gates is the same for every gate.

Power chip package

Abstract: A heat-generating power semiconductor chip is mounted in a package to permit testing or use of the chip before or after mounting of the package to a heat spreader plate. A plurality of sheet metal leads are attached to a dielectric substrate, such as beryllia. The leads are patterned in mirror image fashion to a plurality of terminals on one side of the power chip. In one form, a further sheet metal lead is attached to a further dielectric substrate and is adapted to abut a terminal on the other side of the power chip. In another form, heat transfer structure is provided for transferring heat between the pair of dielectric substrates, thereby enabling heat to be removed from both sides of the power chip.

Performance of a Direct Sequence Spread-Spectrum System with Long Period and Short Period Code Sequences

Abstract: In this paper, the performance of a direct sequence spread-spectrum system is analyzed with both a long period sequence and with a sequence whose period is one bit long. Bit error rates for both quadriphase and biphase chip spreading, in conjunction with both QPSK and BPSK data, are considered in the presence of noise and jamming. The frequency location of the jammer is arbitrary.

Method of, and apparatus for, frequency-hopped frequency-shift-keyed digital data communications

Abstract: A digital data communications method and system combining frequency agility with a frequency-shift-keyed signal to transmit a unique code word representing a plurality of data states Each code word comprises a plurality of chips, each of which is an integer subportion of the bit time interval in which one data bit is communicated The multiple-chip word provides a frequency-hopped spread spectrum signal in which the nominal carrier frequency value is offset for transmitting binary data, or is offset in either frequency direction by different discrete amounts for transmitting multilevel digital data, to allow the data value to be properly decoded at a receiver even if the transmitter instantaneous frequency during at least one chip time interval is jammed by another signal The frequency offset, can also be provided in complementary fashion during selected chip time intervals to even further encode the data bit being communicated and further reduce the probability of jamming The multiple-chip code word, of normal or selected-chip-complemented form, modulates a carrier at the transmitter end The FH-FSK carrier is demodulated at the receiver end by an inverse modulation process which converts the signal into a serial bit stream, for matched filtering transmission and reception apparatus of non-complemented and/or complemented chip-encoded words is described

A 14-bit monotonic NMOS D/A converter

Abstract: A new configuration of a 14-bit digital-to-analog (D/A) converter has been fabricated as an experimental monolithic NMOS chip The concept utilizing two cascaded resistor strings delivers an inherent 14 bit monotonicity and a static voltage output signal The small chip size of about 85 mm/SUP 2/ and the saving of external components make the converter applicable for low-cost high-resolution control loop systems A modified test chip is also described which has been provided as a step into the field of accurate monolithic converters needed for digital audio systems A voltage output settling time less than 10 /spl mu/s and a linearity at the 12 bit level have been achieved

A single chip NMOS ethernet controller

Abstract: The design of an integrated NMOS controller for a 10Mb Ethernet will be described. In addition to handling protocol, redundancy checking and preamble, the chip includes a self-calibrating tapped delay line for clock and data extraction.

IC chip with noise suppression circuit

Abstract: A microprocessor chip is adapted to maintain its databus at a reference voltage level during idle times between outputs. The arrangement enables like pull-up and pull-down delays as well as low noise levels to be achieved in the output circuits.

Transmission line terminator-decoupling capacitor chip for off-chip driver

Abstract: A signal transmission line terminator for an off-chip driver circuit is disclosed in which each capacitor and resistor comprising each terminator are formed on the same chip separate from the driver circuit chip. The close proximity of the elements of the terminator reduce the path lengths therebetween to a minimum. The structure substantially eliminates the corresponding inductive reactance and concommitant ΔI noise at high switching rates employed in high performance computers.

A Single Chip Linear Array Picture Processor

Abstract: A CMOS programable picture processor*) with its own photodiod array is presented. The circuit is novel in that it includes an instruction set that permits most low-level picture processing operations. The chip is a parallel machine with a processing unit for each picture element. Images are binarized and are processed line by line. An experimental chip has been designed and is under fabrication.© (1983) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A CMOS switched-capacitor variable line equalizer

Abstract: The authors describe the design concept and experimental results for a CMOS switched-capacitor variable-line equalizer to be used in time-compression multiplexed (TCM) digital subscriber loop transmission systems. The equalizer transfer function is optimized in the time domain to relax the filter complexity to half that required by the application of classical communication techniques. In order the equalize wide-bandwidth high-speed digital data, a 50 MHz CMOS operational amplifier is proposed. The amplifier uses a folded cascade and buffer structure to achieve good stability against load capacitance change. An experimental chip has been fabricated with 2.5 /spl mu/m CMOS technology. The chip shows excellent characteristics for the equalization of 200 kb/s data travelling through pair cables of 5 km and 0.4 mm diameter.

Ka-Band Monolithic GaAs Balanced Mixers

Abstract: Monolithic integrated circuits have been developed on semi-insulating GaAs substrates for millimeter-wave balanced mixers. The GaAs chip is used as a suspended stripline in a cross-bar mixer circuit. A double sideband noise figure of 4.5 dB has been achieved with a monolithic GaAs balanced mixer filter chip over a 30- to 32-GHz frequency range. A monolithic GaAs balanced mixer chip has also been optimized and combined with a hybrid MIC IF preamplifier in a planar package with significant improvement in RF bandwidth and reduction in chip size. A double sideband noise figure of less than 6 dB has been achieved over a 31- to 39-GHz frequency range with a GaAs chip size of only 0.5 × 0.43 in. This includes the contribution of a 1.5-dB noise figure due to IF preamplifier (5-500 MHz).

Carrier for a leadless integrated circuit chip

Abstract: A carrier for a leadless integrated circuit chip has a cavity into which a chip is laterally inserted through an opening in a side wall of the carrier. A spring arm formed integrally with the carrier flexes backward in a recess to permit insertion of the chip, which has a plurality of electrical contact pads on its upper surface, and then bears against the chip under an internal spring bias to retain it within the cavity. Tabs at the upper corners of the cavity are positioned over the corners of the chip which are free of electrical contact pads, thereby preventing the chip from escaping while exposing the pads for both single and dual pin probing. The external configuration of the carrier conforms to industry standards so that the chip can be fully processed and tested without removing it from the carrier.

A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions

Abstract: A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption. As a result, power dissipation is less than 5 mW/MHz in the active mode, and less than 1 /spl mu/W in both the standby mode and the active quiescent mode (chip enabled, but no address transitions sensed). Three special test features incorporated in the design can be used to reduce the time required for final test and reliability screening.

Semiconductor device having a plurality of CMOS I/O cells located at the periphery of the chip arranged in a direction perpendicular to the sides of the chip

Abstract: A semiconductor device comprises a gate array portion formed in the central portion of a chip, and a number of CMOS input/output cells arranged at the peripheral portion of the chip. Each input/output cell consists of a bonding pad, a p-channel MOS region and an n-channel MOS region, and extends inward from the side of the chip in a direction perpendicular to the side of the chip.

High Thermal Conduction Package Technology for Flip Chip Devices

Abstract: The technology of new packages with high thermal conduction performance, simplified structure, and also high reliability for flip chip devices is described. In order to obtain high thermal conduction, a thermal conduction plate is individually bonded to the back surface of a large-scale integrated (LSI) chip by soft solder and is arranged in close proximity to the inner surface of the cap, when the chip is assembled together with the cap and substrate. The cavity is then filled with a gas which has a high thermal conductance characteristic. As a result, a large part of the heat is effectively drawn off from the back side of the chip to the air-cooling fin through the plate and across the narrow gap filled with the gas. A series of experiments were conducted on a single chip package and a nine chip multichip module. These tests indicated a junction-to-fin thermal resistance of 3.2°C/W for the single chip package and 4.8°C/W as a worst case in the module. In addition a computer model analysis for thermal conduction was studied using a program named TNET-2. It was found that the calculated values corresponded closely to the measured data. More detailed descriptions of packages and results of studies are presented and discussed here.

CMOS Logic circuits with all pull-up transistors integrated in separate chip from all pull-down transistors

Abstract: An integrated circuit chip with a preferred ground structure and including only pull-down transistors (on-chip) is operated by means of an off-chip pull-up transistor arrangement for precharging the data bus to logic high. The arrangement exhibits relatively low noise characteristics allowing relatively high frequency operation without generating noise voltages which exceed FET threshold voltages.

Documentation for the CHIP Computer System (Version 1.1)

Abstract: CHIP (Cornell Hypothetical Instructional Processor) is a computer system that was designed as an educational tool for teaching undergraduate courses in operating systems and machine architecture This document constitutes the sole reference manual for the CHIP computer system A simulator for this hypothetical system exists under the UNIX operating system The CHIP architecture includes dynamic memory mapping suitable for implementing virtual memory, eight interrupt priority levels, memory-mapped input/output and two modes of processor operation The central processor of CHIP is compatible with the PDP-11 at the user-mode instruction level Therefore, any non-privileged code written for the PDP-11 can be executed on CHIP Several new user and kernel-mode instructions have been added to CHIP for increased efficiency The CHIP simulator also supports input/output devices such as terminals, drums, disks and printers All interactions with CHIP take place through an operator''s console being simulated on a terminal Users can examine/alter memory locations, set breakpoints, detect the referencing of specified memory locations, start/stop execution, etc through a console command language Program global variables and functions can be referred to by symbolic name with the mapping to absolute addresses being performed automatically by the system The software support environment for CHIP includes a C compiler, assembler and loader

Full-wave rectifier for CMOS IC chip

Abstract: A full-wave rectifier is implemented in CMOS integrated circuit chip technology. Two transistors are used in a bridge arrangement with two diodes to implement the rectifier while avoiding parasitic transistor action which previously provided an unwanted current path through the chip substrate to defeat full-wave rectification.

Improvements in Multilayer Ceramic Capacitors

Abstract: The increased use of Multilayer Ceramic Capacitors in both chip and encapsulated formats is mainly due to their excellence at decoupling Integrated Circuit Random Access Memories.