Showing papers on "Chip published in 1984"

Optical interconnections for VLSI systems

Abstract: The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The origins of the communication crisis are discussed. Those aspects of electrooptic technology that are applicable to the generation, routing, and detection of light at the level of chips and boards are reviewed. Algorithmic implications of interconnections are discussed, with emphasis on the definition of a hierarchy of interconnection problems from the signal-processing area having an increasing level of complexity. One potential application of optical interconnections is to the problem of clock distribution, for which a single signal must be routed to many parts of a chip or board. More complex is the problem of supplying data interconnections via optical technology. Areas in need of future research are identified.

CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications

Abstract: Using a 3.5-/spl mu/m gate length complementary metal-oxide-semiconductor/silicon-on-sapphire technology, a single-chip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. During each clock period the chip generates a new digitized sample of a sine wave, whose frequency is variable in 2/SUP 20/ steps from DC to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst-case environment, including ionizing radiation levels up to 3/spl times/10/SUP 5/ rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory. The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below -65 dBc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.

Chip Layout Optimization Using Critical Path Weighting

Abstract: A chip layout procedure for optimizing the performance of critical timing paths in a synchronous digital circuit is presented. The procedure uses the path analysis data produced by a static timing analysis program to generate weights for critical nets on clock and data paths. These weights are then used to bias automatic placement and routing in the layout program. This approach is shown to bring the performance of the chip significantly closer to that of an ideal layout which is assumed to have no delay due to routing between cells.

Throughput Analysis for Code Division Multiple Accessing of the Spread Spectrum Channel

Abstract: We consider the use of error correction codes of rate r on top of pseudonoise (PN) sequence coding for code division multiple accessing of the spread spectrum channel. The channel is found to have a maximum throughput of 0.72 and 0.36 based on the evaluation of channel capacity and cutoff rate, respectively. More generally, these two values are derived for given bandwidth expanding n/r versus n/N where n is the length of the PN sequence and N is the number of simultaneous users. It is found that to achieve the maximum throughput, n should be small. This implies that coding schemes with short PN sequences and low rate codes are superior in terms of throughput or antijam capability. The extreme case of n = 1 corresponds to using a very low rate code with no PN sequence coding. Convolutional codes are recommended and analyzed for their error rate and decoding complexity.

Simultaneous placement and wiring for vlsi chips

Abstract: For designing the layout of a master-slice VLSI chip steps for placing components and for determining the wiring pattern interconnecting them are alternated in an iterative process. The chip area is partitioned into subareas of decreasing size, the set of components is partitioned into subsets which fit to the respective subareas, and after each partitioning step the global wiring is determined for the existing subnets of the whole network. Due to this interrelation of placement and wiring procedures, advantages with respect to total wire length, overflow number of wires, and processing time can be gained.

Method and means for improved heat removal in compact semiconductor integrated circuits

Abstract: A semiconductor chip having improved heat dissipation capability. The back surface of a semiconductor chip is provided with microscopic channels defined by fins in intimate contact with the chip. A cover is affixed to the fins to enclose the channels for the laminar flow of coolant fluid. The chip can be mounted in a recessed portion of a dual in-line package (DIP) with conductive tubes integral with the package providing the flow of coolant. Advantageously, the tubes can function as power busses to the integrated circuit.

Cooling system for VLSI circuit chips

Abstract: A system for cooling integrated circuit chips and particularly those involving very large scale integrated circuits; the system provides for closely associating the heat-sink or heat exchange element with the integrated circuit chip by having the heat-sink, in the form of a "cooling chip", in intimate contact with the back surface of an integrated circuit chip (in a "flip chip" configuration, the front, or circuit-implemented, surface, makes contact with a ceramic carrier or module); the cooling chip is provided with a plurality of spaced parallel grooves which extend along the one side or surface opposite the surface that is in bearing contact with the integrated circuit chip, whereby liquid coolant flows through the grooves so as to remove heat from the integrated circuit chip; further included in the system is a specially configured bellows for conducting the liquid coolant from a source to the heat-sink, and for removing the liquid coolant; a coolant distribution means, in the form of at least one glass plate or manifold, is provided with spaced passageways interconnecting the respective incoming and outgoing coolant flow paths of the bellows with the heat-sink.

Correlation detectors for use in direct sequence spread spectrum signal receiver

Abstract: A plurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different assigned code sequence shift. A receiver, synchronized to the clock, discriminates the signal transmitted by a predetermined transmitter from signals transmitted by the others by generating a first bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has a code sequence shift corresponding to that of the predetermined transmitter, and a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unassigned code sequence shift. The difference between the first and second bipolar pseudo-random code sequences, which is a trinary code sequence, is cross-correlated with the incoming signals. The cross-correlation despreads only the signal spread by the sequence having the predetermined code sequence shift. Each receiver includes a number of correlation detectors offset from each other by a fraction of a code chip together with decision circuitry to identify cross-correlation peaks for optimum synchronization. Analog and digital implementations of the correlation detectors are disclosed.

On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays

Abstract: Fault-tolerance is undoubtedly a desirable property of any processor array. However, increased design and implementation costs should be expected when fault-tolerance is being introduced into the architecture of a processor array. When the processor array is implemented within a single VLSI chip, these cost increases are directly related to the chip silicon area. Thus, the increase in area should be weighed against the improved performance of the gracefully degrading fault-tolerant processor array. In addition, a larger chip area might reduce the wafer yield to an unaceptable level making the use of fault-tolerant VLSI processor arrays impractical. The objective of this paper is to devise performance measures for the evaluation of the effectiveness and area utilization of various fault-tolerant techniques. Another goal is to analyze the reduction in wafer yield and investigate the possibility of yield enhancement through redundancy.

Computing inductive noise of chip packages

Abstract: Inductive noise limits the physical design of high-speed, high pin-out chip packages. This paper presents the derivation of some basic equations that are useful for computing inductive noise of various chip packages, and also presents simple asymptotic and limiting results that reduce to some useful approximate results proposed by others. These results are helpful for computing inductive noise in arrays of wire bonds, solder balls, dual in-line package leads, package pins, and connector pins. Computed results agreed well with measured results. We present two simple rules for minimizing inductive noise and also discuss the inductive noise of power and ground planes.

System for improving signal-to-noise ratio in a direct sequence spread spectrum signal receiver

Abstract: A plurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different assigned code sequence shift. A receiver, synchronized to the clock, discriminates the signal transmitted by a predetermined transmitter from signals transmitted by the others by generating a first pseudo-random code that is a replica of the common bipolar pseudo-random code and has a code sequence shift corresponding to that of the predetermined transmitter, and a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unassigned code sequence shift. The difference between the first and second bipolar pseudo-random code sequences, which is a trinary code sequence, is cross-correlated with the incoming signal. The cross-correlation despreads only the signal having the predetermined code sequence shift. Each receiver includes a number of correlation detectors offset from each other by a fraction of a code chip, together with decision circuitry to identify cross-correlation peaks for optimum synchronization. The output of each sub-receiver is processed to extract data using weighting factors selected according to the particular distortion present, to improve signal-to-noise ratio.

Synchronization system for use in direct sequence spread spectrum signal receiver

Abstract: A plurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different assigned code sequence shift. A receiver, synchronized to the clock, discriminates the signals transmitted by a predetermined transmitter from signals transmitted by the others by generating a first pseudo-random code that is a replica of the common bipolar pseudo-random code and has a code sequence shift corresponding to that of the predetermined transmitter, and a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unassigned code sequence shift. The difference between the first and second bipolar pseudo-random code sequences, which is a trinary code sequence, is cross-correlated with the incoming signals. The cross-correlation despreads only the signal having the predetermined code sequence shift. Each receiver includes a number of correlation detectors offset from each other by a fraction of a code chip, together with decision circuitry to identify cross-correlation peaks. The cross-correlation output of a primary correlation detector generates in-phase and quadrature-phase correlation signals, with the quadrature-phase signal being at a minimum when the receiver and predetermined transmitter are perfectly synchronized with each other. The ratio of the in-phase and quadrature-phase signals are processed to identify the presence of a data signal within a background of noise and to improve synchronization lock between the receiver and predetermined transmitter.

Chip Substrate Resistance Modeling Technique for Integrated Circuit Design

Abstract: With the advent of VLSI and the use of statistical simulation techniques to perform integrated circuit design, modeling of chip substrate resistance is becoming increasingly important to successful chip design. This paper will present a substrate resistance modeling technique which may be applied to the design of both FET and bipolar chips. After briefly presenting the theory behind the technique, we will describe its use in developing a substrate resistance model required for studying a disturb problem encountered with a high-speed array chip. The steps involved in building and simplifying the substrate model will be described. The effect on circuit simulations and noise sensitivity will then be shown.

An experimental 1Mb DRAM with on-chip voltage limiter

Abstract: This paper will report on an experimental 21μm2cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm2

Method for fabricating modules comprising uniformly stacked, aligned circuit-carrying layers

Abstract: A method and related fixtures are disclosed which permit formation of stacks of thin circuitry-carrying layers. The layers terminate in an access plane having a two dimensional array of closely-spaced electrical leads. The method includes the steps of measuring the thickness of separate chips, selecting groups of chips having appropriate thicknesses, applying appropriate amounts of epoxy between adjacent chips, aligning the chips (and their electrical leads) in the direction parallel to their planes (i.e., the X-axis), and closing the cavity with an end wall which (a) exerts pressure on the stacked chips and epoxy in a direction perpendicular to the chip planes, and (b) establishes a fixed height of the stack in order to align the leads in the Y-axis. The final fixture provides a fixed-size cavity for confining the layers during curing of thermo-setting adhesive which has been applied between each adjacent pair of layers. An initial fixture is provided for accurately measuring the thickness of each layer under substantial layer-flattening pressure. An intermediate fixture is provided for wet stacking the layers prior to their insertion into the final fixture.

Low-inductance power/ground distribution in a package for a semiconductor chip

Abstract: A package for a semiconductor chip includes as an integral part thereof a frame-shaped multilayer ceramic capacitor. The chip is mounted within the capacitor structure. Conductive portions of the capacitor serve as the terminals and plates of the capacitor and as planar power and ground members for interconnecting an external power supply to the chip. By means of these planar members, power is distributed to the chip in a low-impedance, substantially transient-free manner without utilizing any of the multiple signal leds emanating from the package. Moreover, the signal leads are separated from the ground plane by a low-dielectric-constant material. As a result, the signal leads are minimally loaded and are characterized by a relatively constant impedance selected to optimize signal transfer to and from the chip.

Memory correction scheme using spare arrays

Abstract: Spare chips are employed together with a replacement algorithm to replace chips in memory array when failure is generally more extensive then unrelated cell fails in the memory chips. That is, substitution will be made if an error condition is a result of the failure of a whole chip (chip-kill), a segment of a chip (island-kill), a column of bits of a chip or a row of bits of a chip but will not be performed when it is due to a single failed cell. The replacement of a chip with a chip-kill or with an island-kill is done on the fly and involves only a row of the memory chips or elements leaving other elements of the memory unaffected by the replacement.

Fuse link for varying chip operating parameters

Abstract: Adjustment of operating parameters for a functional circuit is provided by fuse links (44) and (45). For a DRAM, the fuse links (44) control the various internal delays of a timing control generator (40) and fuse links (45) control the sensitivity of sense amplifiers by controlling an access control circuit (42). The sense amplifiers (14) determine the access parameters for a plurality of memory cell arrays (10) and (12). By varying the parameters of the sense amplifiers, the access parameters can be controlled by one adjustment on the central control circuitry.

Chipset synchronization arrangement

Abstract: Each chip (11, 12) of a microprocessor chipset is synchro­ nized by an associated controller (400) which adjusts a control signal (202) for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp (507) which compares the output of an internal clock in each chip with a reference system voltage (508).

Test input multiplexing circuit

Abstract: 57 A test signal, used to initialize an integrated circuit chip for testing, is multiplexed with a data input line (12) of the chip. The test signal circuitry (10) is inactivated during normal operation of the chip. The test circuitry (10) is activated only when a special input signal, which is a voltage at some midpoint between logic states, is applied to the data input (12).

Decoupled integrated circuit package

Abstract: High frequency noise is decoupled from a bus conductor which supplies power to an integrated circuit by insertion of a metallized ceramic chip in the space defined by the two parallel rows of leads extending from the circuit The ceramic chip is provided with a pair of rectangular leads, connected to respective of the metalized opposite surfaces thereof, which are respectively connected to the power supply leads of the circuit

Semiconductor assembly employing noneutectic alloy for heat dissipation

Abstract: A cooling means for a circuit chip device employs a noneutectic metal alloy to form a low thermal resistance bridging interface between the surface of the chip device and a heat sink. The alloy has a solidus-liquidus temperature range such that the solidus is slightly below the maximum operating temperature of the chip, and thus has the capability to reestablish and maintain the interface at a low thermal resistance if stressed during circuit operation, even with a low current load at the interface of the chip device and the heat sink. In addition to the chip interface, the above cooling means is also used at other interfacial regions of the heat sink, dependent on design, to achieve very low thermal resistance.

Hall effect device with overlapping flux concentrators

Abstract: A Hall effect device for responding to weak magnetic fields uses a small chip of gallium arsenide located between the overlapped ends of two flux concentrators The spacing between the concentrators may be as small as 95 micrometers The flux concentrator, which serve to enhance the device's sensitivity are made of amorphous magnetic material, ie a metallic glass, which has high permeability

Moment calculations by digital filters

Abstract: We present a simple recursive algorithm for computing moments of two-dimensional integer arrays. It uses only additions and can be implemented for high-speed and real-time computation at video rates. We describe Complementary Metal-Oxide Semiconductor (CMOS), Very Large-Scale Integrated (VLSI) implementation of the algorithm in a single chip that can calculate the 16 moments μi, j (i, j = 0, 1, 2, 3) (i.e., up to the sixth-order moment) on 512 × 512 array of 8-bit integers in real time (at video rate). Such a chip can have potential applications in image processing, graphics, and robotics. The basic building block of the system is a single-pole digital filter that is implemented by recursive addition. The complexities involved in designing the chip, as well as its area, are significantly reduced by taking advantage of the fact that the column samples of the data array can be processed at a much slower rate than the row samples. An estimate of the chip area obtained from the layout design of the individual cells is given.

Microstore: The Stanford analog memory unit

Abstract: An NMOS device has been developed which provides high speed analog signal storage and readout for time expansion of transient signals. This device takes advantage of HMOS-1 VLSI technology to implement an array of 256 storage cells. Sequential samples of an input waveform can be taken every 5 ns while providing an effective sampling aperture time of less than 1 ns. The design signal-to-noise ratio is 1 part in 2000. Digital control circuitry is provided on the chip for controlling the read-in and read-out processes. A reference circuit is incorporated in the chip for first order compensation of leakage drifts, sampling pedestals, and temperature effects.

A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuit

Abstract: A submicron CMOS 1-Mb RAM with a built-in error checking and correcting (ECC) circuit is described. An advanced bidirectional parity code with a self-checking function is proposed to reduce the soft error rate. A distributed sense circuit makes it possible to implement a small memory cell size of 20 /spl mu/m/SUP 2/ in combination with a trench capacitor technique. The 1M word/spl times/1 bit device was fabricated on a 6.4/spl times/8.2 mm chip. The additional 98-kb parity cells and the built-in ECC circuit occupy about 12% of the whole chip area. The measured access time is 140 ns, including 20 ns ECC operation.

Noncontact dynamic tester for integrated circuits

Abstract: Testing of integrated circuit process intermediates, such as wafers, dise or chips in various stages of production (test chips) is facilitated by a nonintrusive, noncontact dynamic testing technique, using a pulsed laser, with laser light modification to increase photon energy through conversion to shorter wavelength. The high energy laser light excites electron emissions to pass to the detection system as a composite function of applied light energy and of dynamic operation of the circuit; detecting those emissions by an adjacent detector requires no ohmic contacts or special circuitry on the integrated circuit chip or wafer. Photoelectron energy emitted from a test pad on the test chip is detected as a composite function of the instantaneous input voltage as processed on the test chip, in dynamic operation including improper operation due to fault. The pulse from the laser, as modified through light modification, the parameters of detection of bias voltages, and the distances involved in chip-grid-detector juxtaposition, provides emissions for detection of circuit voltages occurring on the test chip under dynamic conditions simulating actual or stressed operation, with high time resolution of the voltages and their changes on the circuit.

A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

Abstract: It is shown how distributed arithmetic techniques can be applied in parallel-data arithmetic computations to achieve highly regular and efficient VLSI structures on silicon. Two individual arithmetic processor chips are described as examples of the technique. The chips described, which are intended primarily for computation of the FFT butterfly, each contain the functional equivalence of two parallel pipelined multipliers. The first chip is an 8-bit prototype device which has been designed and fabricated on a standard 5-/spl mu/m silicon-gate n-channel MOS process. The second chip is a 16-bit CMOS-SOS design which uses a modified architecture to achieve higher clocking rates and improved versatility in systems use.