Showing papers on "Chip published in 1985"

Code Combining--A Maximum-Likelihood Decoding Approach for Combining an Arbitrary Number of Noisy Packets

Abstract: It is well known that if the data rate is chosen below the available channel capacity, error-free communication is possible. Furthermore, numerous practical error-correction coding techniques exist which can be chosen to meet the user's reliability constraints. However, a basic problem in designing a reliable digital communication system is still the choice of the actual code rate. While the popular rate-1/2 code rate is a reasonable, but not optimum, choice for additive Gaussian noise channels, its selection is far from optimum for channels where a high percentage of the transmitted bits are destroyed by interference. Code combining represents a technique of matching the code rate to the prevailing channel conditions. Information is transmitted in packet formats which are encoded with a relatively high-rate code, e.g., rate 1/2, which can be repeated to Obtain reliable communications when the redundancy in a rate-1/2 code is not sufficient to overcome the channel interference. The receiver combines noisy packets (code combining) to obtain a packet with a code rate which is low enough such that reliable communication is possible even for channels with extremely high error rates. By combining the minimum number of packets needed to overcome the channel conditions, the receiver optimizes the code rate and minimizes the delay required to decode a given packet. Thus, the receiver adapts to the actual jammer-to-signal (J/S) ratio which is critical when the level of interference J is not known a priori.

Security system for microcomputers

Abstract: A security system for a personal computer, in which hardware and software are combined to provide a tamper-proof manner of protecting user-access and file-access. The hardware component of the system is an expansion board for insertion into an expansion slot of the PC, and has a first EPROM chip containing four portions of machine code for initializing system function calls and for establishing the proper boot-processing of the PC; a second RAM chip serving as scratch pad memory; a third EEPROM chip storing passwords, audit trail log, protection and encryption system flags, and user-access rights; a fourth automatic encryption and decryption chip for files of the PC; and a fifth clock chip for the audit trail. The software component includes a batch file that runs a program in conjunction with the machine code on the EPROM of the expansion board ensuring access is gained only for valid users. The code on the EPROM monitors all DOS 21H file handling function calls, and initializes the 7CH interrupt vector for allowing the security system to access DOS and the files thereof. During boot processing, the 10H video interrupt handler is monitored to prevent circumventing the security system. Hard-disc format-protection is also provided by monitoring of the 13H interrupt function calls. Files may also be created that may not be copied.

Optical imaging applied to microelectronic chip-to-chip interconnections.

Abstract: An imaging system is proposed as an alternative to metallized connections between integrated circuits. Power requirements for metallized interconnects and electrooptic links are compared. A holographic optical element is considered as the imaging device. Several experimental systems have been constructed which have visible LEDs as the transmitters and PIN photodiodes as the receivers. Signals are evaluated at different source–detector separations. Multiple exposure holograms are used as a means of optical fan out allowing one source to simultaneously address several receiver locations. Limitations of this technique are also discussed.

Stacked double density memory module using industry standard memory chips

Abstract: A stacked double density memory module may be formed from two industry standard memory chips, by jumpering the unused and chip enable pins on one chip and then stacking the jumpered chip on the other chip with the pins on the jumpered (top) chip contacting the corresponding pins on the other (bottom) chip except for the chip select pins. In a preferred embodiment for use with 64K or one megabit DRAMs, the top chip is jumpered with a U-shaped strap which runs from the unused pin to the chip enable pin. The chip enable pin is bent toward the chip body to retain the strap in place. The technique may also be employed for stacking other industry standard memory or array chips.

Integrated circuit chip package

Abstract: An integrated circuit is mounted on, and electrically connected to an underlying substrate by the flip-chip technique. In this technique, the chip is inverted and bonding pads on the chip are soldered to correspondingly located bonding pads on the substrate. By the invention a continuous ribbon or loop of solder or polymer extends between the chip and substrate surfaces and defines a sealed cavity. Because the interior of the cavity is sealed from contaminants, conducting leads of the chip or substrate can be left uncovered within the cavity so reducing the capacitance of high frequency circuits. The substrate can be a connection medium such as a printed circuit board or could be another integrated circuit chip.

Code division multiplexer using direct sequence spread spectrum signal processing.

Abstract: A plurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different predetermined assigned code sequence shift A receiver, synchronized to the clock, discriminates the signal transmitted by a predetermined transmitter from signals transmitted by the others by generating a first bipolar pseudo-random code that is a replica of the common bipolar pseudo-radom code and has a code sequence shift corresponding to that of the predetermined transmitter, and a second bipolar pseudo-random code and has an unassigned code sequence shift The difference between the first and second bipolar pseudo-random code sequences, which is a trinary code sequence, is cross-correlated with the incoming signals The cross-correlation despreads only the signal applied by the sequence having the predetermined code sequence shift Each receiver includes a number of correlation detectors offset from each other by a fraction of a code chip together with decision circuitry to identify cross-correlation peaks for optimum synchronization

CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design

Abstract: In a hierarchical VLSI layout design, the block-level layout design is called a "chip floor plan" In this paper, a semi-automatic VLSI chip floor plan algorithm and its implementation are presented The initial block placement is obtained by an attractive and repulsive force method (AR method), and the subsequent block packing process is performed by gradually moving and reshaping blocks with chip boundary shrinking The chip area estimation is performed by using individual block area calculations from empirically obtained equations A set of interactive commands is also provided to facilitate the manual optimization processes using a color graphic terminal By processing several practical VLSI circuits, it is shown that the method is very effective for handling various kinds of blocks and is able to reduce the design effort required to achieve the chip floor plan

Self-timed random access memory chip

Abstract: A self-timed random access memory circuit is designed on a single monolithic integrated circuit chip. The chip includes a random access memory including addressable storage locations, address decoding circuitry, data input and output circuitry and write enable circuitry. In addition, the chip includes input latches connected to chip input terminals which store data, address and operation control signals from off-chip circuitry in response to a timing signal, also from the off-chip circuitry. Also in response to the timing signal, an output latch on the chip stores data from the random access memory for transmission to output terminals, where the data is available to the off-chip circuitry. The input and output latches permit the self-timed random access memory circuit to perform in a pipelined manner. In addition, the chip includes circuitry that generates the control signals, in response to the latched control signals, with the correct timing for controlling the random access memory, obviating the necessity of the system designer designing a system including the chip having to design off-chip control circuitry with the required timing.

Saw transition detector for PSK signals

Abstract: A phase transition detector for PSK signals which utilizes a dual channel SAW differential delay line to achieve a required delay. Each channel or path of the SAW device comprises an input and an output transducer. The two channels provide a predetermined differential delay (T) inasmuch as they are of different lengths. A PSK input signal is delivered to a power splitter, with the output therefrom coupled to the pair of input transducers of the SAW device. The output transducers are coupled to a multiplier which serves to detect phase transitions in the input PSK signal. The multiplier output is coupled to an output terminal via a low pass filter which provides harmonic repression. In another embodiment a SAW device comprises a bank of dual channel differential delay lines with each dual channel set to a different predetermined delay (T) so that a plurality of PSK signals of different chip rates can be separated out and detected. The PSK input signals are delivered to a power splitter, with the output therefrom coupled to a pair of input transducers of the SAW device. Output transducers are spaced predetermined distances from one or the other of said input transducers. Parallel sets of multipliers and low pass filters are coupled to predetermined SAW output transducers. Each multiplier serves to detect the phase transitions in one, and only one, PSK input signal. The input transducer(s) can be placed near the center of the SAW device, with the output transducers placed on the same, or either, side of the input transducer(s).

Chip card system

Abstract: 1. Chip card system with chip cards for use as a money substitute, as an identity card or as a storage medium, with which a single chip card (1) can be used successfully for different application cases, with which different areas of money (11 , 12 ... 1n ), integrated into the chip, or of a function unit are provided for the different application cases, a selection circuit (121) being provided in the chip for the selection of the different areas in the chip, for which circuit a certain selection procedure is fixed, by which it can be ensured that the areas relevant for the application case concerned and only these are assigned, that a processor (12), by which the processes necessary for the different specific application cases are executed, is provided for specific application cases as a function unit, this multifunctional chip card (1) being suitable to act together with an input/output device (2), in which a combination control element permitting activation is provided and into which the chip card (1) can be inserted and which additionally contains a power source for mobile use, and the input/output device (2) being connectable to a wireless transmitting/receiving device (3) for communication with a stationary device, characterized in that the processor (2) is fitted in the chip in a way known per se, in that this stationary device for its part contains a device which, if a plurality of mobile devices are present in the local area concerned, controls a multiple access in a way known per se and, if appropriate, according to a priority list, and in that the input/output device (2) remains in the ready-to-receive state for specific applications and, in response to the reception of a signal from the stationary station, with which the latter transmits an item of application information, automatically sends the required message.

A decomposition algorithm for circuit routing

Abstract: The circuit routing problem on a VLSI chip is an extremely large linear program with a very large number of rows and columns, too large to be solved even with the column-generating techniques. Based on the distribution of nets, we recursively cut the area of the chip into smaller and smaller regions until the routing problem within a region can be handled by the Dantzig-Wolfe decomposition method. Then we successively paste the adjacent regions together to obtain the routing of the whole chip.

Charge pump for use in a phase-locked loop

Abstract: An improved charge pump for use in a phase-locked loop is disclosed in which there is only one current source, and in which all switching components pass current in the same direction. The charge pump may thus be constructed entirely of NPN transistors, which makes it possible to embody it in a single integrated circuit chip. The pump up and pump down currents inherently have the same magnitude and transient characteristics, thus minimizing steady-state errors.

Semiconductor chip with recessed bond pads

Abstract: A semiconductor chip having bond pads formed on a peripheral ledge recessed below the active chip surface. Ultrasonic wire bonds are made with the pads to lie below the active chip surface.

Programmable integrated circuit fault detection apparatus

Abstract: An integrated circuit fault detection system. The integrated circuit fault detection system includes gate means associated with each functional input and functional output of the chip. The gate means are connected between the functional input and functional output terminals and the bonding pad and are controllable to allow the chip to operate in normal fashion using the input and output terminals thereof and the bonding pads associated therewith. The gate means are also controllable to read test data into a functional input terminal of the chip, write test data out of the functional output terminal of the chip, drive test data from chip functional circuitry through the bonding pad off chip, and accept test data from the outside world through a bonding pad and transfer the test data to chip functional circuitry. The test results can then be analyzed to determine if the chip is functioning properly.

Manufacturing test data storage apparatus for dynamically reconfigurable cellular array processor chip

Abstract: A cellular array processor chip potentially having an unknown number of defects randomly located thereon includes a machine readable record of each defect location, integrated thereon. The record can be a PROM that is programmed at, or after, the end of manufacturing testing.

Ring network for communication between one chip processors

Abstract: The present invention relates to a data transmission system having a ring network for communication between one chip processors each having a serial transmitter and serial receiver. Each one chip processor can operate as an independent local processor or as a network controller communicating via a network driver and the ring network with other one chip processors. Transmission privilege is transformed from a first one chip processor having completed transmission to the next processor in sequence which is ready for transmission, thereby reducing unnecessary waiting time.

VLSI Architecture for a one chip video median filter

Abstract: Real-time image processing in an application environment needs a set of low-cost implementations of various algorithms. This paper presents a one chip VLSI median filter based on a systolic processor and working at video rate. It includes its own memory and can be used without any image memory for on-line processing. The architectural choices have made it possible to design a small size chip with a high performance level.

Chip-on-chip semiconductor device having selectable terminal connections

Abstract: A circuit configuration in a chip for a semiconductor device based on so-called chip-on-chip technology. The chip has a selecting circuit which switches, according to the control signals supplied thereto, an input of an internal circuit formed on the chip to connect to an output of the internal circuit or to an input terminal for receiving signals from another chip with which the chip is to be interconnected in a completed chip-on-chip structure. The control signals to operate the selecting circuit can be supplied without using large terminals to be connected to an external circuit, by simple impedance means and biasing means respectively provided for the chip and the other chip.

Microstore - The Stanford Analog Memory Unit

Abstract: An NMOS device has been developed which provides high speed analog signal storage and readout for time expansion of transient signals. This device takes advantage of HMOS-1 VLSI technology to implement an array of 256 storage cells. Sequential samples of an input waveform can be taken every 5 ns while providing an effective sampling aperture time of less than 1 ns. The design signal-to-noise ratio is 1 part in 2000. Digital control circuitry is provided on the chip for controlling the read-in and read-out processes. A reference circuit is incorporated in the chip for first order compensation of leakage drifts, sampling pedestals, and temperature effects.

Chip on chip type integrated circuit device

Abstract: A circuit for checking the integrity of interconnections between chips in a chip-on-chip type IC device is fabricated in respective portions on the lower and upper chips in peripheral areas thereof intermediate the inner logic circuit of each chip and the corresponding bonding pads. Selection circuits connected between the inner logic circuit signal terminals and the corresponding bonding pads of the chip are switched by control signals to be isolated and permit normal operation of the chip or to a checking mode to isolate the inner logic circuit and permit transmission of test signals through the interconnections. The test signals received through the interconnections are compared with the test signals as transmitted to determine the integrity of the individual interconnections. The disclosed apparatus and method provide for testing of the integrity of interconnections defining single direction signal paths of individual interconnections, as between the upper and lower chips, and for selectively bidirectional transmission through the individual interconnections.

Chip carrier alignment device and alignment method

Abstract: A device and method for aligning and assembling castellated chip carriers with other electrical components such as printed circuit boards or other chip carriers is disclosed. The device provides means for compressively engaging the castellations in the chip carrier thereby providing precise alignment and positioning of the chip carriers relative to other components with which it is assembled. A method utilizing the device and a solder column placement device to produce a pre-leaded castellated chip carrier is also disclosed.

Apparatus and method for fabricating modules comprising stacked circuit-carrying layers

Abstract: A method and related fixtures are disclosed which permit formation of stacks of thin circuitry-carrying layers. The layers terminate in an access plane having a two dimensional array of closely-spaced electrical leads. The method includes the steps of measuring the thickness of separate chips, selecting groups of chips having appropriate thicknesses, applying appropriate amounts of epoxy between adjacent chips, aligning the chips (and their electrical leads) in the direction parallel to their planes (i.e., the X-axis), and closing the cavity with an end wall which (a) exerts pressure on the stacked chips and epoxy in a direction perpendicular to the chip planes, and (b) establishes a fixed height of the stack in order to align the leads in the Y-axis. The final fixture provides a fixed-size cavity for confining the layers during curing of thermo-setting adhesive which has been applied between each adjacent pair of layers. An initial fixture is provided for accurately measuring the thickness of each layer under substantial layer-flattening pressure. An intermediate fixture is provided for wet stacking the layers prior to their insertion into the final fixture.

Chip-like electronic component series

Abstract: A chip-like electronic component series retains a plurality of chip-like electronic components (2) distributed along a longitudinal direction of a tape (1). The tape (1) is formed with a plurality of cavities (5) distributed in its longitudinal direction, so that the chip-like electronic components are received in respective ones of the cavities. In order to retain the chip-like electronic components in the cavities, the cavities are covered by a cover sheet (3). Each of the cavities comprises a relatively flat receiving portion (7) having a bottom surface (6) extending along the longitudinal direction of the tape and a projecting receiving portion (8) projecting from a part of the bottom surface of the flat receiving portion. With such configuration, the cavities can retain at least two types of chip-like electronic components of different geometry or retain the chip-like electronic components at least in two types of conditions.

CUSP: A 2-/spl mu/m CMOS Digital Signal Processor

Abstract: This paper describes the Cornell University Signal Processor (CUSP), a 60 000 transistor 2-/spl mu/m CMOS processor custom designed to compute the Fast Fourier Transform (FFT) and related algorithms. Operating on a 50-MHz clock, the bit-serial arithmetic hardware on a CUSP chip performs over 15 million 20 X 20 bit multiplications per second and computes a 1024 point FFT in 1.33 ms. The chip architecture is presented along with a description of the arithmetic, control, and fault detection circuitry. The inclusion of these components on a single chip is shown to allow large fault tolerant arrays of CUSP processors to be efficiently employed for high-performance applications.

A triple-level wired 24K-gate CMOS gate array

Abstract: A 24K-gate CMOS gate array has been developed using triple-level wiring and a hierarchical layout method. A typical delay time is 1.6 ns with a fanout of 3 and a 3-mm metal interconnect length. The master chip was designed to be freely divided into blocks. A previously developed digital signal processor has been realized on the array. The design time was reduced to 25% of the normal design cycle although the chip size is 3.3 times larger than was realized by a handcrafted design.

Temperature compensation cmos to ecl translator

Abstract: The present invention is a temperature compensating circuit adapted for use with a CMOS to ECL interfacing circuit which uses one normally unused ECL logic gate, formed on a chip of many ECL logic gates for generating the supply voltages for the level interfacing circuit such that the output voltage levels from the interfacing circuit will automatically track with the temperature experienced by the chips' ECL logic gates.

Semiconductor wafer prober

Abstract: PURPOSE:To improve accuracy and reliability by a method wherein needle mark traces of 2 or more chips are added to a pad of a chip to be measured and the marks 2 of 2 or more chips are recognized and compared with each other to perform self-correction automatically. CONSTITUTION:A semiconductor wafer 1 is fixed on a mounting table 3 which moves to the X-axis, Y-axis and Z-axis directions and rotates along the circumference direction with the Z-axis as the center of rotation. The position where a probe card needle 2 touches the pad 5 of the chip 4 is nominated as the point O and the position where the needle mark traces are recognized is nominated as the point P. The needle 2 touches the chip 4 and adds a needle mark R on the pad 5. Then the probe card needle part is shifted to the left from the point O and the needle mark trace R' is added. Then the chip 4 is transferred to the designated position by the rotation of an X-axis motor. Then another one needle mark trace R is added. Then the chip is transferred to the point P. At the recognition point P, two handle mark traces actually added are recognized and compared with each other. The inclination and discrepancy of parallel lines at that time are calculated and automatically corrected.

Adaptive Spread-Spectrum Systems Using Least-Squares Lattice Algorithms

Abstract: Practical communication systems must cope with many uncertainties in addition to determining the transmitted data, e.g., the direction, timing, and distortion of the desired signal, and the spectral and spatial distribution of the interference, all of which may change with time. This paper describes exact least-squares (LS) recursive lattice algorithms which resolve these uncertainties in a direct-sequence spread-spectrum digital communication system. The adaptive LS algorithm is recursive beth in order and time, and converges rapidly to the uncertain parameters. Time-discrete algorithms may be mechanized by a receiver containing integrate-and-dump circuits operating at the chip rate of the pseudonoise (PN) sequence, one in each in-phase and each quadrature channel of each sensor array element's output. Different configurations of optimal time-discrete receivers are presented and transformed into adaptive receivers by taking advantage of the spectral properties of the different kinds of LS filters. Simulation results are presented and some guide lines are given for the architecture of an adaptive direct-sequence spread-spectrum system.

A study of continuous/discontinuous chip formation using acoustic emission

Abstract: Chip formation control is an important problem in unmanned machining operations. Short, discontinuous chips are often most desirable to avoid entanglement with tooling and to aid with mechanized removal systems. Chip formation conditions can change during machining, especially with single-point turning. Experiments were conducted on a machining center. Conditions of feedrate-induced segmented chips correlate well with the count rate of acoustic emission (AE). The sensitivity of AE signals to chip congestion or entangling due to continuous chip formation is illustrated.