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Showing papers on "Chip published in 1988"


Journal ArticleDOI
TL;DR: In this paper, a deconvolution operation performed in the logarithmic time domain gives the "timeconstant spectrum" of the chip-case-ambient thermal structure.
Abstract: A new method has been developed in order to identify the thermal environment of a semiconductor device chip. The identification algorithm operates on the thermal transient response of the device recorded during a one-shot pulse measurement. A deconvolution operation performed in the logarithmic time domain gives the “time-constant spectrum” of the chip-case-ambient thermal structure. A further transformation leads to the “structure-function” that is the cross-sectional area of the heat conducting materials vs thermal resistance (related to the heat source). The structure function has a good and quantitatively evaluable correspondence to the physical chip environment and heat conducting structure. Separating the different regions of the heat-flow path (corresponding to the chip, bond, header, case) as well as the detection of eventual heat-transport irregularities (mounting errors) is possible.

419 citations


Patent
19 Feb 1988
TL;DR: In this article, the alpha barrier is used to cover a substantial portion of the surface of the chip and thereby serve as conduits for the dissipation of heat from the chip.
Abstract: The present invention is directed to a packaged semiconductor chip which effectively dissipates heat and has improved performance. The packaged chip has a plurality of lead frame conductors extending through the encapsulating material which are adhesively joined to the semiconductor chip, preferably by means of an alpha barrier. The conductors cover a substantial portion of the surface of the chip and thereby serve as conduits for the dissipation of heat from the chip. Wires are bonded to the conductors and extend from the conductors to the terminals on the semiconductor chip. In a preferred embodiment the semiconductor chip terminals are located along a center line of the chip. This allows for short connecting wires which in turn contribute to faster chip response.

353 citations


Patent
04 Nov 1988
TL;DR: In this article, a plurality of integrated circuits are packaged within chip carriers and stacked, on one top of the other, on a printed circuit board, each of the input/output data terminals, power and ground terminals of the chips are connected in parallel.
Abstract: A device for increasing the density of integrated circuit chips on a printed circuit board. A plurality of integrated circuits are packaged within chip carriers and stacked, on one top of the other, on a printed circuit board. Each of the input/output data terminals, power and ground terminals of the chips are connected in parallel. Each chip is individually accessed by selectively enabling the desired chip.

240 citations


Journal ArticleDOI
TL;DR: In this paper, the authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model.
Abstract: The authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model. It consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The circuit can be operated in several different configurations by programming the interconnections between the processors. Tests made with the circuit working as an associative memory and as a pattern classifier were so encouraging that the chip has been interfaced to a minicomputer and is being used as a coprocessor in pattern-recognition experiments. This mode of operation is making it possible to test the chip's behavior in a real application and study how pattern-recognition algorithms can be mapped in such a network. >

183 citations


Patent
23 Jun 1988
TL;DR: In this paper, a custom crossbar interconnection chip is presented, which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports.
Abstract: The interconnection chip of the present invention is a custom chip which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports. The chip includes a crossbar interconnection, a FIFO or programmable delay for each of its inputs and a pipeline register file for each of its outputs. By using pre-stored control patterns, the chip can configure its crossbar and delays while performing other operations. Therefore, the usual functions of busses and register files can be realized with this single chip. Various embodiments and applications for the chip are disclosed.

139 citations


Journal ArticleDOI
TL;DR: In this paper, a continuous-time all-MOS universal filter structure is proposed, which achieves complete MOS nonlinearity cancellation and does not require the use of fully balanced op-amps.
Abstract: A continuous-time all-MOS universal filter structure is proposed. The structure is based on the MOSFET-C design approach. It achieves complete MOS nonlinearity cancellation and does not require the use of fully balanced op-amps. General topological requirements are established that are necessary for the conversion of active-RC prototypes to MOSFET-C counterparts, such that MOS nonlinearity cancellation is achieved. Accordingly, a universal active-RC prototype filter structure, which meets the necessary requirements, is presented and its MOSFET-C version is developed. Nonideal effects that may degrade the performance at high frequency are discussed and ways for improvement are proposed. Results obtained from a test chip have verified the viability of the proposed structures. The chip is an implementation of a MOSFET-C universal filter in a 3.5- mu m CMOS process. The filter is successfully tuned over a wide range of pole frequencies (0 to 100 kHz) using op-amps with a measured gain bandwidth of only 1.2 MHz. >

126 citations


Book
01 Sep 1988
TL;DR: Chip-level modeling offers an alternative approach to model development that still represents timing accurately and the use of hardware description languages (HDLs) to achieve the desired accuracy is examined.
Abstract: VLSI circuits have made gate-level modeling of large-scale systems impractical. Chip-level modeling offers an alternative approach to model development that still represents timing accurately. The authors examine this approach to modeling and the use of hardware description languages (HDLs) to achieve the desired accuracy. The characteristics of chip-level models are reviewed and sample models are presented. HDL code for each model is given to illustrate its use. Fault modeling in a chip level is examined. >

98 citations


Journal ArticleDOI
TL;DR: The CLIP7 image-processing chip is implemented as a custom designed integrated circuit and contains a single processing element for use in arrays of processors, used both to study the application of partial local autonomy techniques to image processing and as a fast and convenient system for the emulation of other architectures.
Abstract: A description is given of the CLIP7 image-processing chip. The device is implemented as a custom designed integrated circuit and contains a single processing element for use in arrays of processors. The chip uses 16-bit internal and 8-bit external data buses and divides crudely into two major sections: data processing and data input/output. The first structure to be assembled using these processors is a 256-element linear array, each element incorporating two of the CLIP7 processors. This system, known as CLIP7A, is used both to study the application of partial local autonomy techniques to image processing and also as a fast and convenient system for the emulation of other architectures. CLIP7A software and hardware are also described. >

96 citations


Journal ArticleDOI
R. B. Arps1, T. K. Truong1, D. J. Lu1, R. C. Pasco1, T. D. Friedman1 
TL;DR: A VLSI chip for data compression has been implemented based on a general-purpose adaptive binary arithmetic coding (ABAC) architecture, which permits the reuse of adapter and arithmetic coder logic in a universal way, which together with application-specific model logic can create a variety of powerful compression systems.
Abstract: A VLSI chip for data compression has been implemented based on a general-purpose adaptive binary arithmetic coding (ABAC) architecture. This architecture permits the reuse of adapter and arithmetic coder logic in a universal way, which together with application-specific model logic can create a variety of powerful compression systems. The specific version of the adapter/coder used herein is the "Q-Coder," described in various companion papers. The hardware implementation is in a single HCMOS chip, to maximize speed and minimize cost. The primary purpose of the chip is to provide superior data compression performance for bilevel image data by using conditional binary source models together with adaptive arithmetic coding. The coding scheme implemented is called the Adaptive Bilevel Image Compression (ABIC) algorithm. On business documents, it consistently outperforms such nonadaptive algorithms as the CCITT Group 4 (T.6) Standard and comes into its own when adapting to documents scanned at different resolutions or which include significantly different data such as digital halftones. The multi-purpose nature of the chip allows access to internal partition combinations such as the "Q" adapter/coder, which in combination with external logic can be used to realize hardware for other compression applications. On-chip memory limitations can also be overcome by the addition of external memory in special cases. Other options include the uploading and downloading of adaptive statistics and choices to encode or decode, with or without adaptation of these statistics.

85 citations


Journal ArticleDOI
TL;DR: A family of architectural techniques are proposed which offer efficient computation of weighted Euclidean distance measures for nearest-neighbor codebook searching and very high vector-quantization (VQ) throughout can be achieved for many speech and image-processing applications.
Abstract: A family of architectural techniques are proposed which offer efficient computation of weighted Euclidean distance measures for nearest-neighbor codebook searching. The general approach uses a single metric comparator chip in conjunction with a linear array of inner product processor chips. Very high vector-quantization (VQ) throughout can be achieved for many speech and image-processing applications. Several alternative configurations allow reasonable tradeoffs between speed and VLSI chip area required. >

79 citations


Journal ArticleDOI
TL;DR: In this article, a low-power 16-bit CMOS D/A (digital/analog) converter for portable digital audio is described, which is based on current division.
Abstract: A low-power 16-bit CMOS D/A (digital/analog) converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric averaging technique is used to minimize the harmonic distortion of the converter at high signal levels. The dynamic range is 95 dB. The circuit operates in a time-multiplex mode at a sample frequency of 44 kHz in a power supply range of 2.5-5 V and has a power consumption of 15 mW. A 2- mu m CMOS technology is used and the active chip area is 5 mm/sup 2/. >

Journal ArticleDOI
TL;DR: In this article, the performance of six commercially available chip forming tool inserts has been assessed and the tool restricted contact effect determining the chip streaming (i.e. chip backflow) has been found to be a major influencing factor in chip breaking.

Patent
27 Jun 1988
TL;DR: In this article, the VIA layer is programmed with connections or "vias" at specific locations between the signal layer and a power or ground layer above or below the signal layers.
Abstract: Ceramic packages for encapsulating integrated circuit (IC) chips are made of layers which are laminated together in a co-firing process. A signal layer includes leads electrically connecting external pins with the chip itself. Other layers supply ground and power to the chip by way of the signal layer. The layers are designed so that when a new chip is to be introduced, only one layer of the package, called a "VIA layer," needs to be re-designed for the new chip. The VIA layer is programmed with connections or "vias" at specific locations between the signal layer and a power or ground layer above or below the signal layer. The "vias" are conductive dots that extend through the VIA layer. The layer opposite the signal layer on the other side of the VIA layer contains "internal supply and ground bars" that are electrically connected to internal supply and ground layers. Therefore, selective positioning of the vias enables each signal lead in the signal layer to be selectively connected to internal power or ground. The internal supply and ground bars are aligned transversely with respect to the signal lead, and are close to the chip to minimize the inductance of the connections. For custom chip designs, the programmed VIA layer enables certain bonding areas to be preassigned to power and ground while permitting the circuit designer to freely select the assignment of the external pins.

Patent
15 Jan 1988
TL;DR: In this paper, a method and semiconductor structure for intermixing circuits of two or more different cell classes on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes.
Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Patent
15 Aug 1988
TL;DR: In this paper, the ink in an ink jet is sensed by a capacitor, one plate of which is coupled to ground through the ink, and the absence of ink will appear as a decreased amount of capacitance.
Abstract: The ink in an ink jet is sensed by a capacitor, one plate of which is coupled to ground through the ink. The absence of ink will appear as a decreased amount of capacitance. In this case the charge of the capacitor will leak off faster, and a sample and hold circuit can sense this to output a signal indicating the absence of ink. The charging signal can either be generated on the chip, which is made from silicon, or can be supplied to the chip. The number of pins on the chip taken for this sensing function can be minimized by multplexing the states of signals supplied to the chip for other purposes to generate the necessary signals to control and operate this sensor.


Patent
13 Jun 1988
TL;DR: In this article, a test/load bus is used to load test data and other data onto the integrated circuit chip, to sample test points and to read data previously loaded onto the chip.
Abstract: A system and method for testing nodes, or test points, of an integrated circuit are presented. The invention includes a test/load bus which is used to sequentially load test data and other data onto the integrated circuit chip, to sample test points and to read data previously loaded onto the chip. The test/load bus and its control logic are used for both testing the chip and for loading and dumping data from the chip so that the test capability adds little to the area of the chip.

Journal ArticleDOI
TL;DR: In this article, the design techniques for realizing eight 32-tap transversal filters on a single-CMOS IC are discussed, which is capable of processing signals at a rate of 500 million multiplications and accumulations per second, while achieving a high dynamic range.
Abstract: Design techniques for realizing eight 32-tap transversal filters on a single-CMOS IC are discussed The IC is capable of processing signals at a rate of 500 million multiplications and accumulations per second, while achieving a high dynamic range The IC contains 32 sample-and-holds, a 32*32 analog multiplexer, eight 32-input summing amplifiers, and all of the needed control circuitry The chip was fabricated using a standard CMOS, p-well process with double polysilicon All of the necessary analog sampled-data and digital control circuits were realized on a 307*315 mil/sup 2/ die >

Patent
Chin-Long Chen1
19 Apr 1988
TL;DR: In this article, a reduced redundancy error correction and detection code for memory organized with several bits of the data word on each chip is presented, which will correct all errors on any one chip and detect errors on more than one chip.
Abstract: A reduced redundancy error correction and detection code is shown for memory organized with several bits of the data word on each chip. This package error correction and detection will correct all errors on any one chip and detect errors on more than one chip. A certain arrangement of an ECC matrix is first created for a symbol size code greater than the number of bits per chip. Thereafter certain columns of the matrix are removed to create the final code having a symbol size the same as the number of bits per chip. A specific example of an 80 bit code word is shown having 66 data bits and 14 check bits for a 4-bit-per-chip memory.

Patent
19 Sep 1988
TL;DR: In this paper, a laser programmable integrated circuit chip has a plurality of logic modules organized as rows and columns, which are connected by a grid-like array of conductors.
Abstract: A laser programmable integrated circuit chip has a plurality of logic modules organized as rows and columns. The modules and other chip components are connected by a grid-like array of conductors. The conductors are initially unattached. Customization occurs by fusing laser diffuseable links and severing cut points on the conductors. The modules have continuous conductor lines running through them. These conductor lines aid in testing and are useful in routing and error avoidance. The chip also contains test registers to test the array of logic modules, the input/output blocks, and the conductors.

Proceedings ArticleDOI
11 Apr 1988
TL;DR: A 1.2- mu m CMOS chip set (processor and controller) has been designed for applications in high-performance fast Fourier transform (FFT)-based digital signal processing (DSP) systems.
Abstract: A 1.2- mu m CMOS chip set (processor and controller) has been designed for applications in high-performance fast Fourier transform (FFT)-based digital signal processing (DSP) systems. The processor chip performs about 500 million arithmetic operations per second and operates at an I/O rate of 5 billion bits per second. The controller chip provides total system control for FFT-based DSP systems. Algorithms such as FFT, spectrum analysis, digital filtering (via frequency domain) can be defined on the chip set by coding 5 to 10 instructions in the controller. Although a single chip set can process data rates at very high speeds (e.g. 1 K FFT in 16 mu s), multiple stages can be cascaded very simply for extremely high performance (up to 100-MHz data rates). >

Patent
14 Oct 1988
TL;DR: The chip carrier mosaics as mentioned in this paper can be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.
Abstract: A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high-performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carriers in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.

Proceedings ArticleDOI
07 Jun 1988
TL;DR: A single-chip two-dimensional discrete cosine transform processor that meets the challenge of high throughput rate and versatility and versatility with a die area as small as 40 mm/sup 2/.
Abstract: A single-chip two-dimensional discrete cosine transform processor is presented. This chip meets the challenge of high throughput rate (13.5 MHz) and versatility (block size from 4*4 to 16*16, and direct and inverse DCT) with a die area as small as 40 mm/sup 2/. An efficient optimized architecture providing high computation power is described. The chip is found to exhibit excellent precision performances. A full-custom approach was chosen because of the required speed and economic reasons (implementation of a low-cost real-time video coder/decoder). The chip uses a 1.25- mu m CMOS technology and contains 114000 transistors on 5.4*7.5 mm/sup 2/. >

Patent
05 Aug 1988
TL;DR: In this article, a random sequencer is used to generate a pseudo-random data bit pattern to be written into the cells of a DRAM chip, which can be used to test the functionality and maximum operating speed of the DRAM.
Abstract: A method and apparatus for testing the functionality and maximum operating speed of a dynamic random access memory (DRAM) chip includes a random sequencer circuit for generating a pseudo-random data bit pattern to be written into the cells of a DRAM chip. The apparatus includes a variable clock circuit which produces a continuously variable frequency clock signal to continuously increase the speed at which data is written into the DRAM. During read cycles of the DRAM, data read from the DRAM is compared with the pattern produced by the random sequencer in a comparator, and any non-correspondence between bits will activate an LED to indicate a failure of the chip. In this way, the maximum speed of the chip may be determined to isolate both defective and marginally damaged chips. The apparatus is operated as a stand-alone unit which does not require the use of any software or interfaced host microprocessor.

Patent
29 Nov 1988
TL;DR: An architecture for a dynamic video random access memory on a single integrated circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information in the RAM was proposed in this article.
Abstract: An architecture for a dynamic video random access memory on a single integrated circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information in the RAM and further having the write masking circuitry for modifying selected portions of the line of stored video information between selected START and STOP bit locations within the line.

Journal ArticleDOI
TL;DR: In this article, a 128-channel readout chip for readout with 50 μm pitch has been developed in CMOS technology, which provides signal amplification, parallel data storage and serial readout.
Abstract: A 128 channel readout chip suitable for readout with 50 μm pitch has been developed in CMOS technology It provides signal amplification, parallel data storage and serial readout Switched capacitor technique is used for noise reduction by multicorrelated sampling and simultaneously for second stage amplification Power consumption is controlled by an externally applied reference voltage thereby allowing for an optimization of speed and noise versus power consumption for the individual needs of the particular experiment Pulsed mode operation for further reduction of heat dissipation is easily possible without cutting the supply voltages Very good noise performance (250+45 C D [pF] electrons) low input impedance ( C eff > 200 pF) and large amplification (70 mV/fC) have been obtained at very low power consumption (16 mW per channel) The chip may be used for both synchronous (eg collider) and asynchronous (fixed target) applications where the time of the event is not known in advance A second version with only 64 channels suitable for 100 μm pitch is in preparation Further developments presently under way include the introduction of combinded CMOS-JFET technology

Journal ArticleDOI
TL;DR: In this article, a heat-transfer study is conducted for the steady-state internal thermal resistance of a multichip packaging technology for VLSI-based systems, where chips flip-chip soldered and interconnected on a silicon substrate.
Abstract: A heat-transfer study is conducted for the steady-state internal thermal resistance of a multichip packaging technology for VLSI-based systems. This technology, which is known as advanced VLSI packaging (AVP), has chips flip-chip soldered and interconnected on a silicon substrate. AVP's thermal management approach is to dissipate chip power through the silicon substrate to a heat sink or other packaging levels. The authors found a need to control the chip-to-substrate interface; therefore, they use a three-dimensional heat conduction analysis to characterize this interface. They simulate thermal performance of typical AVP assemblies affected by thermal vias, solder bump heights, high-power I O drivers, and chip sizes. The authors also analyze and measure the internal resistances of an experimental package consisting of three WE32100 chips. These resistances are predicted as 3.7, 4.7, and 5.0 degrees C/W, respectively; they are confirmed by the experimental data. The authors demonstrate the low thermal resistance achieved: 3.0 degrees C/W for a 1-cm square chip and 10 degrees C/W for a 0.25-cm square chip. They also provide their insight into the roles of different conduction paths involved. >

Patent
15 Nov 1988
TL;DR: In this paper, a spread spectrum communication system includes an encoder for differentially encoding a spreading code sequence in accordance with an input data signal, and a differential data decoder where the presently received chip of the spread spectrum signal and a corresponding previously received chip, received a fixed time delay previously, are compared one chip at a time.
Abstract: A spread spectrum communications system includes an encoder for differentially encoding a spread spectrum spreading code sequence in accordance with an input data signal. Each chip of the spreading code sequence is inverted, or not inverted, relative to the polarity of a corresponding chip of the spreading code sequence a fixed time delay previously, depending on whether the input data is a logic one or zero, respectively. At the receiver, the data is recovered in a differential data decoder wherein the presently received chip of the spread spectrum signal and a corresponding previously received chip of spread spectrum signal, received a fixed time delay previously, are compared one chip at a time. Since it is the spreading code sequence that is differentially encoded and differentially decoded, there is no need for a synchronized code sequence generator at the receiver, and data synchronization is achieved after one cycle time of the received spread spectrum spreading code sequence has elapsed.

Patent
22 Feb 1988
TL;DR: In this paper, a multi-gate light valve for an electro-optic line printer is described, where the different elements are uniquely combined in a package utilizing VLSI principles.
Abstract: This invention relates to an electro-optic modulator device, such as a multi-gate light valve for an electro-optic line printer, wherein the different elements are uniquely combined in a package utilizing VLSI principles. A specially designed integrated circuit package is utilized to enable the bonding of one or two electro-optical devices as a single unit. As each electro-optical device has its chip pads at one end of the device, special modifications need to be made to joint the pads to the external connectors. The electro-optical crystal, which may be mounted on a glass plate, is bonded to the integrated circuit chip. Sonic bonding or the two layer metal technique may be used for the crystal to chip bonding.

Journal ArticleDOI
TL;DR: A new and accurate method is described for the accurate characterization of worst-case limit-cycle behaviour and other finite word-length effects in digital filters based on a simulated annealing procedure with a general scope to keep the required CPU times reasonable.
Abstract: The accurate characterization of worst-case limit-cycle behaviour and other finite word-length effects in digital filters constitutes a challenging and important optimization application. Indeed, for a chip implementation this can lead to a significant reduction in the signal word-length and hence to considerable savings in terms of the final chip area. This paper describes a new and accurate method for this investigation which is based on a simulated annealing procedure with a general scope. Novel methods for dynamically and efficiently updating the essential parameters of the annealing schedule keep the required CPU times reasonable. The quality of the results obtained with our optimization routine and the general applicability of our approach are further substantiated with some promising results for the quantization of coefficients in arbitrary digital filters.