Showing papers on "Chip published in 1989"

A family of VLSI designs for the motion compensation block-matching algorithm

Abstract: A family of modular VLSI architectures and chip implementations of the motion-compensation full-search block-matching algorithm are described. This set of application-specific integrated circuits is motivated by the intensive computations required to perform motion compensation in real time. The architectures are based on data-flow designs, which allow sequential inputs but perform parallel processing with 100% efficiency. On the basis of these architectures, a programmable chip can be designed for motion vector estimation with different block sizes. The chips can be cascaded for a larger tracking range or for a video source with a higher pixel sampling rate. A chip-pair design is also derived for calculating fractional motion vectors with quarter-pel precision. The chip-pair design has been laid out, and the chip characteristics are given. Test circuitry is also included to increase the testability of the chips. >

VLSI implementation of a 16*16 discrete cosine transform

Abstract: The implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented. The chip contains 32 processing elements working in parallel and a random-access memory (RAM) which performs a 16*16 matrix transposition. The structure is highly regular and modular, and thus very efficient for VLSI implementation. The chip was designed for real-time processing of 14.3-MHz sample video data. It performs an equivalent of a half billion multiplications and accumulations per second. Fabricated in 2- mu m double-metal CMOS technology, the chip contains approximately 73000 transistors which occupy a 7.2*7.0-mm/sup 2/ area. The 68-pad die size is 8.3*8.1 mm/sup 2/. It is fully functional and is the first working 16*16 DCT chip. The architecture and accuracy studies for finite-wordlength processing are presented. The circuit design and layout using the symbolic design tool MULGA are described in detail. Possible variations are also discussed for multipurpose (variable transform sizes, forward-inverse transform) applications. >

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

Abstract: A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm/sup 2/ in a 2- mu m CMOS process and 500 mW at 25 MHz). >

Cable televison spread spectrum data transmission apparatus

Abstract: Apparatus for transmitting data spread across at least a portion of the bandwith of a cable television channel comprises a carrier signal oscillator (203), a frequency divider (205), a pseudorandom sequence generator (202) and two exclusive OR gates (207, 210). A first exclusive OR gate (207) serves to spread a data signal across the pseudorandom noise sequence generator (202) having a much higher chip rate than the bit rate of the data signal. The second exclusive OR gate (210) modulates the spread spectrum data signal to a carrier frequency for transmission over the cable television channel. The apparatus may be applied for return path transmission in the 0-30 megahertz band which is highly susceptible to interference noise and provides approximately a 20 dB signal to interference ratio advantage over known data coding and transmission schemes. A microprocessor (201) normally present in a cable television terminal may format data for transmission, control the spread spectrum modulation process and control gain control circuitry for introducing an appropriate power level into the cable plant.

GaAs integrated circuit programmable delay line element

Abstract: A semiconductor chip for processing or storing information and a system comprising a plurality of semiconductor chips for processing or storing information. In one form of the invention each chip includes clock input and output circuitry for receiving and transmitting signals of a first frequency and transmission circuitry for receiving and transmitting data. The transmission circuitry is capable of sampling the data at a second clock frequency which is less than the first clock frequency. Circuit components are coupled to the clock circuitry and transmission circuitry for processing the data. In another form of the invention a semiconductor chip comprising clock input and output circuitry, transmission circuitry and circuit components for processing data further includes input circuitry for selecting a variable delay between the time data is received onto the chip and transmitted from the chip In a preferred embodiment of the invention the semiconductor chip includes a memory array for storing data. The transmission circuitry includes a first path for transmitting received data to another like chip and a transmission path capable of combining data which is stored in the memory array with data which is stored in one or more like chips.

A 45-ns 16-Mbit DRAM with triple-well structure

Abstract: The authors describe a 16-Mb DRAM (dynamic RAM) fabricated with a triple-well CMOS technology that enables optimum choice of well bias. With this technology, an optimized chip architecture, and a p-channel load word-line bootstrap driver incorporating a predecoder a 45-ns row-access-strobe access time is achieved. The memory cell is in a quarter-pitched arrangement combined with an interdigitated bit-line/shared-sense-amplifier scheme. This overcomes the difficulty of defining capacitor-plate poly in a scaled-down trench or buried-stacked-capacitor cell. The output waveform of the RAM is shown. The features of the 16M DRAM are summarized. It is capable of fast page, static column, or nibble operation and -*1- or *4-bit organization, determined by the choice of bonding configuration. >

A built-in Hamming code ECC circuit for DRAMs

Abstract: An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique. >

Serial testing technique for embedded memories

Abstract: A testing circuit interfaces serially with the data path of an embedded memory circuit formed from at least one memory unit having separated data input and output lines and tandem addressing. Part of the testing circuit is a series of two-input multiplexer units which are adapted to be embedded on the same chip as the memory circuit. The outputs of the multiplexer units connect to a respective one of the data input lines of the memory circuit. Excepting the first bit position, a first input of each multiplexer unit is adapted to connect to the data output line of the adjacent bit position in the memory circuit. The second inputs of the multiplexer units are adapted to connect to the data bus of the chip. A further part of the testing circuit is a finite state machine which is adapted to connect to the first input of the multiplexer unit at the first bit position and to the data output line at the last bit position. During testing, the finite state machine actuates the multiplexer units to connect the first inputs, and for each address outputs a series of test bits, shifts those bits through the addressed word by a series of read and write operations, and examines those bits after their passage through the addressed word for defects in the memory circuit at that address. The finite state machine may or may not be embedded on the same chip as the memory circuit.

Transceiver employing direct sequence spread spectrum techniques

Abstract: A transceiver for transmitting and receiving digital data is disclosed. The transceiver employs direct sequence spread spectrum communications techniques for reducing interference among multiple users in a communications network environment. Each transceiver has a transmitter for locking a digital bit stream to a predetermined spread spectrum chip sequence and carrier signal. Frequency of the carrier signal and the chip sequence. Both the carrier signal, the chip sequence and the bit stream rate are derived from an integrally related to an accurate reference frequency to facilitate rapid acquisition and decoding of the signal by another transceiver. The transceiver also has a receiver portion for acquiring and decoding a transmitted and direct sequence spread spectrum signal to recover the digital bit stream using the spread spectrum chip sequence and carrier signal.

Multiple access code acquisition system

Abstract: Apparatus for generating a complex composite code for fast acquisition by multiple access users is provided which comprises a composite code generator having an in-phase channel code generator and a quadrature channel code generator for generating two linear composite codes. The quadrature channel composite code is modulated onto a carrier which is 90° out of phase with the in-phase carrier. The two linear composite codes are summed together and simultaneously transmitted to the receivers. Each receiver has a plurality of components code generators which generate replica component codes for fast acquisition of the composite code. A plurality of the components codes of the in-phase composite code are derived from the like components code generators in the quadrature channel to enhance speed of acquisition without acknowledgements by the receivers that any of the components codes have been acquired.

Spread spectrum system with random code retransmission

Abstract: A communication system includes a hub station and a plurality of terminal stations. An inbound satellite communication link from each of the terminal stations to the hub station sends digital data packets encoded with a CDMA code for code division multiple access during synchronized time slots on a contention channel. Each of the digital data packets is encoded with the same CDMA code during a first transmission, but each packet is encoded with an alternate CDMA code during any subsequent transmission.

Temperature sensing circuit

Abstract: In order to sense the temperature of an integrated circuit chip, a semiconductor junction device (D1) integrated on the chip is used to generate a first signal (V 1 ) having a known variation with temperature. A second signal (V 2 ) is generated by passing a PTAT current (I 2 ) through a resistor (R1) so that the second signal (V 2 ) has a known variation with temperature which is opposite in sign to that of the first signal (V 1 ). The two signals are compared (42) to generate an output signal (OT) which is dependent on whether the temperature of the chip is below or above a predetermined threshold temperature. The current (I 1 ) through the junction device (D1) is also PTAT, which provides a more accurate definition of the threshold temperature in terms of integrated circuit parameters.

IC insertion: an application of the travelling salesman problem

Abstract: Chip insertion problems arise naturally in electronic board assembly. Several examples are considered and the problem is formulated as a travelling salesman problem. Microcomputer solutions are possible using the TRAVEL package of Boyd, Pulleyblank, and Cornuejols which provides inexpensive solutions to symmetric problems with less than 300 cities.

A GaAs MESFET IC for optical multiprocessor networks

Abstract: A GaAs, enhanced/depletion mode, self-aligned, refractory-gate, MESFET chip process and circuit family have been developed for the integration of fiber-optic data link functions (e.g. photodetection, amplification, clock recovery, and deserialization) on a single chip. These authors describe the process and present results on integrating a complete optical receiver, including the photodiode and clock recovery circuits, on one chip. The chip functions use over 2000 devices, and perform at 1-GB/s, while dissipating less than 300 mW of heat. This chip is the most complex high-performance optoelectronic integrated circuit reported to date. >

Cavity-down chip carrier with pad grid array

Abstract: The invention is an improved chip carrier assembly utilizing a cavity-down chip carrier with a pad grid array wherein the IC chip within the chip carrier is mounted against a surface opposite the PWB to which the chip carrier is attached such that heat transfer from the IC chip may occur along a short path to a heat sink such that a large heat transfer rate is possible Furthermore, the apparatus utilizes an alignment and electrical connection means between the contact pads of the chip carrier and a PWB to which the chip carrier is attached to compensate for shrinkage variation which occurs during the chip carrier fabrication process Furthermore, within the cavity of the chip carrier there is space for additional components such as a decoupling capacitors This permits the design of an apparatus providing better heat transfer properties, more accurate contact pad locations and the option of including within the chip carrier components which in the past had been mounted outside of the chip carrier

Thermal analysis of integrated circuit devices and packages

Abstract: The integrated circuit device is modeled as a four-layer structure with multiple heat sources located on the surface of the first layer and with the fourth layer representing the device package. Each layer is assumed to have the same rectangular dimensions. Using the separation of variables, an analytical solution for the temperature at any location inside and on the boundaries of the structure is derived. Based upon the solution obtained, a computer program, Thermal, has been written in Fortran. Characteristics of the solution were studied, and several representative device structures were analyzed. The results of the simulation show how the device thermal resistance is affected by the die-bonding layer properties, the electrodes on the chip surface, and the heat spreader at the bottom surface of the chip. A FET power device was also analyzed to illustrate the very narrow hot zones produced on the chip surface, suggesting that the thermal measurement techniques must have adequate spatial resolution to measure the peak temperatures accurately. The lateral spread of heat flux into the regions of the package extending beyond the chip dimensions was studied using the boundary element method. An iteration technique based on the analytical solution has also been developed to account for the effect of this lateral heat spread. The corrected temperature using this iteration technique agrees to within 3.7% with that obtained using the boundary element method. >

Silicon modeling of pitch perception.

Abstract: We have designed and tested an integrated circuit that models human pitch perception. The chip receives as input a time-varying voltage corresponding to sound pressure at the ear and produces as output a map of perceived pitch. The chip is a physiological model; subcircuits on the chip correspond to known and proposed structures in the auditory system. Chip output approximates human performance in response to a variety of classical pitch-perception stimuli. The 125,000-transistor chip computes all outputs in real time by using analog continuous-time processing.

Circuit for providing isolation between components of a power control system and for communicating power and data through the isolation media

Abstract: An industrial automation system using transformers for providing electrical isolation between a system interface chip and a load interface chip while simultaneously allowing communication of power and data across the isolation barrier. Clock pulses are transmitted from the system interface chip to the load interface chip across one transformer, and the clock pulses are used by the load interface chip to create a power supply for operating the components within the chip. Data is communicated from the system interface chip to the load interface chip across a second transformer by the use of messages. Each message comprises a bit sync field, a byte sync field, and a data field. The bit sync field and byte sync field are used by the load interface chip to synchronize itself with the system interface chip. Transmission and reception of data by the chips are interleaved on a bit-by-bit basis, wherein a bit is transmitted from the load interface chip to the system interface chip after each bit is transmitted from the system interface chip to the load interface chip. After each byte of data is transmitted and received by the chips, the load interface chip eliminates synchronization between the chips, and must resynchronize itself with the system interface chip in order to transmit and receive the next byte of data.

Vertically interconnected integrated circuit chip system

Abstract: A high density IC layout is achieved by providing conductive feedthroughs through an IC chip directly to input/output locations within the circuitry, inward from the periphery of the chip or alternately at the periphery of the chip. The chip can thus be mounted to a substrate face up, allowing for visual inspection and simplified mounting techniques. To provide a high density 3-D stack, substrates with chips mounted thereon are stacked together, with substrate feedthroughs connecting to selected chip feedthrough via the substrate routing, and successive layers electrically connected by contact springs. Chips mounted on a single substrate can also be used in a 2-D configuration, without substrate feedthroughs.

An integrated free space optical bus

Abstract: As integrated circuit linewidths are reduced, single-chip system functionality and speed increase. Conventional electronic chip input/output does not follow this trend: bonding pad sizes and off chip capacitive loads remain essentially constant. Shortage of chip interconnect capability has become critical. Integrated free-space optical interconnect has the potential to overcome this problem by providing a large number of high-speed connections between chips. A description is given of the application of free-space optics, quantum-well modulators, and CMOS photodetectors to this task. >

A versatile and powerful chip for real-time motion estimation

Abstract: A VLSI architecture that achieves a single-chip real-time implementation of motion estimation is presented. The case of a block matching algorithm that computes a displacement vector for each block of a segmented image is considered. The versatile architecture of the chip allows displacement vectors to be computed for various sizes of template block and matching window, depending on the pixel rate. The chip computes minimum and maximum values of distances, and the distances can be randomly accessed from the outside. Displacements of +or-7 at video rate or +or-15 for videophone, can be computed for 16*16 blocks. >

Thermal protection method for a power device

Abstract: A thermally protected power transistor comprising a first chip which includes a power transistor and a second chip which includes protection circuitry. The second chip has a plurality of metallic bumps formed thereon which are coupled to various portions of the protection circuitry, wherein at least one metallic bump serves as a thermal couple. The protection circuitry chip is mounted upside down on the power transistor chip and coupled to the power transistor chip by the metallic bumps. The metallic bumps serve to provide electrical power for the protection circuitry, to couple control signals between the protection circuitry and the power transistor, and to couple thermal information from the power transistor to the protection circuitry.

Semiconductor integrated circuit device

Abstract: A semiconductor integrated circuit device according to the present invention comprises a chip substrate formed of a semiconductor. Formed on a surface of the chip substrate is an integrated circuit and a plurality of chip terminals which are located to the outside of the integrated circuit, so as to be connected thereto. An electrical insulating layer covers the entire surface of the chip substrate, and conductor leads equal in number to the chip terminals are formed on the insulating layer. One end of each conductor lead is connected to a corresponding chip terminal, and the other end thereof is formed having a connecting terminal whose surface area is greater than that of each chip terminal. The connecting terminals are distributed substantially over the entire surface of the insulating layer.

Very high efficiency VLSI chip-pair for full search block matching with fractional precision

Abstract: VLSI architecture design and implementation of a chip pair for the motion compensation full search block matching algorithm are described This pair of ASICs (application-specific integrated circuits) is motivated by the intensive computational demands for performing motion compensation in real time They have been developed to calculate fractional motion vectors with quarter-pel precision The VLSI architecture is based on some special data-flow designs that allow sequential inputs but perform parallel processing with 100% efficiency for integer motion vector estimation and nearly 100% for fractional motion vector estimation The chip-pair design has been laid out and simulated using a silicon compiler tool, and the chip statistics are summarized Testing circuitry is included to increase the observability of the chips >

Method of producing an article comprising a multichip assembly

Abstract: In methods of producing an article that comprises a multichip assembly, in which the (typically electronic but not excluding opto-electronic) chips are bonded to a substrate by means of spaced-apart localized solder regions (frequently referred to as "solder bumps"), it is frequently desirable to be able to remove a given chip from the substrate and to replace it with another chip. According to the invention, such chip removal is accomplished by a technique that comprises heating the solder bumps between the given chip and the substrate to a temperature below the solidus temperature of the solder in a manner such that a temperature gradient exists across the solder bumps, and applying to the given chip simultaneously a torque and a lifting force sufficient to cause separation of the given chip from the substrate. The technique can be carried out such that the solder bumps remaining on the substrate after chip removal are of substantially uniform height, facilitating attachment of the replacement chip.

Digital computer with multiprocessor arrangement

Abstract: In a digital computer with multiprocessor arrangement, each processor is a highly integrated computer chip on a semiconductor basis connected to the other processors in the arrangement, which are of same design, via a highly meshed management system composed of meshes and nodes for transmitting digital signals. Peripheral devices such as keyboards, memories, monitors, image sensors, speech analysis units, speech synthesis units as well as transmitters are connected to the computer. According to the invention, the management system is a beam waveguide network. Each node (26) is associated with a processor (11) to which it is coupled via an optical emitter (21) and an optical receiver (22). The new types of chip interconnection which result and hence the high packing density of the chips and large number of cross-connections obtained are particularly advantageous. The computer network has a high functional density and the computer and peripherals are unaffected by electromagnetic influences.

A thin electronic card having an integrated circuit chip and battery and a method of producing same

Abstract: A method for producing an electronic card by printing an electroconductive pattern and a first electrode surface of a battery on a first cover sheet, applying a battery activator onto the first electrode surface, resting an electrolyte-impregnated separator onto the first electrode surface, fixing an IC chip to the electroconductive pattern in a predetermined position, printing a second electrode surface of the battery on a second cover sheet, applying a battery activator onto the second electrode surface, and lapping and sticking the first and second cover sheets together and cutting them into a predetermined size.

Chip identification method for use with scan design systems and scan testing techniques

Abstract: A method and apparatus are provided for uniquely identifying integrated circuit chips adapted for use with scan design systems and scan testing techniques. A predetermined identification number corresponding to each LSI chip to be identified is assigned. Each predetermined identification number has a predefined format. The assigned identification number is stored in a plurality of predefined shift register latches (SRLs) in the corresponding LSI chip to be identified. Then the LSI chip is identified by selectively reading out the stored predetermined identification number.

Dynamic behavior of SMT chip capacitors during solder reflow

Abstract: A dynamic model of a SMT (surface mount technology) type 1206 chip capacitor is developed. The model is used to determine the effects of pad geometry, chip metallization and dimensions, amount of solder, and chip displacement on the ability of the chip to lift (tombstone) and to self-align itself during solder reflow. Both static and dynamic characterizations are shown. The model simulations show that the chip capacitor will begin to lift initially for some geometries, but tombstoning does not appear to be a problem. Thus, to help the self-alignment capabilities, the simulations show that system configurations with smaller pad lengths, smaller pad gaps, larger solder volume, and smaller metallization are best. These conclusions are confirmed when compared to existing recommendations based upon experimental tests. It is concluded that the model is a powerful tool that can be used to optimize these system parameters. >

Short-resistant decoupling capacitor system for semiconductor circuits

Abstract: A decoupling capacitor system for improving the reliability of digital logic circuit boards such as single inline memory modules which use surface-mount decoupling capacitors. The system comprises one or more units of two or more series-connected capacitors connected between the chip supply voltage (Vcc) input and the chip ground (Vss) connection. Given no change in the reliability of the individual capacitors, the reliability of a circuit board can typically be improved by several order of magnitude.