Showing papers on "Chip published in 1991"

Weighted round-robin cell multiplexing in a general-purpose ATM switch chip

Abstract: The authors present the architecture of a general-purpose broadband-ISDN (B-ISDN) switch chip and, in particular, its novel feature: the weighted round-robin cell (packet) multiplexing algorithm and its implementation in hardware. The flow control and buffer management strategies that allow the chip to operate at top performance under congestion are given, and the reason why this multiplexing scheme should be used under those circumstances is explained. The chip architecture and how the key choices were made are discussed. The statistical performance of the switch is analyzed. The critical parts of the chip have been laid out and simulated, thus proving the feasibility of the architecture. Chip sizes of four to ten links with link throughput of 0.5 to 1 Gb/s and with about 1000 virtual circuits per switch have been realized. The results of simulations of the chip are presented. >

Semiconductor chip assemblies, methods of making same and components for same

Abstract: Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

A zero-overhead self-timed 160-ns 54-b CMOS divider

Abstract: The authors describe the design of a custom integrated circuit for the arithmetic operation of division. The chip uses self-timing to avoid the need for high-speed clocks and directly concatenates precharged function blocks without latches. Internal stages form a ring that cycles without any external signaling. The self-timed control introduces no serial overhead, making the total chip latency equal just the combinational logic delays of the data elements. The ring's data path uses embedded completion encoding and generates the mantissa of a 54-b (floating-point IEEE double-precision) result. Fabricated in 1.2- mu m CMOS, the ring occupies 7 mm/sup 2/ and generates a quotient and done indication in 45 to 160 ns, depending on the particular data operands. >

Method and apparatus for the modulation of spread spectrum radio signals

Abstract: A spread spectrum receiver with filters matched to transmitter chip codes are implemented in digital circuits along with a digital circuit for acquisition and tracking of the arrival times of the chip codes. The digital circuit implementations are used for the noncoherent demodulation of pulse position spread spectrum modulation signals where the pulse is a carrier modulator by a chip code and for the noncoherent demodulation of multiple chip code modulation signals where each information symbol is represented by one of several chip codes modulating a carrier.

Built-in self test for integrated circuits

Abstract: A built-in, i.e., on-chip, self-test system for a VLSI logic or memory module. A deterministic data pattern generator is provided on the VLSI chip, and operates to test a chip module and provide a fail/no-fail result, along with data identifying where the fail occurred. This location data is captured and made available for subsequent utilization. The built-in test circuitry is programmable, and is provided with a looping capability to provide enhanced burn-in testing, for example.

A random access photodiode array for intelligent image capture

Abstract: A chip implementing random scan was designed, fabricated, and tested. The chip covers the basic requirements for random access and separation between the sampling and reading processes. In this way, a repeated reading of any pixel at any time can take place. The chip includes an 80*80 matrix of basic cells. Each cell consists of two stages: The first is based on a switch, whereas the second includes a buffer. The chip was fabricated in a 3- mu m CMOS process. It was found to operate functionally. However, the use of a standard process gave rise to the crosstalk phenomenon, which has yet to be overcome. >

Wireless digital communication: a view based on three lessons learned

Abstract: The implications of Shannon's information theory for personal communication network (PCN) design are outlined Examples of improvements in satellite communication, magnetic recording, and modem technologies that have increasingly approached information-theoretic limits are given The emphasis is on the application of Shannon's work to control of four types of interference: multi-user, multiple cell, multipath, and multiple media Code-division multiple access (CDMA), time-division multiple access (TDMA), and frequency-division multiple access (FDMA) techniques in personal communications are compared >

An analog neural network processor with programmable topology

Abstract: The architecture, implementation, and applications of a special-purpose neural network processor are described. The chip performs over 2000 multiplications and additions simultaneously. Its data path is particularly suitable for the convolutional topologies that are typical in classification networks, but can also be configured for fully connected or feedback topologies. Resources can be multiplexed to permit implementation of networks with several hundreds of thousands of connections on a single chip. Computations are performed with 6 b accuracy for the weights and 3 b for the neuron states. Analog processing is used internally for reduced power dissipation and higher density, but all input/output is digital to simplify system integration. The practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition. This network contains over 130000 connections and was evaluated in 1 ms. >

Lead frame-chip package with improved configuration

Abstract: An improved package for semiconductor chips, and method of forming the package are provided. The package includes a lead frame having a central chip bonding portion and first and second sets of interdigitaled fingers. The inner ends of the first set of fingers terminate at a distance from the central chip bonding portion closer than the inner ends of the fingers of the second set at fingers. A semiconductor chip, having input/output pads is bonded to the central chip bonding portion. A first set of wires directly couples respective input/output pads on the chip to the first set of fingers. A second set of wires couples respective input/output pads on the chip with the second set of fingers. Each of the wires of the second set of wires has a first segment extending from its respective input/output pad to an intermediate bonding region, and a second segment extending from the intermediate bonding region to its respective finger of the second set of fingers.

Spread spectrum communications system

Abstract: A spread spectrum communication system for direct sequence transmission of digital information having a modulation format which is particularly suitable for indoor communication within residential, office and industrial structures. The modulation format combines BPSK or MSK spreading with FM carrier modulation by data bits and a carrier frequency shift whose magnitude is related to both a chip rate and a spreading sequence length. The carrier, chip clock and data clock are all synchronous and the sequence length is an integral submultiple of the bit length. The system reduces the frequency error between the transmitter chip clock and the receiver chip clock to permit the elimination of a code phase tracking loop in the receiver to reduce the receiver complexity. The receiver has an extended dynamic range which makes possible the reception of very strong signal without an automatic gain control loop (AGC) as well as reducing the time needed for code phase acquisition. The transmission system is highly resistant to CW jamming and short distance multipath effects.

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

Abstract: The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined. >

Performance of binary and quaternary direct-sequence spread-spectrum multiple-access systems with random signature sequences

Abstract: The performance of synchronous and asynchronous, binary and quaternary (with and without offset) direct-sequence spread-spectrum multiple-access (DS/SSMA) communication systems using random signature sequences and arbitrary chip waveforms is investigated. The average probability of error at the output of the correlation receiver is evaluated using a characteristic-function approach for these systems. Numerical results are presented that illustrate performance comparisons between systems using random and deterministic signature sequences, synchronous and asynchronous systems, systems with rectangular or sinewave chip waveforms, and binary and quaternary systems with the same data rates and bandwidth. In all cases, the accuracy of the Gaussian approximation is also examined. >

CMOS low noise amplifier for microstrip readout Design and results

Abstract: A low noise preamplifier and shaper chip has been designed and built in 1.5 μm CMOS technology to be used for readout of Si microstrip detectors. The chip is optimized with respect to noise. Measurements on the performance of the prototype chip are presented. A noise performance of ENC = 160 e − + 12 e − /pF has been achieved.

Implementation of PRML in a rigid disk drive

Abstract: Describes the channel architecture, IC technology, and integration solutions used in implementing the IBM 0681 disk drive data channel. A brief description of the 0681 disk drive is given along with a block representation of the data channel. Particular focus is placed on the major channel functions: equalization, data coding and detection, gain and timing recovery, and write circuitry. Both the analog and adaptive digital equalizer sections used in the channel are described. The 0681 channel uses an IBM mixed-mode IC technology to implement all channel functions. This IC process is illustrated, along with the partial-response maximum-likelihood (PRML) chip layout. Attention is also given to the hybrid nature of the PRML channel; many channel functions are implemented using a combination of both analog and digital circuits. >

An object position and orientation IC with embedded imager

Abstract: A CMOS VLSI chip that determines the position and orientation of an object against a dark background is described. The chip operates in a continuous-time analog fashion, with a response time as short as 200 mu s and power consumption under 50 mW. A self-contained phototransistor array acquires the image directly, and the output is a set of eight currents from which the position and orientation can be found. The output can be sampled at up to 5000 frames/s, and there is a greatly reduced analog-digital (A-D) conversion requirement (per frame) for real-time interfacing with a digital system. Orientation is determined to within +or-2 degrees or better for moderately sized and sufficiently elongated objects. Chip dimensions are 7900 mu m*9200 mu m. >

Multi-frequency differentially encoded digital communication for high data rate transmission through unequalized channels

Abstract: A differentially encoded digital signal waveform is generated as a discrete time representation of a desired analog signal utilizing multi-frequency modulation techniques. The computational capability of present day, industry-standard microcomputers (57) equipped with a floating point array processor or digital signal processor chip is utilized to perform digital frequency encoding and compute both discrete Fourier transforms (31) and inverse discrete Fourier transforms (25) to provide a transmitter (51) and receiver (53) system utilizing suitably programmed microcomputers coupled by a communications channel.

Microfabricated thermal absolute-pressure sensor with on-chip digital front-end processor

Abstract: A thermal absolute pressure sensor of the heated microbridge type has been integrated with an active bias circuit and an 8-b successive approximation register analog/digital (A/D) converter. The chip, which contains about 1000 devices, is sensitive to variations in absolute gas pressure between 10 and 10/sup 4/ Pa, and it is implemented in a 4-Um NMOS technology merged with the microsensor process. The output of the chip is a robust digital signal adequate for transmission in high noise environments. >

Method and apparatus for establishing spread spectrum communications

Abstract: A method for establishing communications between a master unit (50) and a plurality of node units (51-55). Of the plurality of node units, K node units are assumed to have established communications with a master unit. A first (K+ 1) node unit of the plurality of node units desires to establish communications with the master unit. The method includes transmitting from the master unit a base-station spread spectrum signal (CSn1) having a common-signalling chip code, transmitting from the first node unit a second spread spectrum signal (CSm) with a first identification code using the common-signalling chip code, transmitting from the master unit a third spread spectrum signal (CSn2) with a master unit identification code, using the common-signalling chip code. The method further includes generating at the first node unit using the master unit identification signal (CSn2) a master unit chip code for transmitting spread spectrum signals (CNMK+1) to the master unit. Additionally, the method includes generating at the master unit using the first identification code, a first node unit chip code for transmitting spread spectrum signals (CMNk+1) to the first node unit.

Method and apparatus for the correlation of sample bits of spread spectrum radio signals

Abstract: A spread spectrum receiver correlator for a with filters matched to transmitter chip codes are implemented in digital circuits along with a digital circuit for acquisition and tracking of the arrival times of the chip codes The digital circuit implementations are used for the noncoherent demodulation of pulse position spread spectrum modulation signals where the pulse is a carrier modulator by a chip code and for the noncoherent demodulation of multiple chip code modulation signals where each information symbol is represented by one of several chip codes modulating a carrier

Multiple integrated circuit module which simplifies handling and testing

Abstract: A multi-chip module (26) used to interconnect and house a plurality of integrated circuits (10). The module (26) employs an intermediate structure referred to, herein, as a bridge chip (12). The bridge chip (12) connects the integrated circuit (10) to the module substrate (19). The integrated circuit (10) is attached to the bridge chip (12) and forms a composite structure (18) which can be burned-in and tested as an individual unit. The bridge chip (12) has interconnects to bring out the inputs and outputs of the integrated circuit (10). The composite structure (18) is mounted to the module substrate (19) such that, the integrated circuit (10) has a thermal pathway to the module substrate (19), and the bridge chip (12) connects to the module substrate (19). The module substrate (19) has interconnects to connect the plurality of composite structures (18).

Spread spectrum communications system

Abstract: A spread spectrum communications system includes: a transmitter having an input information a modulator for generating a spread spectrum signal in accordance with an input information signal together with a pseudonoise clock signal used to generate a first pseudonoise signal formed of a plurality of chips, a switch for switching on and off a locally generated carrier signal of said input information signal in accordance with the spread spectrum signal, a first means for inverting a phase of the spread spectrum signal when the value of the pseudonoise signal is equal to one, a second means for multiplying the inverted-phase spread spectrum signal by the carrier signal so as to produce a transmit signal at an output of the second means, and an output means for outputting the transmit signal from the second means so that the transmit signal is transmitted from the transmitter; and a receiver which receives the transmit signal from the transmitter, the receiver having a detector for obtaining a baseband signal from the transmit signal received at the detector, and a demodulation part for demodulating the baseband signal with a second pseudonoise signal which is generated synchronously with the transmit signal, so as to reproduce the input information signal.

A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications

Abstract: A 200-MHz universal all-digital quadrature modulator and demodulator are presented for implementing the front-end signal processing functions for high-bit-rate digital radio applications. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a band-limited IF digital output. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate matched 40-tap finite-impulse-response (FIR) square-root Nyquist filters and can accommodate symbol rates up to Mbd. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256*256 points, thus resulting in a generic chip set suitable for a wide variety of high-bit-rate digital modem designs using various advanced multilevel modulation formats such as M-ary QAM. Both chips were fabricated in a 1.2- mu m CMOS process. >

A nonlinear CMOS analog cell for VLSI signal and information processing

Abstract: A simple reconfigurable continuous-time nonlinear CMOS building block for analog VLSI applications is presented. The new block is introduced as a basic analog cell for the implementation of analog VLSI systems. It simultaneously achieves four-quadrant multiplication and division. Its applications in both analog signal and information processing are discussed. These include multiplication, signal squaring, division, signal inversion, amplitude modulation, RMS-DC conversion, and neural computing. Using the new cell, a MOS VLSI implementation of a feedback/feedforward neural network is developed which achieves the scalar product of two n-tuple vectors by 4(n+1) MOS transistors and one operational amplifier. To verify the versatility of the new cell and its applications, experimental results obtained from a test chip that was fabricated using the MOSIS 2- mu m CMOS process are included. >

A bit-stream digital-to-analog converter with 18-b resolution

Abstract: A two-channel differential 18-b bit-stream digital-to-analog converter implemented in a 2.5- mu m BiCMOS process with 7.3-mm/sup 2/ chip area is described. The circuit contains two identical 1-b D-to-A conversion channels on one single chip. Each channel consists of a digital input part, a switched-capacitor D-to-A network, and two high-performance operational amplifiers. Total harmonic distortion plus noise is better than -102 dB. The dynamic range is more than 108 dB, giving a true 18-b resolution. Output operational-amplifier distortion is below 120 dB at full-scale signal. System design considerations, implementation, and measured results of the IC are discussed. >

Correlator for spread spectrum communications systems

Abstract: An improved correlator for use in a spread spectrum communications system which operates with a predetermined chip sequence includes an N-stage correlation register, wherein each stage corresponds to a signal chip in the sequence, an a means for autocorrelating each of the N stages with the corresponding chips in the sequence. The correlator further includes a means for modifying the sequence to accomodate multiple communication channels.

Optoelectronic component arrays for optical interconnection of circuits and subsystems

Abstract: The design and performance of arrays of hybrid optoelectronic detector and modulator elements for use as optical input and output pads for chip- and board-level optical interconnects are discussed. The application of these interface arrays to specific VLSI circuits is discussed, illustrating the potential improvements in performance levels. This solder bond technique is capable of very accurate component positioning at points across the entire surface of the VLSI circuit, so that precise alignment to the optical pathways can be envisaged with optical signals taken from or delivered to any position on the chip. Measurements presented indicate that submicron positioning can be achieved. In particular, a fabrication-tolerant modulator design incorporating a chirped semiconductor mirror is reported. >

Polyopoly overlapping spread spectrum communication system and method

Abstract: Two, three or more competitive personal communications network spread spectrum systems share spectrum without interfering with each other, without significantly decreasing the chip rate of each PCN system, and without increasing the level of interference seen by fixed service users. A duopoly of spread spectrum communications system includes a first transmitter station, a second transmitter station, a first receiver station and a second receiver station. A transmitter at the second transmitter station transmits a spread spectrum signal on a carrier frequency which is offset from the carrier frequency of the first transmitter at the transmitter station by the chip rate. A tripoly of spread spectrum communication system includes the elements of the duopoly spread spectrum system and further includes a third transmitter station and a third receiver station. A third transmitter at the third transmitter station transmits a spread spectrum signal on a carrier frequency which is offset from the first carrier frequency by twice the chip rate. The first, second and third receiver stations each have receivers which receive the respect of spread spectrum signals from the first, second and third transmitter stations. A polyopoly overlapping spread spectrum communications system may be used which allows many users to transmit and receive throughout the frequency regime.

Variable chip-clocking mechanism

Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.

An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

Abstract: A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required for interconnection. The processing elements are implemented in pairs that are connected to form a ring. In this way three-quarters of the interconnections are between neighbors. The ring structure is laid out in two columns and the interconnection of nonneighbors is routed in the channel between the columns. The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2- mu m CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V/sub DD/=4.75 V and T/sub A/=70 degrees C). The core of the chip (excluding pad cells) is 7.8*5.1 mm/sup 2/ and contains approximately 50000 transistors. The interconnection network occupies 32% of the area. >

VLSI fuzzy chip and inference accelerator board systems

Abstract: The architecture and operational features of a VLSI fuzzy logic inference processor are described. Also described are the architecture and associated high-level software of two VMEbus-board systems based on the fuzzy chip. The VLSI implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. The CMOS chip consists of 688000 transistors, of which 476000 are used for RAM memory. In addition to operating in a robot, the single chip board is installed on a Sun-3 workstation for further research and software development. >