Showing papers on "Chip published in 1992"

Bandlimited quasi-synchronous CDMA: a novel satellite access technique for mobile and personal communication systems

Abstract: Recent trends in digital communications are opening commercial applications to code division multiple access (CDMA). A novel access technique based on bandlimited quasi-synchronous CDMA (BLQS-CDMA) is described, showing all the advantages of synchronizing conventional direct sequence CDMA to drastically reduce the effect of self-noise. Bandlimitation is achieved with no detection loss by means of Nyquist chip shaping, leading to a simple all-digital demodulator structure. Detection losses due to imperfect carrier frequency and chip timing synchronization are analytically derived and numerical results are checked by computer simulations. Impairments due to satellite transponder distortions are evaluated. The full digital modem structure is presented, together with possible applications to mobile and very small aperture terminal (VSAT) satellite communications. >

A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths

Abstract: A field-programmable multiprocessor integrated circuit, PADDI (programmable arithmetic devices for high-speed digital signal processing), has been designed for the rapid prototyping of high-speed data paths typical to real-time digital signal processing applications. The processor architecture addresses the key requirements of these data paths: (a) fast, concurrently operating, multiple arithmetic units, (b) conflict-free data routing, (c) moderate hardware multiplexing (of the arithmetic units), (d) minimal branch penalty between loop iterations, (e) wide instruction bandwidth, and (f) wide I/O bandwidth. The initial version contains eight processors connected via a dynamically controlled crossbar switch, and has a die size of 8.9*9.5 mm in a 1.2- mu m CMOS technology. With a maximum clock rate of 25 MHz, it can support a computation rate of 200 MIPS and can sustain a data I/O bandwidth of 400 Mbytes/s with a typical power consumption of 0.45 W. An assembler and simulator have been developed to facilitate programming and testing of the chip. >

Multiple access telephone extension systems and methods.

Abstract: A method and system for conducting multiple access simultaneous telephone communications in full duplex either over the power lines of a building or using RF transmission. It employs a combination of multiple access techniques selected from among the following: time division, code division, and frequency division. The following features result: a) security coding to prevent unauthorized access and eavesdropping, b) multiple simultaneous conversations through identical and closely coupled transmission media, c) non-interference to other communications systems and users, and d) processing gain for operating in noisy environments.

An integrated mass flow sensor with on-chip CMOS interface circuitry

Abstract: A multielement monolithic mass flow sensor which developed for possible use in automotive and industrial process control applications is reported. The chip illustrates the use of a common microstructure (a thin dielectric window/diaphragm) for the simultaneous measurement of flow velocity (rate), flow direction, gas type, and pressure. These transducers are merged with on-chip interface electronics to amplify and multiplex the transducer signals, control on-chip actuators, perform self-test, reduce the number of external leads required, and demonstrate process compatibility with a p-well CMOS process. The on-chip circuitry also implements a bandgap sensor for the measurement of ambient temperature. Thus, the chip simultaneously monitors all parameters needed for the computation of true mass flow, requires only ten external leads, and delivers high-level buffered output signals. >

Spread spectrum method

Abstract: A method for establishing and communicating synchronous, code division multiple access communications between a base station and a plurality of remote units. A plurality of remote-communications signals which have spread-spectrum modulation are transmitted from the plurality of remote units and arrive simultaneously at the base station. The method includes transmitting repetitively from the base station a access signal having spread-spectrum modulation and receiving the access signal at an accessing-remote unit. The accessing-remote unit transmits an echo signal which has spread-spectrum modulation. The echo signal is received at the base station and a time delay is measured between the access signal and the received echo signal. A protocol signal which has spread-spectrum modulation is transmitted to the accessing-remote unit, with the protocol signal communicating a chip codeword and the time delay measured at the base station. The accessing-remote unit adjusts a delay time such that the communications signal transmitted from the accessing-remote unit arrives simultaneously at the base station with communications signals transmitted from the plurality of remote units. The base station communicates to the plurality of remote units, with a plurality of base-communications signals. Each chip codeword of each base-communications signal is orthogonal to chip codewords of the plurality of base-communications signals. The plurality of remote-communications signals arrive simultaneously at the base station with each chip codeword of each remote-communications signal orthogonal to chip codewords of the plurality of remote-communications signals.

Code position modulation system and method for multiple user satellite communications

Abstract: An embodiment of the present invention is a communications system for multiple users sharing the same maximal length code (MLC) in a code position modulation multiple access environment. A 1023 chip length code is transmitted with reference to an independent coordinated time source. The code repeats every time after 1023 chips have been transmitted. The MLC will begin each time period with the first through 1023 rd chip, depending on the data to be sent and the identity of the user transmitting it. The chips belonging to the MLC that were not sent at the beginning of a time period are sent at the end to complete the MLC each time period in a wrap around fashion. Each time period can be arbitrarily divided into subsections embracing, for example, sixteen chip times. When so divided, more than sixty subsections are possible from one 1023 chip MLC. Respective users are each assigned a subsection. If the transmitted MLC begins on one of the sixteen chip time slots in a particular user's assigned subsection, the chip time slot that the MLC does begin on will be interpreted as communicating four bits of data, 0000 . . . 1111.

A VLSI neural processor for image data compression using self-organization networks

Abstract: An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared The proposed method is quite efficient and can achieve near-optimal results The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested It occupies a silicon area of 46 mm*68 mm in a 20 mu m scalable CMOS technology and provides a computing capability as high as 32 billion connections/s The experimental results for the chip and the winner-take-all circuit test structure are presented >

Application of the ANNA neural network chip to high-speed character recognition

Abstract: A neural network with 136000 connections for recognition of handwritten digits has been implemented using a mixed analog/digital neural network chip. The neural network chip is capable of processing 1000 characters/s. The recognition system has essentially the same rate (5%) as a simulation of the network with 32-b floating-point precision. >

Method and apparatus for providing time diversity

Abstract: The invention provides a method and apparatus for transmitting digital signal information to a receiver using a plurality of antennas. The invention involves applying a channel code to a digital signal producing one or more symbols. A plurality of symbol copies is made and each copy is weighted by a distinct time varying function. Each antenna transmits a signal based on one of the weighted symbol copies. Any channel code may be used with the invention, such as a convolutional channel code or block channel code. Weighting provided to symbol copies may involve application of an amplitude gain, phase shift, or both. The present invention may be used in combination with either or both conventional interleavers and constellation mappers.

Single chip IC tester architecture

Abstract: An integrated circuit (IC) test architecture and technique which can be used in conformity with the IEEE 1149.1 test standard and configured on a single chip. This chip can be remotely controlled via a PC or workstation to generate stimulus and collect response data to fully test an IC which matches the foot print of the test chip. The specified technique uses the IEEE test standard with additional logic on a single chip which permits at speed test functional test of ICs. The test chip can be connected to a PC or workstation via the four (4) channel Test Access Port. By remotely controlling the test chip from the PC or Workstation, stimulus and response data can be generated to completely test any Integrated circuit having a foot print matching the IC of the test chip. In one embodiment, the test chip is mounted on a probe card for at speed functional test of wafers. In another embodiment, the test chip is placed in a socket or adapter for at speed package level test. In another embodiment, the test chip is sandwiched between a device under test (DUT) and the PCB on which the DUT is mounted for at speed board test.

Module level electronic redundancy

Abstract: A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.

A CMOS four-channel*1K time memory LSI with 1-ns/b resolution

Abstract: A four-channel 1024-b time-to-digital converter chip, which records input signals to memory cells at 1-ns intervals, has been developed. To achieve 1-ns precision, the chip incorporates a feedback stabilized delay element. The chip was fabricated on a 5.0-mm*5.6-mm die using 0.8- mu m CMOS technology. It dissipates only 7 mW/channel under typical operating conditions. >

A High-Speed DES Implementation for Network Applications

Abstract: A high-speed data encryption chip implementing the Data Encryption Standard (DES) has been developed. The DES modes of operation supported are Electronic Code Book and Cipher Block Chaining. The chip is based on a gallium arsenide (GaAs) gate array containing 50K transistors. At a clock frequency of 250 MHz, data can be encrypted or decrypted at a rate of 1 GBit/second, making this the fastest single-chip implementation reported to date. High performance and high density have been achieved by using custom-designed circuits to implement the core of the DES algorithm. These circuits employ precharged logic, a methodology novel to the design of GaAs devices. A pipelined flow-through architecture and an efficient key exchange mechanism make this chip suitable for low-latency network controllers.

A VLSI chip set for high-speed lossless data compression

Abstract: A VLSI implementation of a lossless data compression algorithm is reported. This is the first implementation of an encoder/decoder chip set that uses the Rice (see JPL Publication 91-1, 1991) algorithm and provides an introduction to the algorithm and a description of the high-performance hardware. The algorithm is adaptive over a aide entropy range. Its performance on several 8-b test images exceeds other techniques employing differential pulse code modulation (DPCM) followed by arithmetic coding, adaptive Huffman coding, and a Lempel-Ziv-Welch (LZW) algorithm. A major feature of the algorithm is that it requires no look-up tables or external RAM. There are only 71000 transistors required to implement the encoder and decoder. Each chip was fabricated in a 1.0- mu m CMOS process and both are only 5 mm on a side. A comparison is made with other hardware realizations. Under laboratory conditions, the encoder compresses at a rate in excess of 50 Msamples/s and the decoder operates at 25 Msamples/s. The current implementation processes quantized data from 4 to 14 b/sample. >

Architecture for analog and digital image sensor arrays

Abstract: Sensor array architectures for both analog and digital sensor arrays adapted for single chip applications or abutment with other like arrays to form a composite scanning array, the architecture providing a sensor array (10) in which the array video signal processing circuits (38,40,42,44,50), clock circuits (60,70), etc. are integrated onto the same chip (19) as the sensor array (20) itself and dark reference sensors (20′) are located alongside of the image scanning sensors (20) to avoid gaps in the scan line when several sensor arrays are assembled together.

Multi-chip semiconductor package

Abstract: A Multi-chip semiconductor package having the thinnest structure. The package includes a chip set including a first bare chip and a second bare chip which are connected to each other by solder interposed therebetween and a plurality of TAB tapes each having an inner lead and an outer lead, the first bare chip and the second bare chip being provided with a plurality of solder bumps at opposite sides of surfaces thereof facing to each other, each of the inner leads being bonded between each corresponding the solder bump of the first bare chip and each corresponding the solder bump of the second bare chip, and a lead frame bonded to the outer leads of the TAB tapes. The chip set of the multi-chip semiconductor package may be connected to other chip set so that the package has four bare chips. Therefore, the thinnest multi-chip semiconductor package can be achieved and an integration of the package is improved. Also, a chip set is formed by fixing lead frames between two bare chips, to render the chip sets stably and firmly stacked and the pads of each bare chip disposed at desired position.

A two-chip 1.5-GBd serial link interface

Abstract: A silicon bipolar transmitter and receiver chip pair transfers parallel data across a 1.5-GBd serial link. A new 'conditional-invert master transition' code and phase-locked loop that provide adjustment-free clock recovery and frame synchronization are described and analyzed. The packaged parts require no external components and operate over a range of 700 to 1500 MHz using an on-chip VCO. The line code and handshake protocol have been accepted by the serial-HIPPI implementor's group for serially transmitting 800-Mb/s HIPPI data, an ANSI standard, and by SCI-FI, an IEEE standard for interconnecting cooperating computers. >

A special-purpose content addressable memory chip for real-time image processing

Abstract: An application specific integrated circuit (ASIC) using a special-purpose content addressable memory that performs parallel search and multiple update (PSMU) operation is presented. This chip, referred to as multiple update content addressable memory (MUCAM), can search 256, 8-b-wide locations in parallel for target data and update all such locations with new data within 50 ns. MUCAM has been developed for image component labeling and merging operation in a connected component analyzer. It was fabricated using 0.9- mu m CMOS technology. >

Bilithic composite for optoelectronic integration

Abstract: Optoelectronic composite consisting of two chips, the first chip 10 being made of a first material, the second one 13 being made of another material. The first chip 10, for example, comprises a multiplicity of active optoelectronic devices e.g. a laser diode 11 and a photo diode 12, all being monolithically integrated. A multiplicity of other optical devices, e.g. a waveguide 16, is monolithically integrated on the second chip 13. In addition this second chip 13 has depressions of the size of the devices 11,12 integrated on said first chip 10. These devices and the waveguide 16 of the second chip 13 are automatically aligned when flipping both chips together.

Code time division multiple access: an indoor cellular system

Abstract: A wideband communications system for indoor cellular applications is proposed that is based on an accessing scheme called code time division multiple access (CTDMA) It combines some of the most important advantages of code-division multiple access (CDMA) and time-division multiple access (TDMA): a constant-envelope transmitted signal, a perfect separation of the users in one cell and a cluster size of one Simulation results of such a system offering an information data rate of 144 kb/s, applying frequency division duplex and occupying a total bandwidth of 2*20 MHz are presented >

An encoder/decoder chip set for the MPEG video standard

Abstract: A VLSI chip set capable of real-time MPEG (Moving Picture Experts Group) video encoding/decoding has been developed. It is composed of an inter-frame prediction chip, a transform and quantization chip, and a variable length coding chip. To make the chip set more cost effective, the MPEG algorithms are first partitioned into three blocks on the basis of their characteristics. Individual chip architectures are designed with the use of programmable DSP and application specific array approaches. A hierarchical data transmission method is introduced for use among the chips and frame memories. By using three chips, an MPEG video encounter can compress a 30-frames/s image sequence of 352 pels*240 lines. A decoder can be constructed with two chips for the same sequence. >

Multichip ic design using tdm

Abstract: In a multichip integrated circuit module (4), the number of effective input/output pins (3, 5, respectively) is increased by using techniques of TDM (time division multiplexing). A first chip (1) has at least one output shift register (9). A second chip (1) has at least one input shift register (7). Interconnection wires (19) couple the output shift registers (9) and the input shift registers (7). Means (15) are provided for loading data in parallel to the output shift registers (9). Means (17) are provided for sequentially shifting data through the output shift registers (9) over the interconnections (19) and into the shift input registers (7). Embodiments of the invention are described for use in conjunction with bi-directional pins (25), tri-state output drivers (21), and asynchronous logic (18).

An analysis of CDMA with imperfect power control

Abstract: The performance of code-division multiple access (CDMA) mobile communications systems operating with imperfect power control is examined. Exact upper and lower bounds are used to analyze the performance of a CDMA system in which the power in the multiple access interference has a log-normal distribution. The multiple access capability of a system with ideal power control is compared to the multiple access capability of a system with imperfect power control. >

Apparatus for multipath DSSS communications

Abstract: Circuit for recovery of a plurality of multipath direct sequence spread spectrum signal components received over a time span, wherein the multipath signal components are components of a signal generated from digital data comprised of data bits at a data bit rate modulated by a pseudo-noise code, consisting of a sequence of chips having a chip rate greater than the data bit rate, wherein the sequence of chips is a code repetition period equal or greater than the received time span of the multipath signal components. A plurality of correlators is provided. Each correlator has a first input for coupling to the multipath signal components, a second input, and an output. A pseudo-noise code generator generates a duplicate of the pseudo-noise code. A time delayer is coupled between the second inputs of a mulitiplicity of the correlators and the pseudo-noise code generator for delaying the duplicate of the pseudo-noise code by a multiple of a time delay equal to the time of a chip duration or less. A signal combiner is coupled to the plurality of phase correcting devices.

A 180 MHz 0.8 mu m BiCMOS modular memory family of DRAM and multiport SRAM

Abstract: A family of modular memories with a built-in self-test interface designed using a synchronous self-timed architecture is described. This approach is ideally suited to modular memories embedded within synchronous systems due to its simple boundary specification, excellent speed/power performance, and ease of modelling. The basic port design is self-contained and extensible to any number of ports sharing access to a common-core cell array. The same design has been used to implement modular one-, two-, and four-part SRAMs and a one-port DRAM based on a four-transistor (4-T) cell. The latter provides a 45% core cell density improvement over the one-port SRAM. Nominal access and cycle times of 5.5 ns for 64 kb blocks have been shown for a 0.8 mu m BiCMOS process with no memory process enhancements. System operation at 100 MHz has been demonstrated on a broadband time-switch chip containing 96 kb of two-port SRAM. >

Minimum mean squared error interference suppression for direct-sequence spread-spectrum code-division multiple-access

Abstract: Demodulation of a direct-sequence spread-spectrum (DS/SS) code-division multiple-access (CDMA) signal in the presence of multiple-access interference is considered The channel output is first passed through a filter matched to the chip waveform and then sampled at the chip rate Because of the complexity and coefficient noise associated with such an adaptive filter when N is large, simpler structures with fewer adaptive components are proposed In each case the multiple samples per symbol are combined via a trapped delay line, where the taps are selected to minimize the mean square error It is shown that the complexity of both of these schemes are comparable, but that the first scheme is somewhat more effective in cancelling interference Numerical results are presented for specific examples illustrating the efficacy of the proposed methods >

Configuring a wafer-scale two-dimensional array of single-bit processors

Abstract: An overview of the ELSA (European large SIMD array) project, which uses a two-level strategy to achieve defect tolerance for wafer-scale architectures implemented in silicon, is presented. The target architecture is a 2-D array of processing elements for low-level image processing. An array is divided into subarrays called chips. At the chip level, defect tolerance is proved by an extra column of PEs (processing element) and bypassing techniques. At the wafer level, a double-rail connection network is used to construct a target array of defect-free chips that is as large and as fast as possible. Its main advantage is being independent of chip defects, as it is controlled from the I/O pads. An algorithm for constructing an optimized two-dimensional array on a wafer containing a given number of defect-free PEs and connections, a method to program the switches for the target architecture found by the algorithm, and software for programming the switches using laser cuts are discussed. >

Analog VLSI systems for image acquisition and fast early vision processing

Abstract: This article describes a project to design and build prototype analog early vision systems that are remarkably low-power, small, and fast. Three chips are described in detail. A continuous-time CMOS imager and processor chip uses a fully parallel 2-D resistive grid to find an object's position and orientation at 5000 frames/second, using only 30 milliwatts of power. A CMOS/CCD imager and processor chip does high-speed image smoothing and segmentation in a clocked, fully parallel 2-D array. And a chip that merges imperfect depth and slope data to produce an accurate depth map is under development in switched-capacitor CMOS technology.

Asynchronous sampling digital detector system for magnetic and optical recording channels

Abstract: A variable sampling-rate digital channel phase detector for reading synchronous data recordings from magnetic or optical media. All-digital implementation allows multiplexing of several parallel channels on a single monolithic chip for tape storage systems or other magnetic or optical data storage systems. The ASDD channel signal processing is entirely digital and includes A/D converter, digital filter and equalizer, digital differentiator and zero-crossing detector, peak amplitude estimator, zero-crossing qualifier and zero-crossing position (phase) estimator. The ASDD input is an analog waveform and the output includes two flags for qualified negative and positive waveform threshold-crossings and a digital signal encoding a waveform threshold-crossing position within the current sampling clock interval. The ASDD operates over a wide continuous range of channel data rates and provides accurate phase detection at relatively low sampling rates. It is suitable for monolithic CMOS implementation, which provides low power dissipation and small size.

An 85-MHz fourth-order programmable IIR digital filter chip

Abstract: The authors describe the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9- mu m CMOS technology. The coefficient and input data word lengths of the filter are 10 b each, and the output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10*10 multiply-add modules are used in this chip. The chip contains 80000 devices in an active area of 14 mm/sup 2/. It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5*10/sup 9/ multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed. >