Showing papers on "Chip published in 1993"

Orthogonal multicarrier techniques applied to direct sequence spread spectrum CDMA systems

Abstract: We design a new scheme for DS-CDMA applications. The basic principle consists in applying orthogonal multicarrier transmission to DS spread spectrum systems. Several algorithms for estimating the equalizer coefficients are investigated in order to reduce the interuser interference due to multipath propagation and cross-correlation between the code sequences. The resulting system achieves high robustness against channel impairments and outperforms the conventional single-carrier DS-CDMA system. >

Pseudorandom noise ranging receiver which compensates for multipath distortion by dynamically adjusting the time delay spacing between early and late correlators

Abstract: A receiver for pseudorandom noise (PRN) encoded signals consisting of a sampling circuit, multiple carrier and code synchronizing circuits, and multiple digital autocorrelators. The sampling circuit provides digital samples of a received composite signal to each of the several receiver channel circuits. The synchronizing circuits are preferably non-coherent, in the sense that they track any phase shifts in the received signal and adjust the frequency and phase of a locally generated carrier reference signal accordingly, even in the presence of Doppler or ionospheric distortion. The autocorrelators in each channel form a delay lock loop (DLL) which correlates the digital samples of the composite signal with locally generated PRN code values to produce a plurality of (early, late), or (punctual, early-minus-late) correlation signals. Thus, during an initial acquisition mode, the delay spacing is relatively wide, on the order of approximately one PRN code chip time. However, once PRN code synchronism has been achieved, the code delay spacing is narrowed, to a fraction of a PRN code chip time. There are several advantages to this arrangement, especially in environments wherein multipath distortion in the received composite signal is of the same order of magnitude as a PRN code chip time.

Modulated spread spectrum in RF identification systems method

Abstract: A method for RF communication between transceivers in a radio frequency identification system that improves range, decreases multipath errors and reduces the effect of outside RF source interference by employing spread spectrum techniques. By pulse amplitude modulating a spread spectrum carrier before transmission, the receiver can be designed for simple AM detection, suppressing the spread spectrum carrier and recovering the original data pulse code waveform. The data pulse code waveform has been further encrypted by a direct sequence pseudo-random pulse code. This additional conditioning prevents the original carrier frequency components from appearing in the broadcast power spectra and provides the basis for the clock and transmit carrier of the transceiver aboard an RFID tag. Other advantages include high resolution ranging, hiding transmissions from eavesdroppers, and selective addressing.

Integrated circuit package having a face-to-face IC chip arrangement

Abstract: An integrated circuit package includes a stacked integrated circuit chip arrangement (140) placed on a circuit substrate. The stacked IC chip arrangement includes a first IC chip (110) and a second IC chip (120), each having an array of terminals (116, 126) and being positioned in a face-to-face manner. An interposed substrate (130) is positioned between the first IC chip (110) and the second IC chip (120) such that circuitry disposed on the interposed substrate (130) provides electrical connection among the arrays of terminals of the first IC chip (110) and the second IC chip (120) and external circuitry.

Performance of orthogonal CDMA codes for quasi-synchronous communication systems

Abstract: In this paper, the performance of quasi-synchronous direct-sequence CDMA communication systems based on different sets of orthogonal codes is investigated. The authors search for sets of sequences that minimize the probability of bit detection error, given that there is imperfect synchronization among the signals. Orthogonal sequences based on the Sylvester-type Hadamard matrices (Walsh functions) are shown to provide a large improvement over the case where an orthogonal set is chosen at random. For these sequences closed form expressions are derived for the average bit error rate. Computer searches indicate that this set of codes has special properties with respect to minimizing the average cross-correlations between the different signals for small errors in chip synchronization. It appears that these codes are optimal. A multi-carrier signalling scheme designed to help synchronize the CDMA signals at the chip level is also discussed.

Method and apparatus for placing an integrated circuit chip in a reduced power consumption state

Abstract: A method and apparatus for a chip to monitor its own activity and enter and exit a state of reduced power consumption The present invention includes defining a predetermined state in which the chip could power down cleanly and monitoring the chip to determine when the chip is in that predetermined state The present invention also includes a method and apparatus for putting the chip in a state of reduced power consumption state when the chip is in the predetermined state The present invention also includes a method and apparatus for either turning off the clock generation circuitry or leaving it on during the power down state

Three-terminal switched mode power supply integrated circuit

Abstract: An embodiment of the present invention is a three-terminal switched mode power supply chip with a signal terminal for accepting a combination of a feedback control signal and bias supply voltage to operate the chip. A feedback extraction circuit separates the feedback signal from the power supply voltage within the chip by sensing the excess current flowing through a shunt regulator.

Integrated multichip memory module structure

Abstract: An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N×M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.

Multi-rate spread system

Abstract: Apparatus and a method for transmitting a direct sequence, spread spectrum communication system signal. A transmitter (10) that receives a variable data rate information bearing input signal from a digital data source (12) includes a forward error correction encoder (80) that provides redundancy and an interleaver (82) that rearranges the input data. The forward error correction encoder and interleaver minimize the effect of errors that arise in the propagation of the transmitted signal. The output of the interleaver is applied to the input of a Hadamard encoder (84), which converts data words from the interleaver into one of N orthogonal codes, producing a Hadamard signal that varies at a bit rate that changes as the data rate of the information bearing signal varies. A pseudorandom number code generator (16) produces a code signal comprising a pseudorandom sequence of chips supplied at a constant chip rate. The Hadamard signal is input to a direct sequence (DS) modulator that modulates the information bearing signal with the code signal, using an integer number (greater than one) of chips to modulate each bit of the Hadamard signal. As the data rate of the information bearing signal varies, the number of chips per bit of the Hadamard signal is varied so as to minimize variations in the chip rate of the DS modulated signal. The transmitter is preferably combined with a receiver (29) in a transceiver. The receiver demodulates a received signal, and correlates it with a code signal from a pseudorandom number code generator (40) corresponding to the pseudorandom number code generator in the transmitter. The receiver also includes a Hadamard decoder (94), deinterleaver (96), and forward error correction decoder (98). A frequency hopping capability is optionally provided.

Spread-spectrum code and carrier synchronization errors caused by multipath and interference

Abstract: The influence of multipath propagation and spread-spectrum interference on code and carrier synchronization is investigated. Both coherent and noncoherent delay lock loops (DLLs) are considered, with arbitrary early-late spacings up to one chip time. The coherent DLL is shown to have a major advantage; for a relatively high fading bandwidth, it has negligible tracking errors, while a noncoherent DLL always has a certain bias error. The results are particularly interesting for spread-spectrum positioning systems like Global Positioning System (GPS) and GLONASS. >

Packet network interface.

Abstract: A packet switch interface, which may be an asynchronous transfer mode (ATM) layer interface chip, may be connected to the inputs or the outputs of a packet switch. The interface chip modifies the virtual path identifier and the virtual channel identifier in packets directed to and from the switch. The interface chip also manipulates routing tags for the packets which are used for internal routing purposes in the switch. The interface chip includes a local interface through which packets may be extracted from or added to a packet stream flowing between a main input and a main output of the interface. The interface chip polices different communications channels handled in the interface chip by detecting whether traffic in those channels exceeds certain network usage parameters. The interface is also capable of gathering certain statistical information about the traffic in certain communications channels to allow evaluation of network performance. These operations are performed in hardware on a single integrated circuit chip involving a single table look up. This table look up involves addressing a content addressable memory with a predetermined portion of the header of a packet. Finding a match between the predetermined portion of the packet header and the content of the content addressable memory causes the memory to produce an address signal which acts as a pointer to a location in a random address memory containing a parameter block having data used to perform the operations of the interface.

Numerical simulation of continuous chip formation during non‐steady orthogonal cutting

Abstract: A finite element model for numerical simulation of non‐steady but continuous chip formation under orthogonal cutting conditions is described. The problem is treated as coupled thermo‐mechanical. A velocity approach has been adopted for the proposed solution. The computational algorithm takes care of dynamic contact conditions and makes use of an automatic remeshing procedure. The results of simulation yield complete history of chip initiation and growth as well as distributions of strain rate, strain, stress and temperature. The paper includes a detailed presentation of computational results for an illustrative case.

An IC chip of Chua's circuit

Abstract: Reports a working microelectronic chip implementation of Chua's circuit. This chip has been designed and fabricated by using a 2 mu m CMOS technology, with the circuit itself occupying a silicon area of 2.5mm*2.8mm. The chip needs to be powered with a single 9V battery, is autonomous, and generates chaotic signals from the three state variables of Chua's circuit. The proper operation of this chip has been confirmed by experimental reproduction of bifurcation and chaotic phenomena. This microelectronic design of Chua's circuit can be employed as a basic component in the VLSI synthesis of complex circuits making use of chaotic signals, including a class of cellular neural networks and secure communication systems. >

High density memory structure

Abstract: A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

Method and apparatus for time aligning signals for reception in a code-division multiple access communication system

Abstract: A coherent reverse channel, a per-chip spreading function, orthogonal spreading functions and a time alignment of all traffic channels are implemented such that the main signal of each channel arrives at a base-station within a fraction of a chip of one another in accordance with the invention. With this, the orthogonality among all channels is maintained, and, when demodulated, all channels except the channel of interest provides a cross-correlation of substantially zero with respect to the remaining signals.

Integrated circuit chip placement in a high density interconnect structure

Abstract: A high density interconnect (HDI) structure having a dielectric multi-layer interconnect structure on a substrate is fabricated by forming a chip well, placing a chip in the well, and connecting the chip to the interconnect structure. Additionally, temperature sensitive chips or devices may be located beneath the dielectric multi-layer interconnect structure. A spacer die may be located in the substrate while the interconnect structure is fabricated and removed after a chip well aligned with the spacer die is formed, in order to accommodate a chip thickness which is greater than the dielectric multi-layer interconnect structure thickness.

A digital chip timing recovery loop for band-limited direct-sequence spread-spectrum signals

Abstract: Migration towards a full-digital implementation of modems is currently one of the main trends in transmission systems design. The authors describe a noncoherent all-digital delay lock loop (DDLL) suited for chip timing synchronization in band-limited direct sequence spread spectrum (DS/SS) systems, and they thoroughly analyze its performance. The key features of this novel scheme are represented by its low-complexity processing section together with its good tracking capability. Analytical expressions for the DDLL S-curve and steady-state timing jitter are derived and confirmed by a time-domain computer simulation. Furthermore, the Mean Time to Lose Lock (MTLL) of the loop is evaluated and some numerical results are reported. The proposed chip timing synchronization scheme reveals also an improved tracking performance when compared to the traditional analog DLL for rectangular chip DS/SS signals. >

Coherent detection with reference-symbol based channel estimation for direct sequence CDMA uplink communications

Abstract: A new coding/modulation arrangement for up-link direct-sequence code division multiple access (DS-CDMA) communication, which employs coherent detection with reference-symbol based channel estimation, is presented. It is shown that the required E/sub b//N/sub O/ for this scheme is about 2 dB to 2.5 dB lower than non-coherent detection of Walsh coding with bit interleaving and about 1 dB to 1.3 dB lower than noncoherent detection with Walsh symbol interleaving over the entire range of practical vehicle speeds. A frequency domain analysis of this scheme is given.

Transceiver providing selectable frequencies and spreading sequences

Abstract: A transceiver for transmitting and receiving digital data is disclosed The transceiver employs direct sequence spread spectrum communications techniques for reducing interference among multiple users in a communications network environment Each transceiver has a transmitter for locking a digital bit stream to a predetermined spread spectrum chip sequence and carrier signal Frequency of the carrier signal and the chip sequence Both the carrier signal, the chip sequence and the bit stream rate are derived from an integrally related to an accurate reference frequency to facilitate rapid acquisition and decoding of the signal by another transceiver To provide for multiple communications channels on a single transmission medium, means for producing selectable carrier frequencies and/or selectable spreading sequences are included The transceiver also has a receiver portion for acquiring and decoding a transmitted and direct sequence spread spectrum signal to recover the digital bit stream using the spread spectrum chip sequence and carrier signal

A novel readout chip for silicon strip detectors with analog pipeline and digitally controlled analog signal processing

Abstract: A readout chip for silicon strip detectors with analog event pipeline has been fabricated (SACMOS 2 μm technology) and tested. The chip has been designed to operate at the HERA ep collider at a bunch crossing rate of 10.4 MHz. Each channel has a layout width of 44 μm and consists of a fast, low noise, low power preamplifier followed by a switched capacitor analog event pipeline. The preamplifier consists of a single CMOS push-pull gain cell and offers minimal power consumption. A novel feature of our chip is a self-reading architecture that allows the preamplifier to re-read its own pipeline buffers and thus permits a extensive parallel analog signal processing that is digitally controlled. The results from radiation damage tests with 60 Co are given for doses up to 240 krad.

Flip-chip encapsulation on ceramic substrates

Abstract: Flip-chip encapsulation has been shown to provide at least a 5-10/spl times/ improvement in fatigue life of C4 (controlled collapse chip connection) solder joints. IBM has developed, qualified and implemented encapsulation in production for a wide array of selected C4 footprint chips attached to ceramic substrates. In addition to providing a very substantial improvement in reliability, this technology has enabled major extensions to the flip-chip on ceramic menu by relaxing chip footprint or size constraints, accommodating larger chips and allowing smaller C4's on finer pitches. Also, new package technologies have evolved that feature thin and lightweight surface mountable designs that conform to industry outlines. IBM evaluated several encapsulant formulations and tested over 2000 encapsulated chips and 200000 individual C4's during the development and qualification phases. Test data was collected for a variety of accelerated thermal cycling (ATC) conditions and was supported by extensive finite element modeling. Chip configurations included memory and logic footprints and ranged in size to 14.7 mm chip size and 10.2 mm DNP (distance from neutral point of chip footprint). In all cases, ATC data showed a dramatic improvement in C4 life on encapsulated chips with no adverse effects in other tests. Several different encapsulant formulations, each with minor variations, were evaluated, and the encapsulant dispense and cure process was optimized for ease of manufacturing high production volumes that are required by IBM. >

Performance analysis of an all-digital BPSK direct-sequence spread-spectrum IF receiver architecture

Abstract: A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel. >

Integrated services on wireless multiple access networks

Abstract: The performance requirements of the multimedia services which are likely to be supported by future wireless systems are discussed. The effects of these requirements on the choice and the design of the radio multiple access technique are pointed out. The bandwidth management system that is needed by each of the two main access techniques, namely, time division multiple access (TDMA) and code division multiple access (CDMA), in order to efficiently multiplex these services onto the available bandwidth is discussed. >

Design of a low-light-level image sensor with on-chip sigma-delta analog-to-digital conversion

Abstract: The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.

Spread spectrum communication system and an apparatus for communication utilizing this system

Abstract: The present invention relates to a spread spectrum communication system in which a PN code p(t) is generated from a PN generator, data d(t) is multiplied by the PN code p(t) by a multiplier, and multiplied output is subjected to BPSK modulation by a BPSK modulating block. The PN code p(t) is subjected to BPSK modulation at BPSK modulating block, the result is delayed by at least 1 chip of the PN code by a delay block, combined with a modulated signal from BPSK modulating block, converted to an RF signal, and then it is transmitted from an antenna. The signal received by an antenna is amplified by RF amplifier block, converted to an intermediate frequency signal by frequency converting block, split into two, one of the split signals is directly applied to a multiplier, the other is delayed by a delay block, and then these two split signals are multiplied by a multiplier and thus data d(t) is demodulated and output.

Multiple Access Options for Multi-Media Wireless Systems

Abstract: Alternative access strategies for multi-media wireless systems are discussed. FDMA, TDMA, CDMA and random packet access schemes are considered. A number of possible strategies are presented and the major performance issues are discussed.

Compact power module with a heat spreader

Abstract: In a power module having at least one power device chip and circuits for driving and controlling the power device chip which are incorporated within one and the same package, a heat spreader which is constituted by a material having a heat dissipation property and supports the power device chip on its upper surface is inserted into an opening formed in a control substrate having an upper surface on which patterns for forming the chip driving and controlling circuits and a connection pattern for connection with the power device chip are printed, and the control substrate and the heat spreader inserted into the opening are fixedly supported on a base substrate. Thus, the power device chip and the control substrate can be disposed in plane and reduced in size.

Technique for increasing the data rate in a spread spectrum data link

Abstract: A method for increasing the bit rate of a data link is to select two additional 31-bit chip code patterns that are orthogonal to the present two chip codes, and to each other. This method will not require any more bandwidth that the present 10 MHz used. This method suggests that each of the four chip code patterns are assigned a two bit value i.e.: 00, 01, 10, 11. At present, the two correlated chip codes represent data in a pulse position method. No information is transferred by determining which of the two chip codes actually correlated. This new method suggests each of the four chip code patterns will still perform the pulse position modulation and also provide two additional bits of data. These additional two bits of data will up the data rate of the link by 100 percent. Alternatively, the data rate may be increased by coding the datasuch that a reduction in duty cycle is realized as well as an increase in the data rate. Variations of the coding scheme avoid repeating a chip code in successive windows to reduce the effects of multipath propagation.

Timing analyzer for embedded testing

Abstract: A 20 channel timing analyzer was designed in CMOS for embedded testing applications. The chip executes independent events in each of the channels at rates of 100 MHz, with a precision of 312.5 ps. The chip automatically adjusts for clock rates from 10 to 100 MHz and temperature/process variations, and can be calibrated to compensate for clock skew. >

Overview of the CHIP compiler system

Abstract: The MIPSpro compiler system consists of a set of components that enable you to create new 32-bit and 64-bit executable programs (as well as 32-bit executables) using languages such as C, C++, and Fortran. A new 32-bit mode, n32, was introduced with the IRIX 6.1 operating system. This new 32-bit mode has the following features: • full access to all features of the hardware • MIPSIII and MIPSIV instruction set architecture (ISA) • improved calling convention • 32 64-bit floating point registers • 32 64-bit general purpose registers • dwarf debugging format The new 32-bit mode (n32) provides higher performance than the old 32-bit mode available in IRIX releases prior to 6.1. When you compile –n32, the chip executes in 64-bit mode and the software restricts addresses to 32-bits. For more information about n32, refer to the MIPSpro N32 ABI Handbook. In addition, the MIPSpro compiler system: • uses Executable and Linking Format (ELF) for object files. ELF is the format specified by System V Release 4 Applications Binary Interface (SVR4 ABI). Refer to " Executable and Linking Format " for additional information. • uses shared libraries, called Dynamic Shared Objects (DSOs). DSOs are loaded at run time instead of at link time, by the run-time linker, rld. The code for DSOs is not included in executable files; thus, executables built with DSOs are smaller than those built with non-shared libraries, and multiple programs can use the same DSO at the same time. For more information, see Chapter 3, " Using Dynamic Shared Objects. "