Showing papers on "Chip published in 1994"

Multicarrier orthogonal CDMA signals for quasi-synchronous communication systems

Abstract: Proposes a multicarrier orthogonal CDMA signaling scheme for a multiple-access communication system, such as the reverse channel of a cellular network, as an alternative to the multi-user interference cancellation approach. The average variance of cross-correlations between sequences is used as a measure for sequence design. The authors search for sets of sequences that minimize the probability of symbol detection error, given that there is imperfect synchronization among the signals, that is, the signals are quasi-synchronous. Orthogonal sequences based on the Sylvester-type Hadamard matrices (Walsh functions) are shown to provide a significant improvement over the case where a Hadamard (orthogonal) matrix is chosen at random. Computer searches suggest that this set of codes is optimal with respect to the above measure. The issue of chip pulse shaping is investigated. Optimal pulses designed to minimize multiple-access interference in quasi-synchronous systems are obtained for various bandwidths and are shown to provide a large improvement over the raised cosine pulses. A multicarrier signaling scheme is introduced in order to reduce chip level synchronization offsets between the users. >

A surface micromachined silicon accelerometer with on-chip detection circuitry

Abstract: A monolithically integrated acceleration sensor is presented, which contains the complete detection circuitry on the same chip. It is fabricated by means of polysilicon surface micromachining. This design represents the first fully integrated accelerometer that completely meets the requirements of the automotive industry. The sensor structure itself consists of a differential capacitor, whose interdigitated fingers translate parallel to the chip surface. The detection circuitry works at high frequency with a 1 MHz carrier. The output signal of the accelerometer is fed back to the sensor element, so that an overall electromechanical closed loop is built. This allows the sensor to work in a forced-balance mode, reducing the sensor deflection and thus noise and distortion. Additionally, an electrostatic activated self-test function of the sensor element is implemented. The overall sensitivity is 20 mV g−1 with an acceleration range of ±50g. Fundamentals of the fabrication process of the sensor element and basic theoretical considerations are presented. Measurement results of the complete 'sensor and circuit' system are given.

CDMA/TDMA spread-spectrum communications system and method

Abstract: A spread-spectrum transmitter and receiver using code division multiple access with time division multiple access technology for spread-spectrum communications. At a base station, a spread-spectrum transmitter includes a multiplexer for time multiplexing a synchronization-code signal and a plurality of data signals, which may be encoded as a plurality-encoded data signals, to generate a time-multiplexed signal. A chip code generator generates a chip-code signal which is modulo added with the time-multiplexed signal by an EXCLUSIVE-OR gate to generate a spread-spectrum-time-multiplexed signal. A transmitter transmits the spread-spectrum-time-multiplexed signal over a communications channel. A spread-spectrum receiver at the base station processes a plurality of spread-spectrum signals, received from a plurality of remote units in as time division sequence of spread-spectrum signals, using a despreader circuit to generate a time-division signal. A demultiplexer demultiplexes the time-division signal as a plurality of data signals or as a plurality of privacy-encoded data signals. A remote unit, which may be a handset, includes a despreader circuit for despreading the spread-spectrum-time-multiplexed signal as a time-multiplexed signal. A synchronization-code matched filter detects the synchronization-code signal embedded in the time-multiplexed signal and thereby generates a timing signal. A controller uses the timing signal to generate a control signal. The control signal controls a transmit-receive switch for switching an antenna between the despreader circuit to the transmitter at the remote unit.

Paddleless molded plastic semiconductor chip package

Abstract: Disclosed is a semiconductor package and method in which a semiconductor chip is mounted within the opening of a lead frame by bonding wires extending between the active front side of the chip and bonding pads of the lead frame, and the lead frame/chip assembly is encased. within a plastic molded body, with the inactive back side of the chip exposed and facing outside the package.

Multi-chip integrated circuit module

Abstract: A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for receiving an integrated circuit chip die (56). A lower core laminate layer (16) having a conductive layer (18) and conductive layer (20) disposed on opposite sides thereof is laminated to the lower surface of the layer (10). Plated-through holes (36), (38) and (40) are formed through the two layers (10) and (16) to connect the conductive layer (20) with a conductive layer (12) on the upper surface of the layer (10). A high-density interconnect layer includes two laminate layers (126) and (138), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer (126) allow for connections from the die (56) to the conductive layer (12). The via interconnect structures formed in the layer (138) allow interconnection from the upper surface of layer (138) to via interconnects formed in the layer (126). An I/O connector is interfaced with select ones of the plated-through holes with pins (162) and (164). This allows an interface from the module to an operating system through pins (166).

Stack of IC chips in lieu of single IC chip

Abstract: An electronic package is disclosed in which a plurality of stacked "same function" IC chips are designed to be used in lieu of a single IC chip, and to fit into a host computer system, in such a way that the system is "unaware" that substitution has been made Memory packages are of primary interest, but other packages are also feasible, such as packages of FPGA chips In order to "translate" signals between the host system and the stacked IC chips, it is necessary to include suitable interface circuitry between the host system and the stacked chips Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory The interface circuitry can be provided by a single special purpose IC chip included in the stack, referred to as a VIC chip, which chip provides both buffering and decoding circuitry Additionally, the VIC chip should provide power supply buffering And, if it has sufficient real estate, such performance enhancing functions as error correction, memory cache, and synchronized memory may be included in the VIC chip circuitry

VIKING, a CMOS low noise monolithic 128 channel frontend for Si-strip detector readout

Abstract: A low noise Si-strip detector readout chip has been designed and built in 1.5 μm CMOS technology. The chip is optimized w.r.t. noise. Measurements with this chip connected to several silicon strip detectors are presented. A noise performance of ENC = 135 e− + 12 e−/pF and signal to noise ratios between 40–80, depending on the detector, for minimum ionizing particles traversing 280 300 μ m silicon has been achieved.

A CMOS area image sensor with pixel-level A/D conversion

Abstract: Charge-coupled devices (CCD) are at present the most widely used technology for implementing area image sensors. However, they suffer from low yields, consume too much power, and are plagued with SNR limitations due to the shifting and detection of analog charge packets, and the fact that data is communicated off chip in analog form. This paper describes an area image sensor that can potentially circumvent the limitations of CCDs and their alternatives. It uses a standard CMOS process and can therefore be manufactured with high yield. Digital circuitry for control and signal processing can be integrated with the sensor. Moreover, CMOS technology advances such as scaling and extra layers of metal can be used to improve pixel density and sensor performance. The analog image data is immediately converted to digital at each pixel using a one-bit sigma-delta modulator. The use of sigma-delta modulation allows the data-conversion circuitry to be simple and insensitive to process variations. A global shutter provides variable light input attenuation to achieve wide dynamic range. Data is communicated off chip in a digital form, eliminating the SNR degradation of analog data communication. To demonstrate the viability of the approach, an area image sensor chip is fabricated in a 1.2 /spl mu/m CMOS technology. The device consists of an array of 64x64 pixel blocks, a clock driver, a 6:64 row address decoder, 64 latched sense amplifiers, and 16 4:1 column multiplexers. The chip also contains data compression circuitry. >

Low power architecture design and compilation techniques for high-performance processors

Abstract: Reducing switching activity would significantly reduce power consumption of a processor chip. The authors present two novel techniques, Gray code addressing and Cold scheduling, for reducing switching activity on high performance processors. They use Gray code which has only one-bit different in consecutive number for addressing. Due to locality of program execution, Gray code addressing can significantly reduce the number of bit switches. Experimental results show that for typical programs running on a RISC microprocessor, using Gray code addressing reduce the switching activity at the address lines by 30/spl sim/50% compared to using normal binary code addressing. Cold scheduling is a software method which schedules instructions in a way that switching activity is minimized. The authors carried out experiments with cold scheduling on the VLSI-BAM. Preliminary results show that switching activity in the control path is reduced by 20-30%. >

System with chip to chip communication

Abstract: A system for wireless communication between a plurality of semiconductor chips is disclosed Each data line in the present invention is coupled with a transmitter for transmitting information to any other semiconductor chip Furthermore, each data line is coupled with a receiver for receiving information transmitted by any transmitter The system also comprises multiple antennas, fabricated from the chip's metalization layer Nonetheless, separate antennas within the chip packaging can also be used The antenna unit comprises a dipole and a loop antenna in a planar arrangement, thereby forming a spherical electromagnetic pattern of coverage and making the orientation between semiconductor chips for transmission purposes substantially irrelevant Each transmitter in the system comprises a modulator for modulating the information being transmitted, while each receiver comprises a demodulator for demodulating the information transmitted Several modulation schemes can be employed, though amplitude modulation is preferred, whereby each transmitter has a distinct carrier frequency within the operative radio frequency spectra--preferably above 900 MHz Each transmitter and receiver is coupled to a power source comprising a capacitor, as a signal generator, and a rectifying circuit To ensure that the communication between chips is noise/interference free, the entire system is shielded with a metal housing

System and method for orthogonal spread spectrum sequence generation in variable data rate systems

Abstract: A method and system for allocating a set of orthogonal PN code sequences of variable length among user channels operative at different data rates in a spread spectrum communication system is disclosed herein. PN code sequences are constructed that provide orthogonality between users so that mutual interference will be reduced, thereby allowing higher capacity and better link performance. In an exemplary embodiment, signals are communicated between a cell-site and mobile units using direct sequence spread spectrum communication signals. Information signals communicated on the cell-to-mobile link channels are encoded, interleaved, and modulated with orthogonal covering of each information symbol. Orthogonal Walsh function codes of varying length are employed to modulate the information signals. Code assignments are made on the basis of channel data rates in a manner which results in improved utilization of the available frequency spectrum. A substantially similar modulation scheme may be employed on the mobile-to-cell link.

Flash eprom integrated circuit architecture

Abstract: Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell (75-1, 75-n, 76-1, 76-n) is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and two N columns of flash EPROM cells. M word lines (WL1-WLN), each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines (83, 84) are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array.

Controlled equalization of multi-carrier CDMA in an indoor Rician fading channel

Abstract: In this paper, a novel digital modulation technique called Multi-Carrier Code Division Multiple Access (MC-CDMA) is analyzed. With MC-CDMA, each data symbol is transmitted at multiple subcarriers with each subcarrier modulated by "1" or "-1" based on a spreading code. Analytical results are presented on the performance of this modulation/multiple access scheme in the downlink of an indoor wireless Rician fading channel. The performance of a controlled equalization technique that attempts to restore the orthogonality between users is evaluated. >

An integrated 16-channel CMOS time to digital converter

Abstract: An integrated 16-channel Time to Digital Converter (TDC) for use in the NA48 experiment at CERN has been developed in a 1 /spl mu/m CMOS technology. The resolution is 156ns and the total time history is 204.8 ms. Buffering of up to 128 hits is done in on-chip FIFOs. The chip area is 25 mm/sup 2/. The vernier circuit consists of a 16-tap voltage-controlled delay chain controlled by a Delay Locked Loop (DLL). Read out is possible at 40 MHz. JTAG/IEEE 1149.1 protocol has been incorporated to allow in-site testing of the chip. The JTAG data path is also used to access internal control and status registers. >

Integrated memory cube, structure and fabrication.

Abstract: An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N × M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

Spread spectrum microwave overlay with notch filter

Abstract: A spread spectrum CDMA communications system for communicating data and/or digitized voice between a plurality of users to a plurality of PCN units. The spread spectrum communications system is located within a same geographical region as occupied by an existing microwave system. The spread spectrum can operate without causing undue interference to the microwave system and the microwave system can operate without causing significant interference, less than 1% total users affected, to the PCN system. The spread spectrum CDMA communications system includes a plurality of PCN-base stations and a plurality of PCN units. A PCN-base station has a device for converting the format of the data into a form suitable for communicating over radio waves, a spread spectrum modulator for spread spectrum processing the data, a notch filter, and a transmitter for transmitting the spread spectrum processed converted data from the PCN-base station to a PCN unit. The PCN-base station also has an antenna, and spread spectrum detectors for recovering data communicated from the PCN units. A PCN unit has an antenna, and a detector coupled to the antenna for recovering data communicated from the PCN-base station. The detector includes a spread spectrum demodulator. Also, the PCN unit has a device for converting the format of the data into a form suitable for communicating over radio waves, a spread spectrum modulator, an adjustable notch filter and a transmitter.

Method of forming interface between die and chip carrier

Abstract: A method for creating an interface between a chip (10) and chip carrier (26) includes spacing the chip (10) a given distance above the chip carrier (26), and then introducing a liquid (50) in the gap (34) between the chip (10) and carrier (26). Preferably, the liquid (50) is an elastomer which is hardened into a resilient layer after its introduction into the gap (34). In another preferred embodiment, the terminals (331-34) on a chip carrier (326) are planarized or otherwise vertically positioned by deforming the terminals (331-34) into set vertical locations with a plate (380), and then hardening a liquid (350) between the chip carrier (326) and chip (310).

Semiconductor chip assemblies and components with pressure contact

Abstract: A semiconduct chip assembly includes a chip, terminals permanently electrically connected to the chip by flexible leads and a resilient element or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate having contact pads so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Because engagement of this assembly with the substrate does not involve soldering or other complex bonding processes, it is reliable. The assembly can be extremely compact and may occupy an area only slightly larger than the area of the chip itself.

A communication method for an adaptive direct sequence cdma communication system

Abstract: A communication method in an adaptive CDMA communication system (100) capable of communicating a direct sequence spread spectrum communication signals which comprise bit sequences coded with spreading chip sequences. The method includes the steps of transmitting a DS-SS communication signal (30) having a training bit sequence (31) coded with spreading chip sequence. The method includes the step of despreading the DS-SS communication signal based on the training bit sequence (31) during a training interval. The DS-SS communication signals is despread by adaptively determining a despreading chip sequence. Then, following the training interval determining chip timing offset during a chip timing interval. Finally, bit timing offset is determined during a bit timing interval following the chip timing interval.

Semiconductor device having a plurality of chips having identical circuit arrangement sealed in package

Abstract: A semiconductor device includes a first chip having a circuit arrangement, and a plurality of first terminals formed on a main surface of the first chip and substantially arranged into a line. The semiconductor device also includes a second chip having a circuit arrangement identical to that of the first chip, and a plurality of second terminals formed on a main surface of the second chip and substantially arranged into a line. The first and second chips are arranged in a predetermined direction perpendicular to the main surfaces of the first and second chips. The semiconductor device also includes a plurality of connecting members connected to the first terminals and the second terminals and provided for external connections.

Automated optical inspection apparatus

Abstract: This invention provides a method and apparatus for automatically locating the bond of a wire to a lead frame and semiconductor chip or similar device as an in-process operation to facilitate in-process inspection. The apparatus includes a wire bonding machine, or similar apparatus, having a movable platform such as an X-Y table for holding semiconductor chips situated in lead frames; a video camera or other optical sensing or imaging device for generating images, which camera is typically positioned over the target chip and lead frame to be bonded; illumination means for illuminating the chip in a lead frame; an image processor capable of summing said absolute difference values, whereby each sum is stored as a difference metric, and digitizing and analyzing the optically sensed images; a bonding mechanism; and a host controller connected to the bonding mechanism, the movable platform, the camera and the image processor. The apparatus generates and stores a pre-bond digital image of the semiconductor chip in the lead frame before bonding has occurred; connects one or more wires between the chip and lead frame by any of a number of means such as ultrasonic bonding, heat bonding, conductive glue bonding or other means; generates and stores a post-bond digital image of the now-bonded chip in its lead frame; registers the pre-bond and post-bond stored digital images using nearest neighbor interpolation so that analysis can be done; and permits inspection of the results of the wire bonds according to appropriate criteria.

Up-link access apparatus in direct sequence code division multiple access system

Abstract: Disclosed is a link access apparatus of a CDMA system using a DS/SS communication method, and more particularly an up-link access apparatus which overcomes a near/far problem occurring when mobile stations and a base station perform multiple access communication using code division. An up-link access apparatus in a DS/SS-CDMA system has a transmitter for mixing data to be transmitted to a base station with a PN code unique to that mobile station to thereby PN code modulate the data. The transmitter then mixes the PN code modulated data with a carrier having a frequency that is shifted by an identification frequency to thereby output a spread spectrum signal. The apparatus further includes a receiver for mixing a demodulation carrier made up of the PN code and the identification frequency with the spread spectrum signal from the transmitter to thereby output a mixed signal. The mixed signal is then integrated according to a period having a reciprocal corresponding to the identification frequency, demodulated and output as a digital signal.

Method and apparatus for testing of integrated circuit chips

Abstract: A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.

A CNN universal chip in CMOS technology

Abstract: This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of an array of 32/spl times/32 completely programmable CNN cells. Input image can be loaded in optical or electrical form. Accuracy is in the range of 7-8 bit and cell density is of 33 cells/mm/sup 2/. >

Semiconductor laser device

Abstract: PURPOSE:To make a semiconductor laser device advantageous on thinning and a manufacturing cost side in consideration of electrical structure and a heat-dissipating effect while improving the efficiency of manufacture CONSTITUTION:A recessed section 9, in which a semiconductor laser chip 1 and a photo-detector 2 are arranged, is formed into a package 8, and a clearance between an outgoing port at the rear of the semiconductor laser chip 1 and the photo-detector 2 in the recessed section 9 is buried with a transparent material 4 while the specified section of the sidewall of the recessed section 9 is removed Projecting pieces 10a, 10b for installation are projected from the side surface of the package 8 while a pedestal 11, on which a substrate 3, on which the semiconductor laser chip 1 is mounted, is set up, is formed as the projecting pieces 10a, 10b and lead terminals 7 for grounding are connected integrally

Method for forming chip carrier with a single protective encapsulant

Abstract: The present invention relates generally to a new apparatus and method for a chip carrier. More particularly, the invention encompasses an apparatus and a method that uses a chip carrier having a single encapsulant to provide both flip chip fatigue life enhancement and environmental protection. A double-sided, pressure-sensitive, thermally-conductive adhesive tape could also be used with the encapsulated chip to directly attach the chip to a heat sink. Similarly, also disclosed is a method and apparatus for directly joining a heat sink to the chip carrier.

Single-chip self-configurable parallel processor

Abstract: A self-contained, self-configurable cascadable pipelined processor chip (160) is diclosed. The chip contains a computation section (FIGS. 1a-1d) which consists of various types of computation circuits (20-42) that can be software-interconnected in any desired configuration by a set of multiplexers (44-52) whose settings are under the control of a control section (FIG. 2 ). The control section consists of various types of control circuits (60-76) which are also software-interconnectable in any desired configuration under program control. The chip (160) is configured by a very long instruction word and then executes the algorithm defined by that configuration iteratively until stopped. The chip (160) can be programmed to reconfigure itself in response to computation results or other selectable parameters, either in accordance with internally stored configurations or in accordance with configuration information stored in an external random access memory (56, 58). Internal reconfiguration requires no separate reconfiguration time at all, and external reconfiguration can be accomplished in less than 10 μs.

Integrated multichip memory module, structure and fabrication

Abstract: An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N×M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.

A structured testability approach for multi-chip modules based on BIST and boundary-scan

Abstract: Products motivated by performance-driven and/or density-driven goals have started to use multi-chip module (MCM) technology, even though this technology still has several challenging problems, that need to be resolved before it becomes a widely adopted solution. Among the most challenging problems are achieving acceptable MCM assembly yields and meeting product quality requirements. Both of these problems can be significantly reduced by adopting adequate testing. Approaches which guarantee the quality of incoming bare (unpackaged) dies prior to module assembly, ensure the structural integrity and performance of the assembled MCMs, and help isolating defective parts prior to the repair process. This paper presents a structured testability approach that helps resolve the above problems. The approach can be adopted during MCM design and utilized during the manufacturing process. It is based on adopting Built-In-Self-Test (BIST) and boundary-scan and is in general independent of silicon, substrate or attachment technologies, hence it can be considered a generic solution. >

Ds/cdma receiver using moving-averaged pilot signals for weighting and phase rotation of orthogonal data symbol vectors

Abstract: In a direct sequence spread spectrum receiver, spread orthogonal data signals and spread orthogonal pilot signals are correlated with orthogonal despreading sequences at a chip rate. These despread signals are integrated at a symbol rate to produce orthogonal data symbols and orthogonal pilot symbols. A predetermined number of pilot symbols of each phase component are moving-averaged. Each phase component of the orthogonal data symbols is weighted with the moving average value of the corresponding phase component of the pilot symbols, and summed with the other weighted component of the data symbols to produce an output signal of the spread spectrum receiver.