Showing papers on "Chip published in 1995"

Spread spectrum access methods for wireless communications

Abstract: The authors present an overview of the characteristics of code division multiple access (CDMA) as it is currently being envisioned for use in wireless communications. There are many considerations in the design of such systems, and there are multiple designs being discussed. CDMA has been proposed for both terrestrial links and satellite links. However, there are key differences in the characteristics of the two types of links relative to the way they affect a CDMA system. The authors show how the ideas presented affect both terrestrial and satellite-based systems. >

An experimental chip to evaluate test techniques experiment results

Abstract: This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for CrossCheck, Very-Low-Voltage, IDDQ and delay tests are also given.

Chip connection structure having diret through-hole connections through adhesive film and wiring substrate

Abstract: A structure for connecting an integrated circuit chip to a wiring substrate which implements high-density packaging, high-density connection, high-speed signal transmission, and low cost. An integrated circuit is connected to a wiring substrate by means of flip-chip die bonding using an adhesive film. A direct through-hole connection is formed directly below a connecting pad so as to pass through the adhesive film and the wiring substrate. This direct through-hole connection directly connects the connecting pad to the wire. As a result of reduced area and thickness of the chip, the chip is mounted in high density, and high-density inputs and outputs are implemented by means of minute two-dimensional connections. Short wire connections directly connected to the chip permit high speed signal transmission, and high reliability is ensured by the dispersion of stress. Low-cost packaging can be effected by simple processes and facilities.

Time division multiple access methods for wireless personal communications

Abstract: Time division multiple access (TDMA) is a classic approach to multiple access in digital cellular wireless communications systems. The authors summarize a number of frequency and time slot allocation techniques for enhancing the capacity and flexibility of TDMA-based systems. They also describe how the problems of fading, delay spread, time variability and interference affect TDMA systems, and how they may he countered and even exploited by appropriate techniques of detection, diversity, coding, adaptive equalization and slow frequency hopping (FH). It is worth emphasizing that the use of one of these techniques, slow random FH, results in a system that is in effect a hybrid of TDMA and code division multiple access (CDMA). >

Apparatus for packaging a chip

Abstract: A body 300 having a cavity 310 for mounting a chip 120 fabricated with probe sequences at known locations according to the methods disclosed in U.S. Pat. No. 5,143,854 and PCT WO 92/10092 or others, is provided. The cavity includes inlets 350 and 360 for introducing selected fluids into the cavity to contact the probes. Accordingly, a commercially feasible device for use in high throughput assay systems is provided.

High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

A fast single-chip implementation of 8192 complex point FFT

Abstract: Large-scale single-frequency networks are now being considered in Europe as very promising network topologies to achieve drastic savings in spectrum usage for digital terrestrial television transmission. Such networks are possible using the COFDM system, with large guard intervals (more than 200 /spl mu/s) to absorb long echoes. In order to limit the spectral efficiency loss to about 20%, very long size fast Fourier transforms (up to 8 K complex points) have to be performed in real time for the demodulation of every COFDM symbol (every 1 ms). This paper presents the first VLSI single chip dedicated to the computation of direct or inverse fast Fourier transforms of up to 8192 complex points. Due to its pipelined architecture, it can perform an 8 K FFT every 400 /spl mu/s and a 1 K FFT every 50 /spl mu/s. All the storage is onchip, so that no external memories are required. A new internal result scaling technique, called convergent block floating point, has been introduced in order to minimize the required storage for a given quantization noise, The chip, 1 cm/sup 2/ large with 1.5 million transistors, has been designed in a 3.3 V-0.5 /spl mu/m triple-level metal CMOS process and is fully functional. The 8 K complex FFT function could therefore be introduced in the coming years in digital terrestrial TV receivers at low cost. >

Method and apparatus for performing search acquisition in a CDMA communications system

Abstract: A novel an improved method of acquisition in a spread spectrum communication system is presented. In the present invention, a large window of PN chip offset hypotheses are searched and if an energy signal is found that might indicate the presence of the pilot signal having one of the chip offsets of the large search window, then a search of a subset of offset hypotheses, or small window, is searched.

High speed crystallography detector

Abstract: A device for the collection, digitization and analysis of synchrotron x-ray crystallographic data using an area detector which detects x-ray photons directly on arrays of solid state detectors and stores the information on capacitors located on readout unit cell array chips. The device consists of a two dimensional area detector, for amplification, collection and conversion of the diffracted x-rays to electrical signals, drive electronics for providing the timing pulses and biases to the area sensor, output electronics for converting the x-ray signals to digital signals and storing the signals, and a data processor to analyze the digital signal form the output electronics. The solid-state detector array is made up of a variable-area three-dimensional array of detector array chips where each chip is in turn made up of an array of solid-state detectors. Each detector on the detector array chip is electrically connected to a readout unit cell on a readout array chip directly beneath the detector array chip. The readout unit cell contains the circuitry for storage, switching and readout of the x-ray signals.

Modulator-based photonic chip-to-chip interconnections for dense three-dimensional multichip module integration

Abstract: Computation-intensive applications such as sensor signal processing, sensor fusion, image processing, feature identification, pattern recognition, and early vision place stringent requirements on the computational capacity, size, weight, and power dissipation of modular computational systems intended for both embedded and high performance computer environments. Such ultra high speed, ultra high density computational modules will typically be configured with multiple processor, memory, dedicated sensor, and digital signal processing chips in close-packed multichip modules. The present invention relates to a novel architecture and associated apparatus for the development of highly multiplexed photonic interconnections between pairs of such electronic chips incorporated in vertical stacks within three-dimensional multichip module configurations. Vertical signal transmission through the chip substrates is accomplished by using a planar-waveguide-based optical power bus to provide a parallel array of beams to read out a modulator array that is flip-chip bonded to each silicon substrate. Local and quasi-local connectivity in the vertical dimension is accomplished by using diffractive optical structures that provide for both point-to-point interconnections and weighted fan-out within a local neighborhood. Global connectivity is incorporated by means of computer-generated volume holographic optical elements that are fabricated as a multilayer diffractive optical element. Several different architectural implementations of such computational modules are provided to address applications that include high-bandwidth two-dimensional displays, multilayer neural networks, image processors, multiple processors with access to shared memory, and rending engines for computer animation and graphics. In addition, subsystems of the computational-module architecture and apparatus are described that provide for compact optical readout of modulator-based flat panel displays.

Single chip frame buffer and graphics accelerator

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

A 2.7 V to 4.5 V single-chip GSM transceiver RF integrated circuit

Abstract: This paper describes the design and implementation of a single-chip GSM (Global System for Mobile communications) transceiver RF integrated circuit. The chip includes the RF-to-baseband and baseband-to-RF (receive and transmit) functions, two fixed frequency PLL's, and a programmable frequency agile UHF synthesizer. It is implemented In a 1.5 /spl mu/m silicon bipolar process with 12 GHz NPN's and 110 MHz lateral PNP's. The receive path uses a single-IF solution including the RF mixer, quadrature demodulator, and variable gain IF amplifier on chip. The transmit path uses a direct-up architecture with an offset mixer and an output buffer capable of driving 0 dBm into 50 /spl Omega/. The frequency agile UHF synthesizer switches between receive and transmit modes and settles to within /spl plusmn/50 Hz (0.1 ppm) in less than 500 /spl mu/s. The UHF synthesizer includes all the synthesizer logic and the oscillator on chip. The only external components are the loop filter and tank circuit. This paper first explains the chip architecture decisions and block level descriptions. The transistor level circuit designs and layout are then discussed. Finally, the performance of the circuit performance versus the requirements is presented.

A communication scheme for analog VLSI perceptive systems

Abstract: A communication architecture tailored for analog VLSI perceptive systems is proposed. Information is generated on a transmitter array of cells each driving a pulse generator. The resulting pulse-frequency modulated signals are transmitted through the nonarbitered, asynchronous access of pulses to a common bus. Pulses are decoded and accumulated in a receiver chip and the mapping of the activity distribution of the transmitter onto the receiver is achieved. One possible implementation of these principles is presented. The circuit description of all blocks is given and experimental results are shown: they satisfactorily support the theoretical basis upon which the system was constructed. Extensions to the communication architecture are finally presented. >

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

Abstract: This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT's connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >

Direct chip attach circuit card

Abstract: A structure and a method is disclosed for making a laminated circuit carrier card for the purpose of making a Direct Chip Attached Module (DCAM) with low cost and high reliability. The carrier is made using an organic or an inorganic laminated carrier having at least one surface available for direct chip mount. The chip has at least one solder ball with a cap of low melting point metal. The surface of the carrier has electrical features that are directly connected to the low melting point metal on the solder ball of the chip to form the eutectic and this way the chip is directly attached to the carrier.

High density electrical interconnect apparatus and method

Abstract: The present invention relates generally to a new apparatus and method for use in chip, module, card, etc., burn-in and/or test or electrical interconnection. More particularly, the invention encompasses an apparatus that is used as a temporary media between a chip, module, card, etc., that needs to be tested and/or burned-in and a test or burn-in system. A method for such burn-in and/or test or electrical interconnection is also disclosed. The invention also encompasses an apparatus and a method that can be used as a permanent media between two electrical devices, such as, for example, between a chip and a module or a card, etc., that is to be contained in and part of a system.

A spread spectrum code pulse position modulated receiver having delay spread compensation

Abstract: A spread spectrum code pulse position modulated communication system is disclosed. The communication system includes a spread spectrum code pulse position modulated receiver that compensates for the delay spread of a transmission medium, such as a wireless radio channel of a local area network. Delay spread may cause signal components of one transmitted spread spectrum codeword to spill over into chip positions of adjacent symbols, causing intersymbol interference, or into chip positions on quadrature channels of a given symbol interval, such as in a QPSK implementation, causing interchip interference. The disclosed receiver decodes a transmitted spread spectrum code pulse position modulated signal in the presence of such delay spread, utilizing a tentative symbol estimator to sample the matched filter data. The tentative symbol estimator will assign a weight to each potential symbol value, taking into account the cross-rail or bias influence caused by the residual coupling between the signals on quadrature channels for a given symbol duration. In addition, the disclosed receiver includes a mode sifter which evaluates the weighted values for each symbol estimate and assigns final estimates to each symbol value, taking into account the influence of codewords transmitted during one or more successive symbol intervals on one another.

Data transmitter and receiver of a spread spectrum communication system using a pilot channel

Abstract: An improved spread spectrum communication system includes a transmitter and a receiver utilizing a pilot channel for the transmission of pure rather than modulated PN codes for code acquisition or tracking purposes with a lower bit error rate. The pilot signal is used to obtain initial system synchronization and phase tracking of the transmitted spread spectrum signal. At the transmitter side, Walsh an orthogonal code generator, a Walsh modulator, a first PN code generator, a first band spreader, a second band spreader, finite impulse response filters, digital-to-analog converter, low-pass filters, an intermediate frequency mixer, a carrier mixer, a band-pass filter are used to transmit a spread spectrum signal. At the receiver side, a corresponding band-pass filter, a carrier mixer, an intermediate-frequency mixer, low-pass filters, analog-digital converters, a second PN code generator, an I channel despreader, a Q channel despreader, a PN code synchronization controller, a Walsh an orthogonalcode generator, a first Walsh demodulator, a second Walsh demodulator, accumulator & dump circuits, a combiner, and a data decider are used to demodulate a received spread spectrum signal.

A programmable analog cellular neural network CMOS chip for high speed image processing

Abstract: A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4/spl times/4 CNN prototype system has been designed in a 2.4 /spl mu/m CMOS technology and successfully tested. The cell density is 380 cells/cm/sup 2/ and the cell time constant is 10 /spl mu/s. The current drain for a typical template is 40 /spl mu/A/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128/spl times/128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies. >

Chip on Board: Technologies for Multichip Modules

Abstract: Preface Acknowledgments A brief introduction to wire bonding, tape automated bonding, and flip chip on board for multichip module applications Making COB testing tractable: chip pretest and system diagnostics Chip level interconnect wire bonding for multichip modules Chip level interconnect: wafer bumping and inner lead bonding Chip level interconnect: solder bumped flip chip Chip attachment Wire bonding chip on board Tape automated bonding chip on board and on MCM-D Solder bumped flip chip attach on SLC board and multichip module Micron bump bonding chip on board chip on board encapsulation Underfill encapsulation for flip chip applications Index

Mobile communication system using various multiple access methods

Abstract: A mobile communication system in which various access methods may be selected according to the user's priority. In the mobile communication system, each of a mobile station and radio base stations has a radio processor, which has TDMA, CDMA and FDMA communication units. The CDMA communication unit comprises channel coders each for performing a primary modulation to a transmitting signal, spread-spectrum code generators for respectively generating different spread-spectrum signals, a clock generator/controller for controlling the generation of chip clocks to control the generation of the spread-spectrum codes, oscillators for setting different carrier frequencies to outputs calculated as products, and a CPU for generally controlling various parts or elements to control the assignment of a CDMA signal or a TDMA signal to an arbitrary time slot transmitted from the TDMA communication unit. The radio processor transmits different signals of different access methods existing in each time slot of the same frame different signals.

A new block-matching criterion for motion estimation and its implementation

Abstract: A novel and efficient block-matching motion estimation criterion called minimized maximum error (MiniMax) is considered. The proposed method can save hardware area about 15% with acceptable video performance. A chip which combines the MiniMax matching criterion and the one-dimensional full search algorithm is presented. The ASIC is motivated by the need of the intensive computational demand to perform motion estimation in real time. The proposed single chip can match the applications of H.261 and MPEG international standards. Chip cascading is allowed for larger searching range applications. >

Method and apparatus for testing integrated circuit chips

Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

A novel approach for the thermal characterization of electronic parts

Abstract: The accurate prediction of operating temperatures of temperature sensitive electronic parts at the component, board and system level is seriously hampered by the lack of reliable, standardized input data. The situation which prevails today is that component manufacturers supply to end-users experimental data which characterizes the thermal behaviour of packages under a set of standardized and idealized conditions. Such characterizations normally involve the junction-to-case thermal resistance or the junction-to-ambient resistance according to MIL or SEMI standards. There are several practical difficulties associated with such an approach, which will be briefly commented upon. Today, the need for more accurate junction temperature prediction becomes increasingly urgent, and the call for a precise definition of the various thermal resistances is heard by a growing number of researchers. The paper continues with a survey of the open literature and discusses the pros and cons of several methods that describe the thermal behaviour of electronic parts. It is concluded that none of these methods is capable of meeting the objectives that are proposed. A novel approach is introduced, based on the derivation of a simple resistance network starting from a detailed model using optimization techniques. The proposed method is applied to two cases: a so-called 'validation' chip, functioning as a benchmark for the software that is used to generate the detailed model, and a 208-PQFP component. It is demonstrated that it is possible to create a compact model comprising a simple resistance network, representing the detailed model to a high accuracy which is independent of the boundary conditions.

Methods and apparatus for secure hardware configuration

Abstract: Methods and apparatus are provided for electronically configuring hardware features and options. A computer chip encoding method is provided in which a predetermined code or encryption sequence is uniquely associated with a computer chip. This code is used to modify a hardware configuration by enabling new features or options. The systems and methods reduce manufacturing and inventory costs by allowing a generic product to be produced which is then customized to meet the needs of the user. In addition, features and options of a data processing system can be dynamically upgraded without interruption of service or hardware replacement.

Dynamic sectorization in a spread spectrum communication system

Abstract: A system and method for dynamically varying traffic channel sectorization within a spread spectrum communication system is disclosed herein. In a preferred implementation the system is operative to convey information to at least one specified user in a spread spectrum communication system and includes a pseudorandom code generator (50) for generating, at a predetermined chip rate, a pseudorandom noise (PN) signal of a predetermined PN code. The PN signal is then combined with a first information signal in a spread spectrum transmitter (42) to provide a PN spread information signal. The system further includes at least one additional spread spectrum transmitter (44, 46) each for receiving through a respective delay element (52, 54) delayed versions of the PN signal for providing at least one additional modulation signal. A switching transmission network (74) is disposed to selectively transmit via antennas (85, 86) the first and additional modulation signals respectively to a first and at least one additional coverage area. Selective transmission of the first and the at least one additional modulation signal results in variation in size of a first user sector. The first user sector is associated with a first set of traffic channels, one of which is allocated to the specified user. The system may also be configured to selectively receive, and coherently combine, first and second modulation signals from first and second coverage areas.

Chip level waveguide sensor

Abstract: Waveguide sensors are formed on a chip package which contains at least one source and at least one detector. Simple waveguide elements are mounted on the chip. Waveguide defining elements can also be formed integrally with the chip package so that simple waveguide bodies can be inserted or removed. Various geometries of source, reference detector, and sensing detector can be produced. A liquid waveguide sensor is formed by filling a waveguide channel with a liquid reagent.

Multi-chip semiconductor chip module

Abstract: A semiconductor device including a plurality of chip units each defined by a side wall and arranged in a state such that a side wall of a chip unit abuts a corresponding side wall of an adjacent chip unit, and an interconnection structure for interconnecting a plurality of terminals of a side wall of a chip unit to corresponding terminals of a side wall of an adjacent chip unit that abuts the chip unit at the respective side walls.

Fully scalable parallel processing system having asynchronous SIMD processing

Abstract: Parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as work-station or supercomputer.

High density inter-chip connections by electromagnetic coupling

Abstract: Signal communication paths between multiple chips are established through inter-chip electro-magnetic coupling, thereby potentially eliminating mechanical inter-chip contacts and increasing inter-chip interconnection capacity while maximizing chip real estate allocated to a circuit layer. In one embodiment, multiple chips each include a conductive layer, disposed over a circuit layer on a substrate, divided into electro-magnetic coupling device elements such as capacitor plates. When utilizing capacitor plates, chips are arranged face-to-face with opposing chips having mirror image capacitor plate patterns to form a plurality of capacitors. Conventional signal transmission circuits produce time-varying signals which propagate to conventional signal receiving circuits of another chip via an embodiment of electro-magnetic signal communication paths formed by the capacitors. In another embodiment, one of the chips may function as a passive chip carrier that includes a conventional communication path between sets of capacitor plates that capacitively interconnect multiple chips that are facially opposed to the chip carrier. In another embodiment, chips having a capacitive interconnect layer can be combined into arrays with each array arranged in an offset, face-to-face spatial orientation with respect to at least one other array. Because the arrays are offset, one chip may be capacitively coupled to more than one other chip. As a result, any chip may communicate with any other chip by propagating a transmitted signal from chip to chip via capacitor links until received by a destination chip.