Showing papers on "Chip published in 1996"

Methods for concurrently processing multiple biological chip assays

Abstract: Methods for concurrently processing multiple biological chip assays by providing a biological chip plate comprising a plurality of test wells, each test well having a biological chip having a molecular probe array; introducing samples into the test wells; subjecting the biological chip plate to manipulation by a fluid handling device that automatically performs steps to carry out reactions between target molecules in the samples and probes; and subjecting the biological chip plate to a biological chip plate reader that interrogates the probe arrays to detect any reactions between target molecules and probes.

Single chip modules, repairable multichip modules, and methods of fabrication thereof

Abstract: Multichip and single chip modules are presented as well as a chips first fabrication of such modules. The multichip module comprises a plurality of chips affixed in a planar array by a structural material which surrounds the sides of the chips such that the upper surfaces of the chips and an upper surface of the structural material are co-planar and the lower surface of at least one chip and a lower surface of the structural material are co-planar. A photo-patternable dielectric is disposed directly on the upper surfaces of the chips. The photo-patternable dielectric includes vias to at least some contact pads at the upper surfaces of the chips and the module further comprises an intrachip metallization layer on the photo-patternable dielectric layer. Subsequent processing provides a multi-layer chip interconnect structure over the intrachip metallization layer and photo-patternable dielectric. Testing and repair of the module can be accomplished prior to or subsequent to fabrication of the multi-layer chip interconnect. Formation of multiple single chip modules is accomplished by singulating the multichip module into individual packages.

An overview of multi-carrier CDMA

Abstract: We review new multiple access schemes based on a combination of code division and multi-carrier (also known as OFDM: orthogonal frequency division multiplexing) techniques, such as multi-carrier code division multiple access (MC-CDMA), multicarrier DS-CDMA and multitone CDMA (MT-CDMA). We discuss their advantages and disadvantages, and present some computer simulation results on the down-link bit error rate (BER) performance in a frequency selective slow Rayleigh fading channel. Code division and OFDM based multiple access schemes have drawn a lot of attention in the field of wireless personal and multimedia communications because of the need to transmit at a high data rate in a mobile environment.

256/spl times/256 CMOS active pixel sensor camera-on-a-chip

Abstract: A CMOS imaging sensor is described that uses active pixel sensor (APS) technology and permits the integration of the detector array with on-chip timing, control, and signal chain electronics. This sensor technology has been used to implement a CMOS APS camera-on-a-chip. The camera-on-a-chip features a 256/spl times/256 APS sensor integrated on a CMOS chip with the timing and control circuits, and signal-conditioning to enable random-access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms). The chip features simple power supplies, fast readout rates, and a digital interface for commanding the sensor, as well as for programming the window-of-interest readout and exposure times. Excellent imaging has been demonstrated with the APS camera-on-a-chip, and the measured performance indicates that this technology will be competitive with charge-coupled devices (CCD's) in many applications.

Multistage linear receivers for DS-CDMA systems

Abstract: A new family of multistage low-complexity linear receivers for direct sequence code division multiple access (DS-CDMA) communications is introduced. The objective of the proposed design is to mitigate the effect of multiple access interference (MAI), the most significant limiting factor of user capacity in the conventional DS-CDMA channel. The receivers presented here employ joint detection of multiple users and therefore require knowledge of all the signature codes and their timing. In addition, for a multipath environment, reliable estimates of the received powers and phases are assumed available for maximal ratio RAKE combining. Each stage of the underlying design recreates the overall modulation, noiseless channel, and demodulation process. The outputs of these stages are then linearly combined. The combining weights can be chosen to implement different linear detectors, including the decorrelating and minimum mean square error (MMSE) detectors. In this paper, we focus on implementing the MMSE detector. Simulation results illustrate that significant performance gains can be achieved in both synchronous and asynchronous systems.

Cellular communication system with dynamically modified data transmission parameters

Abstract: An apparatus and process for improving the performance of a cellular communication system using direct sequence spread spectrum techniques. The apparatus and process enable dynamic modification of communication system parameters including PN code length, chipping rate and modulation technique for transmission of a data packet. Modification is based on proximity of the transmitter and receiver, transmitter and receiver capabilities, and other factors. The system evaluates tradeoffs between data transmission speed and communication range to improve system performance.

Automatic power control system for a code division multiple access (cdma) communications system

Abstract: A receiver receives signals and noise over a frequency spectrum of a desired received signal. The desired received signal is spread using code division multiple access. The received signals and noise are demodulated to produce a demodulated signal. The demodulated signal is despread using a code uncorrelated with a code associated with the desired received signal. A power level of the despread demodulated signal is measured as an estimate of the noise level of the frequency spectrum.

Single layer leadframe design with groundplane capability

Abstract: A method of making an electronic package. The method includes the step providing a leadframe of a single layer of material. The leadframe includes a semiconductor chip support, a plurality of signal leads, and a common ground portion substantially surrounding the chip support portion. A semiconductor chip having a plurality of signal sites and a plurality of ground sites is positioned on the semiconductor chip support of the leadframe. Selected ones of the signal sites of the semiconductor chip are selectively electrically connected to respective ones of the signal leads of the lead frame and selective ones of the ground sites of the semiconductor chip are selectively electrically connected to the common ground portion of the leadframe. Each of the signal leads of the leadframe are electrically isolated from each other and from the common ground portion of the leadframe.

Millimeter-wave performance of chip interconnections using wire bonding and flip chip

Abstract: The performances of two different interconnection techniques for coplanar MMICs, wire bonding and flip chip, are investigated at millimeter-wave frequencies. By developing an accurate model for the interconnections, which is validated with experimental data up to 120 GHz, the limitations with respect to frequency and interconnection distance of either technique are pointed out, yielding useful data for the design of hybrid MMW-subsystems.

Single chip multiprocessor architecture with internal task switching synchronization bus

Abstract: A plurality of processors which can be the same or different are formed on a single integrated circuit chip together with a memory controller and an I/O controller, and are interconnected by a data transfer bus. The processors can have larger word lengths and operate at higher speeds than comparable single chip processors due to reduced latency and signal path lengths. The processors are further interconnected by a processor synchronization bus which enables one processor to cause another processor to perform a task by generating an interrupt and passing the required parameters. The parameters can be passed via shared memory, or via a bidirectional data section of the processor synchronization bus. A processor running a large scale CAD or similar application can cause a smaller processor to perform I/O tasks in native code. A multiprocessor system can be configured as including a Single-Chip module (SCM), a Multi-Chip Module (MCM), Board-Level Product (BPL), or as a box-level product which includes a power supply.

Direct sequence frequency ambiguity resolving receiver

Abstract: A parallel frequency acquisition technique is disclosed for increasing receiver sensitivity and increasing process gain while reducing the necessary preamble duration required for spread spectrum acquisition. In addition, techniques are disclosed for reducing the effects of jamming and impulse noise on the performance of the receiver as well as enhanced antenna diversity approaches. Further, techniques are taught which compensate for chip code alignment drift, providing an associated transmitter maintains carrier and chip code coherence. These techniques allow for the use of lower cost frequency setting crystals in both the receiver and transmitter as well as the operation of the system over a wider temperature range.

Mitigation of multipath effects in global positioning system receivers

Abstract: A technique for minimizing or eliminating the effect of multipath signals in a receiver processing pseudorandom (PRN) code signals, such as in a global positioning system (EPS) receiver. The presence of multipath signals adversely affects both code measurements and carrier phase measurements of received PRN signals. One aspect of the invention provides for improved code tracking in the presence of multipath signals, by sampling the received code with a multipath mitigation window (MMW) (FIG. 25D) that results in a code error function (FIG. 25F) that reduces or eliminates the multipaht effects. The MMW, which may by any of a number of preferred waveforms (FIGS. 35b-35E), provides a code error function that varies in opposite directions from zero at a desired tracking point (402), but assumes a nearly zero value when the MMW is advanced from the tracking or synchronization point by more than a small fraction of a code chip. Because of this nearly zero code error value on the early side of the desired tracking point, delayed multipath signals will have a corresponding code error function that is nearly zero (FIG. 25F) at the desired tracking point of the directly received signals, and the multipath signals will, therefore, have little or no effect on the desired tracking point and on code synchronization. The effects of multipath signals on carrier phase measurements are minimized by sampling the received signals, together with their possible multipath components, before and immediately after code transitions (vectors A and B, respecitvely). The vector rellationship of the directly received (D) and multipath (M) signals is such that performing a vector average of the two types of samples (A and B) produces the directly received signal (D) and its correct phase, with many, if not all, of the multipath components (M) eliminated.

Digital downconverter/despreader for direct sequence spread spectrum CDMA communications system

Abstract: A system for digitally downconverting and despreading a multi-channel analog direct sequence spread spectrum signal is provided. The system includes a free-running, non-steering, clock generator which outputs an A/D sample clock, and an A/D sample clock having a rate which is an integral multiple of a chip rate of the spread spectrum signal. An A/D converter which receives the spread spectrum signal and the A/D sample clock and outputs a digitized multi-channel signal from the multi-channel spread spectrum signal, and a local pseudo-noise sequence signal source which outputs M local pseudo-noises, wherein M is an integer greater that 1 is also included. A multi-channel complex downconverter/polyphase filter which receives the digitized multi-channel signal and the A/D sample clock and a sample timing phase control signals, simultaneously filters and downconverts the digitized multi-channel signal to baseband, corrects timing phase misalignment between the digitized multi-channel signal and the locally generated pseudo-noise sequences, and outputs a multi-channel complex corrected baseband signal is provided.

An Evaluation of Chip Separation Criteria for the FEM Simulation of Machining

Abstract: Different chip separation criteria for the FEM simulation of machining were examined. Criterion based on distance between the tool tip and the node located immediately ahead, criterion based on maximum shear stress in the element ahead of the tool tip, criterion based on average maximum shear stress in the shear plane, and criterion based on a combination of distance and stress were investigated. Under conditions of smooth separation of chip from workpiece, simulation results showed that, during steady-state cutting, the type of chip separation criteria did not greatly affect chip geometry, nor distributions of stress and strain. The magnitude of the chip separation criteria also did not significantly affect chip geometry and distributions of stress in the chip but it did affect the chip separation process, distributions of stress in the machined surface, and distributions of effective plastic strain both in the chip and in the machined surface. During the initiation of cutting, neither the geometrical nor physical criteria simulate the machining process correctly. A combination of geometric and physical criteria was also recommended in this study.

Fan-out semiconductor chip assembly

Abstract: A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid material to form a compliant layer filling the space between the package element and the dielectric element, and surrounding the leads. The dielectric element and package element extend outwardly beyond the edges of the chip, and physically protect the chip. The assembly may be handled and mounted by conventional surface mounting techniques. The assembly may include additional circuit elements such as capacitors used in conjunction with the chip.

Materials and mechanics issues in flip-chip organic packaging

Abstract: The strength of flip chip organic packaging technology rests upon the knowledge and manufacturing base of C4 solder bump chip interconnection, and printed circuit technology infrastructure. The key innovation was the underfill encapsulation between the chip and the laminate which overcame the road-block of low cycle fatigue of C4 solder bump due to large CTE difference between silicon and laminate. The advent of SLC (surface laminar circuit) innovation extends the flip chip technology to higher solder bump density and larger chip I/O expected for future generations of semiconductors. The flip chip packages contain new materials, interfaces, and new processes which in turn govern the mechanical integrity of the packaging module and module card assembly. The increasing pervasiveness of electronic packages requires meeting new sets of environments. It is important to have a good understanding of materials, interface, metrology and mechanics issues related to organic packages, and how to apply this understanding in the modelling of design, process and reliability of flip chip. This paper will deliver an overview of some of the key technical challenges associated with materials and mechanics in FCA (flip-chip attach) assembly on organic carriers.

Modeling, measurement, and simulation of simultaneous switching noise

Abstract: The computer package designer depends on modeling power supply noises to ensure that system designs will function properly. Power supply noises can have a tremendous effect on system operation and performance. The circuit simulation of a system power distribution is very challenging since it requires accurate models of active devices, passive components, transmission lines, and a very large power distribution network. This paper presents the development of a high-frequency power distribution model for the simulation of simultaneous switching noise of a complementary metal-oxide-semiconductor (CMOS) chip on a multilayered ceramic substrate. Measurements are performed on a CMOS chip with simultaneously switching off-chip drivers (OCD's). The modeling approach is validated by the excellent agreement between the measurement waveforms and simulation results.

A cnn universal chip in cmos technology

Abstract: This paper describes the design of a programmable cellular neural network (CNN) chip with added functionalities similar to those of the CNN universal machine. The prototype contains 1024 cells and has been designed in a 1.0 μm, n-well CMOS technology. Careful selection of the topology and design parameters has resulted in a cell density of 31 cells mm -2 and around 7-8 bits accuracy in the weight values. Adaptive techniques have been employed to ensure accurate external control and system robustness against process parameter variations.

LED display packaging with substrate removal and method of fabrication

Abstract: A light emitting diode display package and method of fabricating a light emitting diode (LED) display package including a LED array display chip, fabricated of an array of LEDs, formed on a substrate, having connection pads positioned about the perimeter of the LED array display chip, a separate silicon driver chip having connection pads routed to an uppermost surface, positioned to cooperatively engage those of the display chip when properly registered and interconnected using wafer level processing technology. The display chip being flip chip mounted to the driver chip and having a layer of interchip bonding dielectric positioned between the space defined by the display chip and the driver chip. The LED display and driver chip package subsequently having selectively removed the substrate onto which the LED array was initially formed, thereby exposing the connection pads of the display chip and a remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer. The light emitted from the LED display chip, being emitted through the remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer of the display chip.

Multi-channel pill with integrated optical interface

Abstract: An optical interface incorporated into a multi-channel telemetry device used principally to provide data representing physiological conditions in a human subject. Information is transmitted without the need of a bio-compatible electrical connection via an optical link which conveys calibration parameters and commands to control the operation of the telemeter. The optical link is configured to reside completely on an integrated circuit chip. Of the three channels designed into the chip by means of appropriate electronic circuitry, one of the channels measures temperature and the other two channels are dedicated to develop generic information selectively derived from other physiological conditions. Calibration information that is programmed into the telemeter by means of the optical interface is retrieved by time division multiplexing with one of the generic channels.

Spread spectrum transmitter and receiver employing composite spreading codes

Abstract: In a system with a spread spectrum transmitter and receiver employing composite spreading codes, the transmitter spreads, in a spreading part, a baseband modulated signal by a short code from a short code generator and a long code from a long code generator with a longer chip period than that of the short code and then transmits the spread baseband modulated signal. The receiver despreads a spread baseband received signal in a receiving part by a pair of short and long codes in one despreading part to obtain a baseband modulated signal of a direct path and despreads the spread baseband received signal by the pair of short and long codes delayed by a multipath delay time difference in the other despreading part to obtain a baseband modulated signal of a delayed path, and the baseband modulated signals thus obtained are diversity-detected to obtain a detected baseband signal.

Clock skew optimization for ground bounce control

Abstract: High speed synchronous digital systems require large switching currents to facilitate rapid signal transitions. These large currents create voltage drops on the power distribution network and necessitate expensive chip packaging with a large number of supply pins. In this paper we propose a novel technique to reduce the dynamic transient current drawn from the supply pins. Our approach is based on sub-dividing the synchronous clocking into multiple sub-clocks with relative skew. This spreads the computation across the entire clock cycle instead of largely occurring at the beginning. Timing constraints must also be obeyed, so that no races or timing errors are introduced. We propose an exact algorithm based on integer linear programming to solve this problem. We have used our method in the design of a 5 GHz ECL encoder chip to achieve a factor of two reduction in ground bounce, as shown by HSPICE simulations. We also obtained order-of-magnitude improvements in ground bounce on benchmarks laid our in submicron CMOS technology. The approach potentially leads to significant reductions in packaging costs.

Time division duplex repeater for use in a cdma system

Abstract: A method and apparatus for time division duplex (TDD) repeating a spread spectrum signal, said spread spectrum signal comprised of a series of code symbol modulated with a pseudonoise (PN) sequecne. The TDD repeater receives intermittently the spread spectrum signal at a location remote from a source supplying the spread spectrum signal. The TDD repeater amplifies and delays the received spread spectrum signal by a predetermined amount. The TDD repeater transmits intermittently the delayed amplified received spread spectrum signal such that the TDD is not receiving the spread spectrum signal when it is transmitting the signal energy.

A time digitizer CMOS gate-array with a 250 ps time resolution

Abstract: A pipelined time digitizer CMOS gate-array has been developed using 0.5 /spl mu/m Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion.

Accelerated testing for cosmic soft-error rate

Abstract: This paper describes the experimental techniques which have been developed at IBM to determine the sensitivity of electronic circuits to cosmic rays at sea level. It relates IBM circuit design and modeling, chip manufacture with process variations, and chip testing for SER sensitivity. This vertical integration from design to final test and with feedback to design allows a complete picture of LSI sensitivity to cosmic rays. Since advanced computers are designed with LSI chips long before the chips have been fabricated, and the system architecture is fully formed before the first chips are functional, it is essential to establish the chip reliability as early as possible. This paper establishes techniques to test chips that are only partly functional (e.g., only 1Mb of a 16Mb memory may be working) and can establish chip soft-error upset rates before final chip manufacturing begins. Simple relationships derived from measurement of more than 80 different chips manufactured over 20 years allow total cosmic soft-error rate (SER) to be estimated after only limited testing. Comparisons between these accelerated test results and similar tests determined by ``field testing`` (which may require a year or more of testing after manufacturing begins) show that the experimental techniques are accuratemore » to a factor of 2.« less

An accurate equivalent circuit model of flip chip and via interconnects

Abstract: In this paper, the transition discontinuities of flip chip circuits are modeled and investigated using finite-difference time-domain (FDTD) method to predict the S-parameters of different packages. This includes transition between two coplanar lines on the chip and mother board and transition between two striplines in a package. The computed S-parameter of the flip chip package using the FDTD model are used to develop an equivalent circuit for the transition discontinuity over a wide frequency band. A general and accurate equivalent circuit model of the interconnect has been developed and presented. In this circuit model, a statistical analysis is used to compute the value of the circuit elements. Also, losses in the flip chip package are represented by a simple function versus frequency. These losses include substrate loss of the chip and the mother board due to excitation of surface wave and radiation loss due to the bump. Conductor and material substrate losses are not included in this circuit model. Good agreement has been obtained between the S-parameters of the FDTD model and the equivalent circuit model over a wide frequency band of up to 50 GHz. Furthermore, the effects of the bump dimensions on the equivalent circuit model has been also evaluated and presented. The results show important issues in the design of the flip chip interconnect. The bump dimensions can be used as impedance matching parameters to achieve minimum losses over a wide frequency band. The presented equivalent circuit model can be used in commercial circuit simulators to predict monolithic microwave/millimeter wave integrated circuit (MMIC) performance including the package.

Single-chip interpolating time counter with 200-ps resolution and 43-s range

Abstract: In this paper, we present a design and test results of the interpolating time counter implemented on a single field programmable gate array (FPGA) chip. The counter contains two 6-bit time-to-digital converters (TDCs), each having 200-ps resolution (LSB) within 10 ns range, and the 32-bit, 100-MHz real-time counter, which is also used for frequency measurement. The utilization of the logic cells on the FPGA chip is 93%. The software correction of the TDC's nonlinearity errors resulted in lowering the random error of the counter to 0.65 LSB or 129 ps (RMS).

Microcircuit with memory that is protected by both hardware and software

Abstract: A secure electronic data module containing a monolithic semiconductor chip of the type having a memory that is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that my be a printed circuit board or another chip; a multi-level interlaced power and ground lines using minimum geometries; and a detection circuit block for detecting an external trip signal that my be produced by a prespecified change in an operating condition brought on by unauthorized accessing, or an internal trip signal that may be produced by shorting of power and ground lines or by a change in an oscillator's frequency, also associated with or appurtenant to unauthorized accessing of the secure memory.

Sizing of clock distribution networks for high performance CPU chips

Abstract: In a high performance microprocessor such as Digital's 30O MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a complex grid with multiple drivers. The large capacitance of this distribution grid together with the high clock frequency results in substantial power dissipation in the chip. In this paper, we describe techniques to size the interconnect segments (thus reducing their capacitance) of the distribution network while meeting certain design goals. These techniques place no restrictions on the topology of the network being sized, and have been successfully used on very large examples.

Channel access and interference issues in multi-code DS-CDMA wireless packet (ATM) networks

Abstract: Multi-Code Direct-Sequence Code-Division-Multiple-Access (MC-CDMA) has been proposed as a flexible multiple access scheme for wireless packet networks that support a large variety of mobiles with different and even time-varying rates. Using MC-CDMA, traffic streams with significantly different transmission rates can be easily integrated into a unified architecture, with all the transmissions occupying the same bandwidth and having the same spread spectrum processing gain. In this paper, we address medium-access and interference issues in MC-CDMA wireless packet networks. For medium access, we propose and study Multi-Code CDMA (MC-CDMA) with Distributed-Queueing Request Update Multiple Access (DQRUMA) to form a unified bandwidth-on-demand fair-sharing platform for multi-rate wireless services. DQRUMA is an efficient demand-assignment multiple access protocol for wireless access and scheduling. Pseudo-Noise (PN) codes (primary codes) and optimal power levels are allocated to the mobiles on a slot-by-slot basis, and a Maximum Capacity Power Allocation (MCPA) criterion exploits the sub-code concatenation property of the MC-CDMA transmission. Simulation results show that the system provides close to ideal-access performance for multi-rate mobiles, both with homogeneous traffic characteristics and with a mix of heterogeneous traffic characteristics. Finally, we analyze the effects of MC-CDMA intercell interference on the reverse link (i.e., mobile to cell site) and investigate interference reduction by using the Maximum Capacity Power Allocation (MCPA) criterion. Our results show significant reduction in reverse-link MC-CDMA intercell interference is possible using the MCPA criterion.