Showing papers on "Chip published in 1998"

Self-powered signal processing using vibration-based power generation

Abstract: Low power design trends raise the possibility of using ambient energy to power future digital systems. A chip has been designed and tested to demonstrate the feasibility of operating a digital system from power generated by vibrations in its environment. A moving coil electromagnetic transducer was used as a power generator. Calculations show that power on the order of 400 /spl mu/W can be generated. The test chip integrates an ultra-low power controller to regulate the generator voltage using delay feedback techniques, and a low power subband filter DSP load circuit. Tests verify 500 kHz self-powered operation of the subband filter, a level of performance suitable for sensor applications. The entire system, including the DSP load, consumes 18 /spl mu/W of power. The chip is implemented in a standard 0.8 /spl mu/m CMOS process. A single generator excitation produced 23 ms of valid DSP operation at a 500 kHz clock frequency, corresponding to 11,700 cycles.

An integrated processor and programmable data path chip for reconfigurable computing

Abstract: The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (1101, 1103), and interfaces (319a, 319b, 311) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable "hard-wired" functions.

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Abstract: This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.

Multiple chip assembly

Abstract: This disclosure provides a multiple chip assembly where multiple chips are stacked on top of one another using relatively low melting temperature solder balls. Preferably, the chips (either packages or flip chip attachment) are each mounted to a substrate which is larger in lateral surface area than the associated chip. Each substrate thus has a free area, not masked by the chip, which is utilized to mount a vertically-adjacent substrate. Within this free area, solder balls connect the substrates to provide for vertical logic bus propagation through the assembly and vertical heat dissipation. The solder balls are made to have a relatively low melting temperature, permitting interconnection between chip/substrate layers without affecting connection between chip and substrate or with an intervening carrier. At the same time, the layers are compressed together during such interconnection to bring a thermal transport layer in contact between the bottom of each substrate and the chip of an underlying layer, to facilitate lateral heat dissipation.

Integrated circuit package and method of fabrication

Abstract: The present invention is directed to a semiconductor package and its method of manufacture. Conductors mounted on a flexible polymer tape are used to connect a semiconductor chip to a substrate. The flexible polymer tape can be folded back under the chip to reduce the size necessary for mounting the assembly to almost that of the chip itself. The polymer tape also provides flexibility to reduce stresses on the electrical connections caused by thermal expansion and compression. Additionally, the present invention allows for the stacking of semiconductor chips on top of one another, reducing signal propagation delays between them.

Semiconductor device using a chip scale package

Abstract: A semiconductor device package which eliminates the possibility of damages to a solder connected portion of a flip-chip connected chip by load, or which eliminates ultrasonic output at the time of wire bonding is described. Electrodes of a first chip are connected to first connection pads corresponding to the electrodes with the first chip being bonded at its rear surface to a rear surface of a second chip. A first resin is interposed in a gap between the first chip and a circuit board so as not to cover the first or second connection pads. Thereafter, the electrode of the second chip is connected to the second connection pads by wires, and the whole device is overlayed by a second resin.

Interconnect and circuit modeling techniques for full-chip power supply noise analysis

Abstract: This paper describes the interconnect and circuit modeling techniques to analyze the on-chip power supply noise for high-performance very large scale integration (VLSI) design. To reduce the complexity of full-chip analysis, a hierarchical power supply distribution model, which consists of a 12/spl times/12 package model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model, is developed. This integrated chip-and-package model provides a complete analysis of the resistive IR drop, inductive delta-I noise, and the on-chip Vdd distribution. It also allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise. Analysis results of our benchmark microprocessor chips will be presented to demonstrate the various applications of this methodology.

Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces

Abstract: A bump-bonded multi-chip flip-chip device (100) is formed by manufacturing a mother chip (102) having a first set (207) of bumps (212) and a second set (209) of bump contacts (210). A daughter chip (104) is also formed which has conductive bumps (312). The daughter chip (104) and the mother chip (102) are placed face-to-face and contact is made between the daughter chips bumps (312) and the mother chips bump contact regions (210). After interconnection of the daughter chip (104) and the mother chip (102), the mother chip (102) is contacted to an IC package (106) using the bumps (212). The package (106) uses a plurality of metallic layers interconnected selectively by conductive vias in order to route signals between the mother chip (102), the daughter chip (104), and external terminals (112) of the package (106).

Chip capacitors and chip capacitor electromagnetic interference filters

Abstract: An electromagnetic interference (EMI) filter capacitor assembly is provided for shielding and decoupling a conductive terminal pin or lead of the type used, for example, in an implantable medical device against passage of external interference signals. The EMI filter is constructed of relatively inexpensive ceramic chip capacitors which replace relatively expensive feedthrough capacitors as found in the prior art. The chip capacitors are mounted directly onto a hermetic feedthrough terminal in groups of two or more which vary in physical size, dielectric material and capacitance value so that they self-resonate at different frequencies. This "staggering" of resonant frequencies and direct installation at the hermetic terminal provides the EMI filter with sufficient broadband frequency attenuation. In one preferred form, multiple chip capacitor groupings are mounted onto a common base structure, with each capacitor grouping associated with a respective terminal pin. In another preferred form, a non-conductive substrate is provided with metalized circuit traces to better accommodate the mounting of the chip capacitors. Additionally, novel chip capacitor geometry/termination-metallization is provided which significantly reduces the internal inductance of the capacitor to improve its high frequency performance as an EMI filter. Such reduced inductance chip capacitor designs are readily adaptable to incorporate multiple electrically isolated active plate sets within a single monolithic casing.

Power reduction in a multiprocessor digital signal processor based on processor load

Abstract: Improved operation of multi-processor chips is achieved by dynamically controlling processing load of chips and controlling, significantly greater than on/off granularity, the operating voltages of those chips so as to minimize overall power consumption. A controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage. Further improvement is possible by controlling the supply voltage of individual processing elements within the multi-processor chip, as well as controlling the supply voltage of other elements in the system within which the multi-processor chip operates.

Poly routing for chip interconnects with minimal impact on chip performance

Abstract: Methods for using the polysilicon layer to route the cells in the ASIC are disclosed. The poly layer of an IC chip is used for routing chip interconnects with minimal impact on the chip performance by selecting nets in the IC chip based on a predetermined or a desired qualification. A maximum allowable length of the poly layer to be used for chip interconnects is determined based on the intended technology of the chip. A filtering algorithm filters the netlist to provide a set of candidate nets that are suitable for poly layer routing based on the predetermined or desired qualification. A routing tool routes the selected nets that have been selected by the filtering algorithm by using the poly layer. Some of the poly layer routings are further rejected by a post processing step.

Method and system for providing a probe array chip design database

Abstract: Systems and method for organizing information relating to the design of polymer probe array chips including oligonucleotide array chips. A database model is provided which organizes information interrelating probes on a chip, genomic items investigated by the chip, and sequence information relating to the design of the chip. The model is readily translatable into database languages such as SQL. The database model scales to permit storage of information about large numbers of chips having complex designs.

A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

Abstract: A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-/spl mu/m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3/spl times/ the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10/sup -14/.

Chip-level detection in optical code division multiple access

Abstract: A new detector for optical code-division multiple-access (CDMA) communication systems is proposed. This detector is called the chip-level receiver. Both ON-OFF keying (OOK) and pulse-position modulation (PPM) schemes, that utilize this receiver, are investigated in this paper. For OOK, an exact bit error rate is evaluated taking into account the effect of both multiple-user interference and receiver shot noise. An upper bound on the bit error probability for pulse-position modulation (PPM)-CDMA system is derived under the above considerations. The effect of both dark current and thermal noises is neglected in our analysis. Performance comparisons between chip-level, correlation, and optimum receivers are also presented. Both correlation receivers with and without an optical hardlimiter are considered. Our results demonstrate that significant improvement in the performance is gained when using the chip-level receiver in place of the correlation one. Moreover the performance of the chip-level receiver is asymptotically close to the optimum one. Nevertheless, the complexity of this receiver is independent of the number of users, and therefore, much more practical than the optimum receiver.

Chip scale packages and methods for manufacturing the chip scale packages at wafer level

Abstract: In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer is provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

Abstract: In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

Circuit and method for ensuring interconnect security with a multi-chip integrated circuit package

Abstract: Circuitry implemented within a multi-chip module comprising a first integrated circuit chip and a second integrated circuit chip coupled together through an interconnect. Both the first and second integrated circuit chips include a cryptographic engine coupled to the interconnect and a non-volatile memory element used to contain key information. These cryptographic engines are solely used to encrypt outgoing information being output across the interconnect or to decrypt incoming information received from the interconnect. This prevents fraudulent physical attack of information transmitted across the interconnect.

Chip with internal signal routing in external element

Abstract: A semiconductor chip is provided with a dielectric element having conductive features interconnecting electronic elements within the chip with one another. The conductive features replace internal conductors, and can provide enhanced signal propagation between elements of the chip. The conductive features on the dielectric element are connected to contacts on the chip by deformable conductive elements such as flexible leads so that the dielectric element remains movable with respect to the chip. The dielectric element may have a coefficient of expansion different from that of the chip itself.

Low-power Viterbi decoder for CDMA mobile terminals

Abstract: An efficient state-sequential very large scale integration (VLSI) architecture and low-power design methodologies ranging from the system-level to the layout-level are presented for a large-constraint-length Viterbi decoder for code division multiple access (CDMA) digital cellular/personal communication services (PCS) applications. The low-power design approaches are also applicable to many other systems and algorithms. VLSI implementation issues and prototype fabrication results for a state-sequential Viterbi decoder for convolutional codes of rate 1/2 and constraint-length 9 are also described. The chip's core, consisting of approximately 65 k transistors, occupies 1.9 mm by 3.4 mm in a 0.8-/spl mu/m triple-layer-metal n-well CMOS technology. The chip's measured total power dissipation is 0.24 mW at a 14.4 kb/s data-rate with 0.9216 MHz clocking at a supply voltage of 1.65 V. The Viterbi decoder presented here is the lowest power and smallest area core in its class, to the best of our knowledge.

Cracking DES: Secrets of Encryption Research, Wiretap Politics and Chip Design

Abstract: From the Publisher: In clear, easy to read and understand language, this controversial book reveals the full technical details on how researchers and data recovery engineers can build a DES cracker. It includes design specifications and board schematics, as well as full source code for the custom chip.

Testing and burn-in of IC chips using radio frequency transmission

Abstract: A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.

Integrated single chip dual mode raid controller

Abstract: A RAID controller integrated into a single chip (100). The RAID controller chip (100) includes a general purpose RISC processor (121), memory interface logic (128), a host CPU PCI bus (150), at least one back-end I/O interface channel (130), at least one direct memory access (DMA) channel (122), and a RAID parity assist (RPA) circuit (126). The RAID chip enables higher integration of RAID functions within a printed circuit board and in particular enables RAID function integration directly on a personal computer or workstation motherboard. The back-end I/O interface channel is preferably dual SCSI channels. The RAID chip is operable in either of two modes. In a first mode, the chip provides pass through from the host CPU (102) interface directly to the dual SCSI channels (130). This first mode of operation, a SCSI pass-through mode, allows use of the chip for non-RAID storage applications and enables low level manipulation of the disk array in RAID applications of the chip. The first mode of operation permits use of the chip without change to host applications and drivers. Rather, the chip is operable in a manner compatible with known available SCSI controller devices. The second mode of operation, a RAID control mode, provides full RAID management features to the attached host CPU. In the preferred embodiment, the RAID chip presents an Intelligent I/O (I2O) interface to the host CPU to enhance portability and performance of the host/RAID interaction.

Computer-aided design considerations for mixed-signal coupling in RF integrated circuits

Abstract: This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods.

Item locator with attachable receiver/transmitter

Abstract: A device which functions to locate preselected items which are remote from a user. The device comprises two parts; a hand held device and multiple sensors/chips which are applied to objects the user desires to locate. The hand held devices contains a control panel selector buttons for each multiple sensors/chip it is desired to locate. When a preselected button is depressed, a transmitter sends signal containing preselected code. The signal is received by a receiver in each multiple sensors/chip. The receiver in each multiple sensors/chip reads the code and if a match is obtained the receiver enables an audio tone generator in the multiple sensors/chip to send a tone through an audio speaker. The multiple sensors/chip further, transmits a signal to the hand held device which is received by a second receiver and decoded. The second receiver matches the code with the multiple sensors/chip selected and enables a second audio tone generator to send a second tone through a second speaker. Both tones are controlled to become louder the closer the hand held device is to the desired multiple sensors/chip. The multiple sensors/chip has an attachment device permitting attachment to various articles to be found. The hand held device and multiple sensors/chip are powered by a power source.

Within-chip variability analysis

Abstract: Current, integrated circuits are large enough that device and interconnect parameter variations within it chip are as important as those same variations from chip to chip. Previously, digital designers were concerned only with chip-to-chip variability, for which analysis techniques exist; concern for within-chip variations has been in the domain of analog circuit design. In this paper, we lay the groundwork needed to analyze the impact of inter-chip variations on digital circuits and propose an extreme-case analysis algorithm to efficiently determine the worst case performance due to such variability.

Speed and energy analysis of digital interconnections : comparison of on-chip, off-chip, and free-space technologies

Abstract: We model and compare on-chip (up to wafer scale) and off-chip (multichip module) high-speed electrical interconnections with free-space optical interconnections in terms of speed performance and energy requirements for digital transmission in large-scale systems. For all technologies the interconnections are first modeled and optimized for minimum delay as functions of the interconnection length for both one-to-one and fan-out connections. Then energy requirements are derived as functions of the interconnection length. Free-space optical interconnections that use multiple-quantum-well modulators or vertical-cavity surface-emitting lasers as transmitters are shown to offer a speed–energy product advantage as high as 30 over that of the electrical interconnection technologies.

Integrated circuit package for flip chip

Abstract: An integrated circuit package includes a ceramic substrate having a cut out configured to receive a flip chip. The cut out includes vias formed as through holes. A flip chip is received within the cut out of the ceramic substrate and has conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip. The conductive bumps are received within the through holes of the ceramic substrate. A second integrated circuit chip is mounted on the flip chip in back-to-back relationship. A controlled impedance line is secured to the conductive bumps and acts as a coax. In another aspect of the present invention, a heat sink can be mounted on the back of the flip chip, and the second integrated circuit chip mounted on the heat sink.

Stacked carrier three-dimensional memory module and semiconductor device using the same

Abstract: A three-dimensional memory module includes a plurality of semiconductor device units, every adjacent two of which are stack-connected via through-holes by a bump connecting method. Each of the plurality of semiconductor device units includes a carrier having a circuit pattern and the through-holes connected to the circuit pattern. The semiconductor device unit also includes at least one semiconductor memory chip mounted on the carrier such that the semiconductor memory chip is connected to the circuit pattern, and at least one chip select semiconductor chip mounted on the carrier to be connected to the circuit pattern such that the chip select semiconductor chip can select the semiconductor memory chip.

Millimeterwave characteristics of flip-chip interconnects for multi-chip modules

Abstract: Electromagnetic simulations and measurement data of flip-chip transitions are presented. First-order effects are identified and design criteria for mm-wave multi-chip interconnects are derived. In coplanar environment, the flip-chip scheme provides interconnects with excellent low-reflective properties. For conductor-backed structures, the suppression of parasitic modes represents the key issue.

Methods and apparatus for random backoff based access priority in a communications system

Abstract: The present invention provides methods and apparatus for providing access priority in a MAC protocol of a communications system such as, for example, with respect to UMTS RACH. Particularly, the invention introduces several access priority methodologies including: (i) random chip delay access priority (RCDAP); (ii) random backoff based access priority (RBBAP); (iii) variable logical channel based access priority (VLCAP); (iv) UMTS-specific variable logical channel based access priority (VLCAP'); (v) probability based access priority (PBAP); and (vi) retransmission based access priority (REBAP). Each methodology associates some parameter or parameters to access priority classes in order to influence the likelihood of a remote terminal completing a successful access request to a base station.