Showing papers on "Chip published in 2000"

Improved sense-amplifier-based flip-flop: design and measurements

Abstract: Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.

VLSI-NEMS chip for parallel AFM data storage

Abstract: We report the microfabrication of a 32×32 (1024) 2D cantilever array chip and its electrical testing. It has been designed for ultrahigh-density, high-speed data storage applications using thermomechanical writing and readout in thin polymer film storage media. The fabricated chip is the first very large scale integration (VLSI)-NEMS (NanoEMS) for nanotechnological applications. For electrical and thermal stability, the levers are made of silicon, and the heater/sensor element is defined as a lower, doped platform with the tip on top. Freestanding cantilevers are obtained with surface-micromachining techniques, which yield better mechanical stability and heatsinking of the chip than bulk-micromachining releasing techniques do. Two-wiring levels interconnect the cantilevers for a time-multiplexed row/column addressing scheme. By integrating a Schottky diode in series with each cantilever, a considerable reduction of crosstalk between cantilevers has been achieved.

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Abstract: Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging

Analytical comparison of various fiber-optic CDMA receiver structures

Abstract: We study the performance of optical code-division multiple access (CDMA) systems using various receivers structures. Two general classes of receivers based on required electronic bandwidth are studied. Optical orthogonal codes (OOCs) are utilized as signature sequences and the performance studied in this paper takes into account the effect of all major noise sources, i.e., quantum shot-noise, dark current noise, and Gaussian circuit noise. Furthermore, this paper introduces a generalized method of analyzing the performance of various optical CDMA receiver structures. Required mean number of photon count per chip time for reliable transmission of data bits for various receiver structures is investigated. Finally, the advantages and disadvantages of various receiver structures are discussed.

Single-chip computers with microelectromechanical systems-based magnetic memory (invited)

Abstract: This article describes an approach for implementing a complete computer system (CPU, RAM, I/O, and nonvolatile mass memory) on a single integrated-circuit substrate (a chip)—hence, the name “single-chip computer.” The approach presented combines advances in the field of microelectromechanical systems (MEMS) and micromagnetics with traditional low-cost very-large-scale integrated circuit style parallel lithographic manufacturing. The primary barrier to the creation of a computer on a chip is the incorporation of a high-capacity [many gigabytes (GB)] re-writable nonvolatile memory (in today’s terminology, a disk drive) into an integrated circuit (IC) manufacturing process. This article presents the following design example: a MEMS-based magnetic memory that can store over 2 GB of data in 2 cm2 of die area and whose fabrication is compatible with a standard IC manufacturing process.

Code for spectral amplitude coding optical CDMA systems

Abstract: A new code structure for spectral amplitude coding optical code division multiple access (CDMA) is proposed and analysed. It is shown that such codes can effectively suppress the intensity noise and in turn increase the number of active users and improve the bit error rate performance.

The H1 silicon vertex detector

Abstract: The design, construction and performance of the H1 silicon vertex detector is described. It consists of two cylindrical layers of double-sided, double-metal silicon sensors read out by a custom designed analog pipeline chip. The analog signals are transmitted by optical fibres to a custom-designed ADC board and are reduced on PowerPC processors. Details of the design and construction are given and performance figures from the first data-taking periods are presented.

An efficient electrical addressing method using through-wafer vias for two-dimensional ultrasonic arrays

Abstract: This paper presents a technology for high density and low parasitic capacitance electrical interconnects to arrays of Capacitive Micromachined Ultrasonic Transducers (CMUTs) on a silicon chip. Vertical wafer feedthroughs (vias) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the chip. A 20 to 1 high aspect ratio 20 /spl mu/m diameter via is achieved by using Deep Reactive Ion Etching (DRIE). Reduction of the parasitic capacitance of the polysilicon pads to the substrate can be achieved by using Metal Insulator Semiconductor (MIS) operating in the depletion region. This three-dimensional architecture allows for elegant packaging through simple flip-chip bonding of the chip's back side to a printed circuit board (PCB) or a signal processing chip.

Design of system-on-a-chip test access architectures using integer linear programming

Abstract: Test access is a major problem for system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip I/Os, special access mechanisms are required to test them after system integration. An efficient test access architecture should reduce test cost and time-to-market by minimizing test application time. We address several issues related to the design of test access architectures. Even though these design problems are NP-complete, they can be solved exactly using integer linear programming (ILP). As a case study, the ILP models for two hypothetical but representative systems are solved using a public-domain ILP software package.

Module component and method of manufacturing the same

Abstract: The invention relates to a module component having chip components buried in a circuit board, and a method of manufacturing the same, and more specifically it relates to a module component capable of obtaining desired circuit characteristics and functions stably if the size of the component is reduced, being produced very efficiently, and suited to machine mounting, and a method of manufacturing the same. According to the invention, since a desired circuit is composed by disposing a specific number of chip components according to a specified rule, it is not necessary to heat the buried chip components at high temperature when forming a module, chip components are obtained in specified values, and the circuit characteristics, functions, and dimensional precision are stably obtained exactly as designed, and moreover since the chip components are disposed according to a specified rule, it is easy to automate insertion of chip components and increase its operation speed, even if the size of the chip components is reduced, and the circuit composition may be flexibly and easily changed only by changing the inserting position and type of chip components.

Vertically integrated flip chip semiconductor package

Abstract: Provided is a vertically integrated (“chip-over-chip”) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages. Packages in accordance with the invention have increased access speeds between chips and reduced total chip package footprint.

Semiconductor device and method of manufacturing the same

Abstract: An LSI chip has first electrodes. A chip carrier has a board, second electrodes arranged on a first surface of the board, third electrodes arranged on a second surface of the board, and wires connecting second electrodes to third electrode each other. Bumps combine the first electrodes of the LSI chip with the second electrodes of the chip carrier each other. Resin fills a space between a main surface of the LSI chip and a first surface of the board, so as to fix the bumps to each other. Ball electrodes are combined with third electrodes of the chip carrier.

Micromachine stacked flip chip package fabrication method

Abstract: To form a micromachine package, bond pads on a front surface of a controller chip are aligned with corresponding traces on a front surface of a micromachine chip. The bond pads are physically connected to the traces thus mounting the controller chip as a flip chip to the micromachine chip. A bead is formed around a periphery of the controller chip. The bead and the controller chip form an enclosure around a micromachine area in the front surface of the micromachine chip. This enclosure protects the micromachine area from the ambient environment.

Method for transmitting data on viewable portion of a video signal

Abstract: A method of encoding data in the visible portion of a transmitted video signal without degrading display of the received video signal, and for decoding the data in the received video signal. Each group of data bits to be transmitted, referred to a data symbol, is associated with one of a number of longer predetermined sequences of chips. Each chip sequence is divided into a multiplicity of lines of chips, and each line of chips together with its inverse are embedded, in pairwise fashion, in respective pairs of line scans of the video signal prior to its transmission. Received pairs of line scans are operated upon to detect the lines of chips they represent, and each of the number of chip sequences is correlated with the detected line of chips to derive a correlation magnitude. The chip sequence with the largest correlation magnitude is selected as the chip sequence whose data symbol was transmitted.

A generic interface chip for capacitive sensors in low-power multi-parameter microsystems

Abstract: This paper presents a generic low-power sensor interface chip compatible with smart microsystems and a wide range of capacitive transducers. The interface chip is highly programmable, can communicate with an external microcontroller using a nine-line sensor bus standard, contains a switched-capacitor readout circuit, supports sensor self-test, and includes a temperature sensor. The circuit can interface with up to six external sensors and contains three internal programmable reference capacitors in the range of 0.15–8 pF. The chip measures 3.2×3.2 mm in a standard 3-μm single-metal double-poly p-well process, dissipates less than 2.2 mW from a single 5 V supply, and can resolve input capacitance variations of less than 1 fF in 10 Hz bandwidth.

Low-power CMOS digital design with dual embedded adaptive power supplies

Abstract: A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in the decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design.

Method of making stacked chip package

Abstract: A method of making a stacked chip package comprises the steps of: (a) placing a first chip onto a substrate in a manner that solder bumps on the first chip are aligned with corresponding flip-chip pads formed on a surface of the substrate; (b) reflowing the solder bumps; (c) attaching a second chip to the first chip through an adhesive layer; (d) curing the adhesive layer; (e) forming an underfill between the first chip and the substrate; (f) curing the underfill; (g) electrically coupling the second chip to corresponding wire-bondable pads formed on the surface of the substrate; and (h) encapsulating the first chip and the second chip against a portion of the surface of the substrate. This invention is characterized in that the adhesive layer is cured before underfilling thereby forming a protection layer on the first chip. Therefore, the cured adhesive layer can help the first chip to resist stresses created during curing process of the underfill, thereby reducing the problem of die cracking.

Design of orthogonal pulse shapes for communications via semidefinite programming

Abstract: In digital communications, orthogonal pulse shapes are often used to represent message symbols for transmission through a channel. In this paper, the design of such pulse shapes is formulated as a convex semidefinite programming problem, from which a globally optimal pulse shape can be efficiently found. The formulation is used to design filters that achieve (a) the minimal bandwidth for a given filter length; (b) the minimal filter length for a given bandwidth; (c) the maximal robustness to timing error for a given bandwidth and filter length. Bandwidth is measured either in spectral energy concentration terms or with respect to a spectral mask. The effectiveness of the method is demonstrated by the design of waveforms with substantially improved performance over the "chip" waveforms specified in standards for digital mobile telecommunications.

Face-up semiconductor chip assemblies

Abstract: Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

Spread spectrum receiver with multi-path correction

Abstract: A spread spectrum receiver uses a comparison of the magnitude of the code correlation amplitudes at equal power at a one chip spacing to the magnitude at a central position there between to determine if multipath interference is present. The lead or lag error from constructive or destructive multipath interference may also be determined. Inaccuracies due to such interference may then be corrected or minimized by, for example, determining the residual code phase error and/or the prompt or accurate code phase delay.

On-chip picosecond time measurement

Abstract: A flash Time to Digital Converter (TDC) can be calibrated to a precision on the order of the arbiter aperature without precise input signals. A theoretical result useful for calibration of a noise-limited arbiter array is derived, and verified empirically. A test chip with 64 arbiters in a 0.35 /spl mu/m CMOS process shows temporal resolution better than 2 picoseconds.

The role of custom design in ASIC Chips

Abstract: Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Through floorplanning and tiling data paths, the designer places the critical wires first, before the logic is placed. Crafted datapath cells structure wiring at the other end of the spectrum by keeping local wires short enabling the use of minimum sized drivers. Routing the wires first gives early visibility of timing issues, allows the design to be optimized to drive the exact wire load, and enables the use of fast circuit styles.

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

Abstract: This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-/spl mu/m CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems.

Single-chip CMOS optical microspectrometer

Abstract: Numerous applications, e.g., systems for chemical analysis by optical absorption and emission line characterization, will benefit from the availability of low-cost single-chip spectrometers. A single-chip CMOS optical microspectrometer containing an array of 16 addressable Fabry–Perot etalons (each one with different resonance cavity length), photodetectors and circuits for read-out, multiplexing and driving a serial bus interface has been fabricated. The result is a chip that can operate using only four external connections (including Vdd and Vss) covering the visible spectral range of the spectrum with FWHM=18 nm. Frequency output and serial bus interface allow easy multi-sensor, multi-chip interfacing using a microcontroller or a personal computer. Power consumption is 1250 μW for a clock frequency of 1 MHz.

On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

Abstract: On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.

Chip-core framework for systems-on-a-chip

Abstract: A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.

Content addressable memory system with cascaded memories and self timed signals

Abstract: A system includes cascaded content addressable memory (CAM) chips connected to a common bus. Each CAM chip includes a CAM array, a self-timed signal generator and hit propagation and match address transfer circuits. Each CAM array including an array of core cells provides, through its encoder, hit and match address signals resulting from a search operation in response to a clock signal. Each match address transfer circuit transfers the match address signal to the common bus, in response to a self-timed signal, the hit signal and a propagation-in hit signal provided from an upstream CAM chip, so that more than one CAM chip is prevented from providing the match address signal to the common bus simultaneously. Each hit propagation circuit provides a propagation-out hit signal to a downstream CAM chip, in response to the self-timed signal, the hit signal and the propagation-in hit signal from the upstream CAM chip, so that a hit signal is propagated from an upstream CAM chip to a downstream CAM chip. Each CAM chip may include an extra row for providing a modelmiss signal or a modelhit signal which is used for a generating self-timed signal. Each word may be divided into two halves and two match lines of the two halves are coupled by a logic circuit. The system may also observe a multiple match status and the highest priority chip indicating a match.

The APV25 0.25 /spl mu/m CMOS readout chip for the CMS tracker

Abstract: The APV25 is a chip designed for readout of silicon microstrips in the CMS tracker at the CERN Large Hadron Collider. It is the first major chip for a high energy physics experiment to exploit a modern commercial 0.25 /spl mu/m CMOS technology. Experimental characterisation of the circuit shows excellent performance before and after irradiation. Automated probe testing of many chips has demonstrated a very high yield. A summary of the design, detailed results from measurements, and probe testing results are presented.

Transmission using an antenna array in a CDMA communication system

Abstract: The invention provides for transmission and reception of a data signal using a plurality of transmitting antennas. Each antenna transmits a different pilot signal having a pseudo random chip code sequence. A receiver filters each transmitted pilot using that pilot's chip code. The filtered pilots are weighted and combined. Each pilot signal's weight is adaptively adjusted in part on a signal quality of the combined signal. A data signal is transmitted such that different spread spectrum versions of the data signal are transmitted from each transmitting antenna. Each version having a different chip code identifier. Upon reception, each version is filtered with its associated chip code. The filtered versions are weighted in accordance with the adjusted weights associated with the pilot signal of the respective antenna.

Multiuser detector for variable spreading factors

Abstract: A plurality of communication signals have differing spreading codes. Each communication has an associated code comprising chips. For each chip of each communication, a vector of that chip convolved with an impulse response is produced. For each communication, support blocks comprising the chip vectors are produced. A number of the chip vectors in a support block is based on that communication's spreading factor. A system response matrix is assembled. The system response matrix has symbol sub-matrices. Each symbol sub-matrix comprises a support block from each communication. Data of the communications is detected using the symbol response matrix.