Showing papers on "Chip published in 2008"

An integrated software system for analyzing ChIP-chip and ChIP-seq data.

Abstract: We present CisGenome, a software system for analyzing genome-wide chromatin immunoprecipitation (ChIP) data. CisGenome is designed to meet all basic needs of ChIP data analyses, including visualization, data normalization, peak detection, false discovery rate computation, gene-peak association, and sequence and motif analysis. In addition to implementing previously published ChIP-microarray (ChIP-chip) analysis methods, the software contains statistical methods designed specifically for ChlP sequencing (ChIP-seq) data obtained by coupling ChIP with massively parallel sequencing. The modular design of CisGenome enables it to support interactive analyses through a graphic user interface as well as customized batch-mode computation for advanced data mining. A built-in browser allows visualization of array images, signals, gene structure, conservation, and DNA sequence and motif information. We demonstrate the use of these tools by a comparative analysis of ChIP-chip and ChIP-seq data for the transcription factor NRSF/REST, a study of ChIP-seq analysis with or without a negative control sample, and an analysis of a new motif in Nanog- and Sox2-binding regions.

Novel Low-Density Signature for Synchronous CDMA Systems Over AWGN Channel

Abstract: Novel low-density signature (LDS) structure is proposed for transmission and detection of symbol-synchronous communication over memoryless Gaussian channel. Given N as the processing gain, under this new arrangement, users' symbols are spread over N chips but virtually only dv < N chips that contain nonzero-values. The spread symbol is then so uniquely interleaved as the sampled, at chip rate, received signal contains the contribution from only dc < K number of users, where K denotes the total number of users in the system. Furthermore, a near-optimum chip-level iterative soft-in-soft-out (SISO) multiuser decoding (MUD), which is based on message passing algorithm (MPA) technique, is proposed to approximate optimum detection by efficiently exploiting the LDS structure. Given beta = K/N as the system loading, our simulation suggested that the proposed system alongside the proposed detection technique, in AWGN channel, can achieve an overall performance that is close to single-user performance, even when the system has 200% loading, i.e., when beta = 2. Its robustness against near-far effect and its performance behavior that is very similar to optimum detection are demonstrated in this paper. In addition, the complexity required for detection is now exponential to dc instead of K as in conventional code division multiple access (CDMA) structure employing optimum multiuser detector.

Spread Spectrum Systems with Commercial Applications

Abstract: From the Publisher: The first spread spectrum challenge was answered by the original communicator to schedule a time for sending and receiving messages because of heavy "traffic" or the desire to avoid interception. Today, spread spectrum systems are a unique blend of analog and digital technology answering an ever increasing range of military, commercial, and consumer communications, data transmission, message privacy, signal hiding, and position location challenges. For nineteen years telecommunications, electrical, and electronics engineers looking for a thoroughly practical, self-contained guide to this important field have turned here. Now this new edition offers... Complete coverage of the latest commercial applications, including everything from direct sequence versus frequency hopping, operation below ambient noise level, error correction coding, near-far performance, linear signal requirements, and synchronization. A full CDMA guide that features discussion of the number of signals in a bandwidth, frequency division multiplex, time-division multiplex, code division multiple access, receiver sensitivity, multipath rejection, direct sequence, fading rate, and more. A new section on the testing and evaluation of spread spectrum systems, including techniques for monitoring sensitivity, selectivity, jamming margin, synch acquisition, loss of synchronization, S/N ratio versus interference level, process gain, cross correlation, transmitter measurements, and more. Three new appendices covering typical error correction coding integrated circuits; typical integrated circuit frequency synthesizers; and spread spectrum's effect on standard microwave communications links. Continuing the freedom from burdensome mathematical rigor and precedence that made the previous editions of this practical presentation of the technology so popular, the Third Edition is assured of its place as one of the most useful working references for a wide range of engineers.

Embedded wafer level ball grid array (eWLB)

Abstract: The main challenges of today's device packaging are miniaturization, continuously increasing operating frequencies/high data rates, high number of I/Os, reliability, and thermal requirements. One of the major package trends driven by mobile-phone applications is the Wafer Level Ball Grid Array (WLB). Drivers for the implementation of WLB technology are cost reduction, smaller form factor and better electrical performance with respect to high frequency applications. Thin-film WLB technology consists in realizing additional redistribution layers above the passivation of a semiconductor chip using standard thin-film techniques to rearrange peripheral pads on the wafer in an array pattern. A hard limit will be reached with this technology, when the number of I/Os reaches a larger number dian can be fitted on the silicon chip at a given pitch. We introduce Infineon's embedded Wafer Level Ball Grid Array technology, which allows fitting interconnects onto a so-called fan-out area extending the chip area. The core process of this emerging technology is the encapsulation of silicon dice by compression molding. The eWLB technology is a forward-looking development of the WLB technology, upholding the known benefits such as small package dimensions, excellent electrical and thermal performance, and maximum connection density. However, this technology significantly increases the functionality and application spread. Due to eWLB. complex semiconductor chips such as modem and processor chips for applications in mobile communications require a high number of solder connections with standardized contact spacing to be produced with a minimal footprint. At the same time, the packages can be provided with as many solder contacts as needed. The possibility of additional wiring area around the chip proper means that the wafer-level packaging technology also lends itself to new. space-sensitive applications. We demonstrate the capabilities of Infineon's molded embedded Wafer Level Package Technology and show how we extended it towards a Platform Technology. The qualified Platform we introduce here covers currently a range of package sizes up to 8×8mm2 at a ball pitch of 0.5mm. The Qualification Criteria we have applied follow the tests described in JEDEC Standard Number 26-A.

A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations

Abstract: A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 mum CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 muW at 1 Mb/s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and digitize the random circuit offset to create a stable unique digital chip ID code. A thorough statistical analysis is presented in order to explore the ID circuit reliability and stability. Two ID generators with different layout techniques were designed and fabricated to provide a performance comparison of power consumption, ID stability, and ID statistical robustness.

A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB Tansmitter

Abstract: The chip is composed of eight 16-channel front-end blocks, data serializing circuits, a DSP for on-chip spike sorting, digital MUX, encoder, UWB TX, and bias generators The chip operates in one of the two modes In sorting mode, a selected channel is connected to the on-the-fly spike sorting block and the extracted features of the spikes are transmitted for off-chip classification In streaming mode, all the sampled data from the 128 channels are recorded and transmitted without any additional processing

Direct-Referencing Two-Dimensional-Array Digital Microfluidics Using Multilayer Printed Circuit Board

Abstract: Digital (i.e., droplet-based) microfluidics, by the electrowetting-on-dielectric (EWOD) mechanism, has shown great potential for a wide range of applications, such as lab-on-a-chip. While most reported EWOD chips use a series of electrode pads essentially in 1D line pattern designed for specific tasks, the desired universal chips allowing user-reconfigurable paths would require the electrode pads in 2D pattern. However, to electrically access the electrode pads independently, conductive lines need to be fabricated underneath the pads in multiple layers, raising a cost issue particularly for disposable chip applications. In this paper, we report the building of digital microfluidic plates based on a printed circuit board (PCB), in which multilayer electrical access lines were created inexpensively using the mature PCB technology. However, due to its surface topography and roughness and resulting high resistance against droplet movement, the as-fabricated PCB surfaces require high (~500 V) voltages unless coated with or immersed in oil. Our goal is the EWOD operations of droplets not only on oil-covered surfaces but also on dry ones. To meet the varying levels of performances, three types of gradually complex post-PCB microfabrication process are developed and evaluated. By introducing land-grid-array sockets in the packaging, a scalable digital microfluidic system with a reconfigurable and low-cost chip is also demonstrated.

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Abstract: Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.

A 90nm CMOS 60GHz Radio

Abstract: CMOS-based circuits operating at mm-wave frequencies have emerged in the past few years. This paper discusses the integration of a 60GHz CMOS single-chip transmitter and a single- chip receiver using a standard 90nm CMOS technology demonstrating a reliable solution for 60GHz single-chip radio. Proper transistor layout, complete and accurate modeling and optimized parasitic extraction method enabled the robust design of the wideband super-heterodyne architecture to support the entire 57- to-66GHz band. The analog radio front-end is controlled by a serial digital interface and has been co-designed and integrated together with a high-speed digital signal processor including analog-to-digital conversion, high speed PHY signal processing such as frequency-offset compensation, phase tracking, FIR and DFE, to support both advanced OFDM and SCBT modulation scheme. The resulting single-chip solution enables data throughputs exceeding 7Gb/s (QPSK) and 15Gb/s (16QAM) for a total DC power budget of below 200mW in TDD operation. In combination with a low-cost FR4-based packaging technology, it provides a high-performance cost-effective solution for a wide range of high volume consumer electronic applications.

A 77GHz 4-channel automotive radar transceiver in SiGe

Abstract: A fully integrated 4-channel automotive radar transceiver chip, integrated in a 200-GHz SiGe:C production technology, is presented. With a typical transmit power of 2 x +7 dBm at the antenna ports and all functions active, the chip draws a current of about 600 mA from a single 5.5 V supply. The design permits FMCW operation in the 76 to 77 GHz band at chip-backside temperatures from -40degC to +125degC.

VLSI implementation of a neural network memory with several hundreds of neurons

Abstract: We designed an Electronic Neural Network (ENN) memory with 256 neurons on a single chip using a combination of analog and digital VLSI technology plus a custom microfabrication process. Amplifiers with inverting and noninverting outputs are used for the neurons to make inhibitory and excitatory connections. The connections between the individual neurons are provided by amorphous‐silicon resistors which are placed on the CMOS chip in the last fabrication step. This technique allows a very dense packing of the neurons. Electron‐beam direct‐writing is used to pattern the resistors making it easy to change the information stored in the network from one chip to the next.

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

Abstract: An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.

Stack package made of chip scale packages

Abstract: A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Abstract: Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm2.

Design Optimization for Integrated Neural Recording Systems

Abstract: Power and chip area are the most important parameters in designing a neural recording system in vivo. This paper reports a design methodology for an optimized integrated neural recording system. Electrode noise is considered in determining the ADC's resolution to prevent over-design of the ADC, which leads to unnecessary power consumption and chip area. The optimal transconductance and gain of the pre-amplifiers, which minimizes the power-area product of the amplifier, are mathematically derived. A numerical example using actual circuit parameters is shown to demonstrate the design methodology. A tradeoff between the power consumption of the system and the chip area in terms of the multiplexing ratio is investigated and the optimal number of channels per ADC is selected to achieve the minimum power-area product for the entire system. Following the proposed design methodology, a chip has been designed in 0.35 mum CMOS process, with the multiplexing ratio of 16:1, resulting in total chip area of 2.5 mm times 2.0 mm and power consumption of 5.3 mW from plusmn1.65 V.

Design and performance of the 6 GHz waveform digitizing chip DRS4

Abstract: The high demands of modern experiments in fast waveform digitizing led to the development of the DRS4 chip, which is a radiation hard switched capacitor array (SCA) fabricated in a 025 μm CMOS process It is capable to digitize 8+1 input channels at sampling rates up to 6 Giga-samples per second (GSPS) with an individual channel depth of 1024 bins and a effective range of 115 bits A novel cascading scheme allows the combination of several channels or even chips to deliver very deep sampling depths or interleaved sampling with up to 48 GSPS An on-chip PLL ensures high timing accuracy over a wide temperature range The high analog bandwidth of 850 MHz, low power consumption of 40 mW/channel and fast readout time make this chip attractive for many experiments, replacing traditional ADCs and TDCs

A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer

Abstract: A 60-GHz receiver (RX) front-end chip fabricated in 90 nm CMOS process is presented. The RX chip consists of an LNA, a downconversion mixer, and a phase-locked loop synthesizer. The RX chip is capable of generating LO signal from phase-locked synthesizer. The components of the RX chip employ fully differential architecture to avoid influences of parasitic components and operate with low LO signal amplitude. Measured power gain and NF of 22 dB and 8.4 dB were obtained at 61.5 GHz, respectively, and the RX chip receives a radio signal with an on-chip dipole antenna. These results indicate the possibility of realization of a CMOS single-chip 60-GHz transceiver.

Manufacturing method of semiconductor device

Abstract: The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on the first semiconductor chip, and a sealing body are comprised. A first gold bump is connected to the wiring substrate, heating, and injection by pressure welding of the first gold bump is done under normal temperature after that at the hole-like electrode of the first semiconductor chip. Since injection by pressure welding of the second gold bump of the second semiconductor chip is done under normal temperature into the hole-like electrode of the first semiconductor chip and the second semiconductor chip is stacked, the chip-stack can be performed under normal temperature. The chip after the second stage can be stacked in the state where there is no warp in the first stage chip, by this, and the quality and reliability of the semiconductor device (semiconductor package) can be improved.

An Integrated Implantable Stimulator That is Fail-Safe Without Off-Chip Blocking-Capacitors

Abstract: We present a neural stimulator chip with an output stage (electrode driving circuit) that is fail-safe under single-fault conditions without the need for off-chip blocking-capacitors. To miniaturize the stimulator output stage two novel techniques are introduced. The first technique is a new current generator circuit reducing to a single step the translation of the digital input bits into the stimulus current, thus minimizing silicon area and power consumption compared to previous works. The current generator uses voltage-controlled resistors implemented by MOS transistors in the deep triode region. The second technique is a new stimulator output stage circuit with blocking-capacitor safety protection using a high-frequency current-switching (HFCS) technique. Unlike conventional stimulator output stage circuits for implantable functional electrical stimulation (FES) systems which require blocking-capacitors in the microfarad range, our proposed approach allows capacitance reduction to the picofarad range, thus the blocking-capacitors can be integrated on-chip. The prototype four-channel neural stimulator chip was fabricated in XFAB's 1-mum silicon-on-insulator CMOS technology and can operate from a power supply between 5-18 V. The stimulus current is generated by active charging and passive discharging. We obtained recordings of action potentials and a strength-duration curve from the sciatic nerve of a frog with the stimulator chip which demonstrate the HFCS technique. The average power consumption for a typical 1-mA 20-Hz single-channel stimulation using a book electrode, is 200 muW from a 6 V power supply. The silicon area occupation is 0.38 mm2 per channel.

Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

Abstract: The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space * Power) ]. It doubles the throughput performance and performance/watt, and provides >10times improvement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight SPARC cores, each supporting concurrent execution of eight threads for 64 threads total. Each SPARC core has a floating point and graphics unit and an advanced cryptographic unit which provides high enough bandwidth to run the two 10 Gb Ethernet ports encrypted at wire speeds. There is a 4 MB Level2 cache on chip. Each of the four on-chip memory controllers controls two FBDIMM channels. Niagara2 has 503 million transistors on a 342 mm2 die packaged in a flip-chip glass ceramic package with 1831 pins. The chip is built in Texas Instruments' 65 nm 11LM triple-Vt CMOS process. It operates at 1.4 GHz at 1.1 V and consumes 84 W.

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing

Abstract: In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address-event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16times16 has been implemented with programmable kernel size of up to 16times16. The chip has been fabricated in a standard 0.35 mum complimentary metal-oxide-semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2D arrays of such chips. Pixel operation exploits low-power mixed analog-digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.

Camera system with multiple pixel arrays on a chip

Abstract: A camera system uses one or more image sensor IC chips each having multiple pixel arrays on the same semiconductor substrate (i.e., “multiple pixel arrays on a chip”). In one embodiment, such a camera system includes: (a) optical components that create multiple images in close physical proximity of each other (e.g., within a few millimeters or centimeters); and (b) a single sensor substrate (“chip”) containing multiple 2-dimensional pixel arrays that are aligned to capture these multiple images, so as to convert the multiple images into electrical signal. The pixel arrays can be manufactured using a CCD or a CMOS compatible process. For manufacturing reasons, such a chip is typically two centimeters or less on a side. However, large chips can also be made. Optional electronic components for further signal processing of the captured images may be formed either on the sensor chip (i.e., in a “system-on-a-chip” implementation), or in a separate back-end application specific integrated circuit (ASIC). In addition, digital storage components, display elements, and wired or wireless communication links may also be included in any suitable combination to allow review and further processing of the captured images.

Cool Chips: Opportunities and Implications for Power and Thermal Management

Abstract: Alongside innovative device, circuit, and microarchitecture level techniques to alleviate power and thermal problems in nanoscale CMOS-based integrated circuits (ICs), chip cooling could be an effective knob for power and thermal management. This paper analyzes IC cooling while focusing on the practical temperature range of operation. Comprehensive analyses of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies are presented. Unlike all previous works, this analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While chip cooling always gives performance gain at the device and circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and an associated cost that may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots.

A Programmable SIMD Vision Chip for Real-Time Vision Applications

Abstract: A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 times 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 times 16 PE array is fabricated by the 0.18 standard CMOS process. It has a pixel size of 30 mum times 40 mum and 8.72 mum W power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

A Low-Power Fully Implantable 15-Channel Retinal Stimulator Chip

Abstract: Retinal prostheses are being developed around the world in hopes of restoring useful vision for patients suffering from certain types of diseases like age-related macular degeneration (AMD) and retinitis pigmentosa. The central component of an electrical retinal prosthesis is a wirelessly powered and driven stimulator chip. The chip receives commands from the outside and outputs biphasic current pulses to an electrode array placed in the retina that stimulate the remaining retinal neurons. The chip contains 30\thinspace000 transistors in a 0.5 mum technology (two-poly three-metal, 2P3M), occupies an area of 2.3 mm x 2.3 mm, and excluding the current sources consumes less than 2 mW of power. The chip is powered inductively via a 125 kHz power signal which is rectified to generate a plusmn2.5nV supply. The data signal is transmitted as an amplitude shift keyed (ASK) signal on a 13.56 MHz carrier. The data rate can be varied from 25 to 714 kHz and the symbol (0 or 1) is encoded as the pulse width of the data signal. A self-biased feedback-loop-based single-to-differential converter restores the signal to full rail levels. Clock and data recovery is performed by a self-biased low-power inverter-based delay-locked loop (DLL). The chip can receive four commands, and each command is 16 bits long. The current amplitude, pulse duration, and inter-pulse duration can be programmed by using the four commands.

A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip

Abstract: In order to face the inherent complexity of new radio access technologies and to address the development of multi-standard devices, an innovative reconfigurable baseband architecture based on a distributed control and communication framework is proposed. This architecture is tailored to the possibilities and limitations of next-generation CMOS nanotechnologies in terms of leakage and timing closure. A combination of technology features, message passing control model, network-on-chip, asynchronous implementation, clocking and power reduction policies is used. The 79.5 mm 2 chip was manufactured in a 130 nm CMOS technology and is integrated in a prototyping platform to perform real-time experimentation of advanced MIMO OFDM based telecom techniques. It is composed of 23 functional units, such as computing intensive IPs, channel coding blocks, programmable DMA engines, an ARM946ES core, and an Ethernet interface. These elements are interconnected via an asynchronous layered Network-on-Chip using an interface that controls the communication and configuration parameters during application scheduling.

Printed circuit board and method for manufacturing printed circuit board

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Characterisation of chip formation during orthogonal cutting of titanium alloy Ti–6Al–4V

Abstract: The mechanics of segmented chip formation during orthogonal cutting of titanium alloy Ti–6Al–4V are studied in detail with the aid of high speed imaging of the chip formation zone. Cutting speeds from 4 to 120 m/min and feeds of 0.05, 0.075 and 0.1 mm were used. Segmented chip formation was observed throughout and detailed measurements of recorded video sequences examined the deformation within chip segments and within the shear bands separating the chip segments. The chip segment geometry was characterised in terms of the cutting parameters given above and the shear strains both within the chip segments and the shear bands were analysed. A thermal model of the process was developed and average temperatures for the primary shear zone and for the tool rake face were calculated.

A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip

Abstract: In order to face the inherent complexity of new radio access technologies and to address the development of multi-standard devices, an innovative reconfigurable baseband architecture based on a distributed control and communication framework is proposed. This architecture is tailored to the possibilities and limitations of next-generation CMOS nanotechnologies in terms of leakage and timing closure. A combination of technology features, message passing control model, network-on-chip, asynchronous implementation, clocking and power reduction policies is used. The 79.5 chip was manufactured in a 130 nm CMOS technology and is integrated in a prototyping platform to perform real-time experimentation of advanced MIMO OFDM based telecom techniques. It is composed of 23 functional units, such as computing intensive IPs, channel coding blocks, programmable DMA engines, an ARM946ES core, and an Ethernet interface. These elements are interconnected via an asynchronous layered network-on-chip using an interface that controls the communication and configuration parameters during application scheduling.

Thermal Management for 3D Processors via Task Scheduling

Abstract: A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and reduce the delay of interconnects across the dies. However, a major challenge in 3D technology is the increased power density which brings the concern of heat dissipation within the processor. High temperatures trigger voltage and frequency throttlings in hardware which degrade the chip performance. Moreover, high temperatures impair the processorpsilas reliability and reduce its lifetime. To alleviate this problem, we propose in this paper an OS-level scheduling algorithm that performs thermal-aware task scheduling on a 3D chip. Our algorithm leverages the inherent thermal variations within and across different tasks, and schedules them to keep the chip temperature low. We observed that vertically adjacent dies have strong thermal correlations, and the scheduler should consider them jointly. Our proposed algorithm can remove on average 54% of hardware DTMs and result in 7.2% performance improvement over the base case.