Showing papers on "Chip published in 2010"

Chip coated light emitting diode package and manufacturing method thereof

Abstract: A chip coated LED package and a manufacturing method thereof. The chip coated LED package includes a light emitting chip composed of a chip die-attached on a submount and a resin layer uniformly covering an outer surface of the chip die. The chip coated LED package also includes an electrode part electrically connected by metal wires with at least one bump ball exposed through an upper surface of the resin layer. The chip coated LED package further includes a package body having the electrode part and the light emitting chip mounted thereon. The invention improves light efficiency by preventing difference in color temperature according to irradiation angles, increases a yield, miniaturizes the package, and accommodates mass production.

Application of the DRS chip for fast waveform digitizing

Abstract: The high demands of modern experiments in fast waveform digitizing led to the development of a whole family of switched capacitor arrays (SCA), called the Domino Ring Sampler (DRS). The most recent version, DRS4, is produced in a radiation hard 0.25 μm CMOS process, and is capable of digitizing 9 differential input channels at sampling rates of up to 6 Giga-samples per second (GSPS) with an analogue bandwidth of 950 MHz (−3 dB). The channel depth can be configured between 1024 and 8192 cells, and the signal-to-noise ratio allows a resolution equivalent to more than 11 bits. Using an interleaved sampling technique, sampling rates up to 48 GSPS are possible. Compared with the previous versions, the DRS4 chip contains several improvements such as an on-chip PLL for sampling-frequency stabilization and various mechanisms to reduce the read out dead-time. The high bandwidth, low power consumption and short readout time make this chip attractive for many experiments, replacing traditional ADCs and TDCs. This includes time-of-flight detectors, cosmic gamma ray observatories, PET scanners and industrial applications.

Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Abstract: A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.

Integrated circuit chip using top post-passivation technology and bottom structure technology

Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

Abstract: This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18- μm CMOS process with analog options, the 1.1-mm2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -6 dBm and a sensing inaccuracy of ±0.8° C (3 σ inaccuracy) over operating temperature range from -20°C to 30°C with one-point calibration.

Comparison of the chip area usage of 2-level and 3-level voltage source converter topologies

Abstract: In the low voltage converter range, 3-phase 3-level VSC topologies are not wide spread in industry because of the increased part count and higher costs, although they are more efficient for higher switching frequencies. In this paper an alternative 3-level topology referred to as T-type is presented, which is very high efficient for medium switching frequencies (4–20 kHz). Additionally, it is shown that the total silicon chip area of a 3-level topology can be lower than in a 2-level topology since the losses are distributed over more components leading to only a small increase in the junction temperature. This allows for the design of a chip area and cost optimized 3-level bridge leg module for the mass market.

Approximate logic synthesis for error tolerant applications

Abstract: Error tolerance formally captures the notion that -- for a wide variety of applications including audio, video, graphics, and wireless communications -- a defective chip that produces erroneous values at its outputs may be acceptable, provided the errors are of certain types and their severities are within application-specified thresholds. All previous research on error tolerance has focused on identifying such defective but acceptable chips during post-fabrication testing to improve yield. In this paper, we explore a completely new approach to exploit error tolerance based on the following observation: If certain deviations from the nominal output values are acceptable, then we can exploit this flexibility during circuit design to reduce circuit area and delay as well as to increase yield. The specific metric of error tolerance we focus on is error rate, i.e., how often the circuit produces erroneous outputs. We propose a new logic synthesis approach for the new problem of identifying how to exploit a given error rate threshold to maximally reduce the area of the synthesized circuit. Experiment results show that for an error rate threshold within 1%, our approach provides 9.43% literal reductions on average for all the benchmarks that we target.

Wavelength Division Multiplexing Based Photonic Integrated Circuits on Silicon-on-Insulator Platform

Abstract: We review recent advances in the development of silicon photonic integrated circuits for high-speed and high-capacity interconnect applications. We present detailed design, fabrication, and characterization of a silicon integrated chip based on wavelength division multiplexing. In such a chip, an array of eight high-speed silicon optical modulators is monolithically integrated with a silicon-based demultiplexer and a multiplexer. We demonstrate that each optical channel operates at 25 Gb/s. Our measurements suggest the integrated chip is capable of transmitting data at an aggregate rate of 200 Gb/s. This represents a key milestone on the way for fabricating terabit per second transceiver chips to meet the demand of future terascale computing.

Horizontal correlation analysis on exponentiation

Abstract: We introduce in this paper a technique in which we apply correlation analysis using only one execution power curve during an exponentiation to recover the whole secret exponent manipulated by the chip. As in the Big Mac attack from Walter, longer keys may facilitate this analysis and success will depend on the arithmetic coprocessor characteristics. We present the theory of the attack with some practical successful results on an embedded device and analyze the efficiency of classical countermeasures with respect to our attack. Our technique, which uses a single exponentiation curve, cannot be prevented by exponent blinding. Also, contrarily to the Big Mac attack, it applies even in the case of regular implementations such as the square and multiply always or the Montgomery ladder. We also point out that DSA and Diffie-Hellman exponentiations are no longer immune against CPA. Then we discuss the efficiency of known countermeasures, and we finally present some new ones.

A Floating-Gate-Based Field-Programmable Analog Array

Abstract: A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 × 3 mm2 in 0.35-μm CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (> 9 b of FG voltage) and speed (≈ 20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are presented.

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

Abstract: Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.

High-Performance Modulators and Switches for Silicon Photonic Networks-on-Chip

Abstract: The stringent on- and off-chip communications demands of future-generation chip multiprocessors require innovative and potentially disruptive technology solutions, such as chip-scale photonic transmission systems. A space-switched, wavelength-parallel photonic network-on-chip has been shown to equip users with high-bandwidth, low-latency links in an energy-efficient manner. Here, experimental measurements on fabricated silicon photonic devices verify a large set of the components needed to construct these networks. The proposed system architecture is reviewed to motivate the demanding performance requirements of the components. Then, systems-level investigations are delineated for multiwavelength electrooptic modulators and photonic switching elements arranged in 1 × 2, 2 × 2, and 4 × 4 formations. Compact (~10 ?m), high-speed (4 Gb/s) modulators, having a large degree of channel scalability (four channels demonstrated), are demonstrated with excellent data integrity (bit error rates (BERs) 10 dB). Data integrity is also verified for the switches (BERs < 10-12) with power penalty measurements amid dynamic operation. These network component demonstrations verify the feasibility of the proposed system architecture, while previous works have verified its efficacy.

Embedded Wafer Level Ball Grid Array (eWLB)

Abstract: The main challenges of today's device packaging are miniaturization, continuously increasing operating frequencies/high data rates, high number of I/Os, reliability, and thermal requirements One of the major package trends driven by mobile-phone applications is the Wafer Level Ball Grid Array (WLB) Drivers for the implementation of WLB technology are cost reduction, smaller form factor and better electrical performance with respect to high frequency applications Thin-film WLB technology consists in realizing additional redistribution layers above the passivation of a semiconductor chip using standard thin-film techniques to rearrange peripheral pads on the wafer in an array pattern A hard limit will be reached with this technology, when the number of I/Os reaches a larger number dian can be fitted on the silicon chip at a given pitch We introduce Infineon's embedded Wafer Level Ball Grid Array technology, which allows fitting interconnects onto a so-called fan-out area extending the chip area The core process of this emerging technology is the encapsulation of silicon dice by compression molding The eWLB technology is a forward-looking development of the WLB technology, upholding the known benefits such as small package dimensions, excellent electrical and thermal performance, and maximum connection density However, this technology significantly increases the functionality and application spread Due to eWLB complex semiconductor chips such as modem and processor chips for applications in mobile communications require a high number of solder connections with standardized contact spacing to be produced with a minimal footprint At the same time, the packages can be provided with as many solder contacts as needed The possibility of additional wiring area around the chip proper means that the wafer-level packaging technology also lends itself to new space-sensitive applications We demonstrate the capabilities of Infineon's molded embedded Wafer Level Package Technology and show how we extended it towards a Platform Technology The qualified Platform we introduce here covers currently a range of package sizes up to 8×8mm2 at a ball pitch of 05mm The Qualification Criteria we have applied follow the tests described in JEDEC Standard Number 26-A

High-Sensitivity Software-Configurable 5.8-GHz Radar Sensor Receiver Chip in 0.13- $\mu$ m CMOS for Noncontact Vital Sign Detection

Abstract: In this paper, analyses on sensitivity and link budget have been presented to guide the design of high-sensitivity noncontact vital sign detector. Important design issues such as flicker noise, baseband bandwidth, and gain budget have been discussed with practical considerations of analog-to-digital interface and signal processing methods in noncontact vital sign detection. Based on the analyses, a direct-conversion 5.8-GHz radar sensor chip with 1-GHz bandwidth was designed and fabricated. This radar sensor chip is software configurable to set the operation point and detection range for optimal performance. It integrates all the analog functions on-chip so that the output can be directly sampled for digital signal processing. Measurement results show that the fabricated chip has a sensitivity of better than -101 dBm for ideal detection in the absence of random body movement. Experiments have been performed successfully in laboratory environment to detect the vital signs of human subjects.

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

Abstract: A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.

An 8 $\,\times\,$ 8 InP Monolithic Tunable Optical Router (MOTOR) Packet Forwarding Chip

Abstract: In this paper, we demonstrate single-channel operation of the first InP monolithic tunable optical router (MOTOR) chip designed to function as the packet forwarding engine of an all-optical router. The device has eight-input and eight-output ports and is capable of 40-Gb/s operation per port with bit-error rates below 1E-9. MOTOR integrates eight wavelength-tunable differential Mach-Zehnder semiconductor optical amplifier (SOA) wavelength converters with preamplifiers and a passive 8 × 8 arrayed-waveguide grating router. Each wavelength converter employs a widely tunable sampled-grating distributed Bragg reflector (DBR) laser for efficient wavelength switching across the C band and other functions required for 40-Gb/s wavelength conversion. Active and passive regions of the chip are defined through a robust quantum well intermixing process to optimize the gain in the wavelength converters and minimize the propagation losses in passive sections of the chip. The device is one of the most complex photonic integrated circuits (PICs) reported to date, with dimensions of 4.25 mm × 14.5 mm and more than 200 functional elements integrated on-chip. We demonstrate single-channel wavelength conversion and channel switching with this device using 231 - 1 pseudorandom bit sequence (PRBS) data at 40 Gb/s. A power penalty as low as 4.5 dB was achieved with less than 2-W drive power per channel.

The trouble with multi-core

Abstract: Designers now accept that although transistors will still get smaller and more numerous on each chip, they aren't going to operate faster than they do toady.And if you tried to incorporate all those transistors into one giant microprocessor, you might well end up with a device that couldn't compute any faster than the chip it was replacing, which explains the shift to assembling them into multiple microprocessor cores instead.

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme

Abstract: A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 x 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.

Thermal-Aware Task Scheduling for 3D Multicore Processors

Abstract: A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and reduce the delay of interconnects significantly across the dies. However, a major challenge in 3D technology is the increased power density, which gives rise to the concern of heat dissipation within the processor. High temperatures trigger voltage and frequency throttlings in hardware, which degrade the chip performance. Moreover, high temperatures impair the processor's reliability and reduce its lifetime. To alleviate this problem, we propose in this paper an OS-level scheduling algorithm that performs thermal-aware task scheduling on a 3D chip. Our algorithm leverages the inherent thermal variations within and across different tasks, and schedules them to keep the chip temperature low. We observed that vertically adjacent dies have strong thermal correlations and the scheduler should consider them jointly. Compared with other intuitive algorithms such as a Random and a Round-Robin algorithm, our proposed algorithm brings lower peak temperature and average temperature on-chip. Moreover, it can remove, on average, 46 percent of thermal emergency time and result in 5.11 percent (4.78 percent) performance improvement over the base case on thermally homogeneous (heterogeneous) floorplans.

A method for the identification of the specific force coefficients for mechanistic milling simulation

Abstract: This paper presents a new method to obtain the specific cutting coefficients needed to predict the milling forces using a mechanistic model of the process. The specific coefficients depend on the tool–material couple, the cutting conditions and the geometry of the tool, being usually calculated applying the force model in an inverse way. The most used inverse method is based on the calculation of the average cutting force per revolution values measured in a series of slot machining tests at different feed rates. In this research work, the inverse method is applied using the instantaneous cutting force values, solving the equations system by a constrained least squares fitting method. Furthermore, the cutting force and specific cutting coefficients relation with rake angle and chip thickness is analysed. The results are validated by the comparison of the simulations and experiments in orthogonal cutting test, showing the advantages of using the new method.

The digital silicon photomultiplier — System architecture and performance evaluation

Abstract: In this paper we present the first fully digital implementation of the Silicon Photomultiplier The chip design is based on the technology demonstrator chip presented in [3] The new sensor represents a self-contained detector including a JTAG controller for configuration and test, single-ended and differential clock and test input signals, an integrated acquisition controller and two serial data outputs The sensor is based on a single photon avalanche photodiode (SPAD) technology integrated in a standard CMOS process flow Photons are detected directly by sensing the voltage at the SPAD terminal using a dedicated cell electronics block next to each diode This block also contains active quenching and recharge circuits as well as a one bit memory for the selective activation of individual detector cells A balanced trigger network is used to propagate the trigger signal from all cells to the two integrated time-to-digital converters Photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise The resulting data packets are transferred to the readout system through a serial data interface In this paper, we discuss the new sensor architecture and evaluate its performance

VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory

Abstract: Bit-error correction is crucial for realizing cost-effective and reliable NAND Flash-memory-based storage systems. In this paper, low-power and high-throughput error-correction circuits have been developed for multilevel cell (MLC) nand Flash memories. The developed circuits employ the Bose-Chaudhuri-Hocquenghem code to correct multiple random bit errors. The error-correcting codes for them are designed based on the bit-error characteristics of MLC NAND Flash memories for solid-state drives. To trade the code rate, circuit complexity, and power consumption, three error-correcting architectures, named as whole-page, sector-pipelined, and multistrip ones, are proposed. The VLSI design applies both algorithmic and architectural-level optimizations that include parallel algorithm transformation, resource sharing, and time multiplexing. The chip area, power consumption, and throughput results for these three architectures are presented.

Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application

Abstract: A compact STT(Spin-Transfer Torque)-RAM with a 14F2 cell was integrated using modified DRAM processes at the 54nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of STT-RAM, we estimate that the unit cell dimension below 30nm can be smaller than 8F2.

Cantilever couplers for intra-chip coupling to photonic integrated circuits

Abstract: Development of Integrated Optical Circuits depends greatly on progress in coupling light to and between chip devices. Exemplary disclosed embodiments provide a system and method of fabricating couplers for optical chips that may allow for access to devices on the entire chip surface. Cantilever couplers comprising optical waveguides are deflected out-of-plane creating access to remote portions of devices. An exemplary system and method may provide waveguides with tunable angles of deflection creating greater flexibility in optical coupling options.

Active chip on carrier or laminated chip having microelectronic element embedded therein

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

LED flip-chip package structure with dummy bumps

Abstract: A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip.

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

Abstract: A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of , where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of at a 1-MHz offset frequency. The chip core occupies 0.37 and the measured power consumption is 8.1 mA from a 1.2-V power supply.

Neural Dynamics in Reconfigurable Silicon

Abstract: A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm2.

A 74.8 mW Soft-Output Detector IC for 8 $\,\times\,$ 8 Spatial-Multiplexing MIMO Communications

Abstract: In this paper, VLSI implementation of a configurable, soft-output MIMO detector is presented. The proposed chip can support up to 8 × 8 64-QAM spatial multiplexing MIMO communications, which surpasses all reported MIMO detector ICs in antenna number and modulation order. Moreover, this chip provides configurable antenna number from 2 × 2 up to 8 × 8 and modulation order from QPSK to 64-QAM. Its outputs include bit-wise log likelihood ratios (LLRs) and a candidate list, making it compatible with powerful soft-input channel decoders and iterative decoding system. The MIMO detector adopts a novel sphere decoding algorithm with high decoding efficiency and superior error rate performance, called modified best-first with fast descent (MBF-FD). Moreover, a low-power pipelined quad-dual-heap (quad-DEAP) circuit for efficient node pool management and several circuit techniques are implemented in this chip. When this chip is configured as 4 × 4 64-QAM and 8 × 8 64-QAM soft-output MIMO detectors, it achieves average throughputs of 431.8 Mbps and 428.8 Mbps with only 58.2 mW and 74.8 mW respective power consumption and reaches 10-5 coded bit error rate (BER) at signal-to-noise ratio (SNR) of 24.2 dB and 22.6 dB, respectively.