Showing papers on "Chip published in 2013"

Compact spectrometer based on a disordered photonic chip

Abstract: Light scattering in disordered media has been studied extensively due to its prevalence in natural and artificial systems. In photonics most of the research has focused on understanding and mitigating the effects of scattering, which are often detrimental. For certain applications, however, intentionally introducing disorder can actually improve device performance, as in photovoltaics. Here, we demonstrate a spectrometer based on multiple light scattering in a silicon-on-insulator chip featuring a random structure. The probe signal diffuses through the chip generating wavelength-dependent speckle patterns, which are detected and used to recover the input spectrum after calibration. A spectral resolution of 0.75 nm at a wavelength of 1,500 nm in a 25-μm-radius structure is achieved. Such a compact, high-resolution spectrometer is well suited for lab-on-a-chip spectroscopy applications. A miniature spectrometer has been developed that employs light scattering in a photonic chip with a random structure. It generates wavelength-dependent speckle patterns, which are detected and analysed to recover the spectrum of the input signal. It has a resolution of 0.75 nm in the 1,500 nm wavelength region.

Chip on board based highly integrated imager

Abstract: An apparatus for use in decoding a bar code symbol may include an image sensor integrated circuit having a plurality of pixels, timing and control circuitry for controlling an image sensor, gain circuitry for controlling gain, and analog to digital conversion circuitry for conversion of an analog signal to a digital signal. The apparatus may also include a PCB for mounting the image sensor integrated circuit and light source bank. The connection between the image sensor integrated circuit and/or light source bank and the PCB characterized by a plurality of wires connecting a plurality of bond pads and a plurality of contact pads, where the wires, bond pads, and contact pads provide electrical input/output and mechanical connections between the image sensor integrated circuit and the PCB. The apparatus may be operative for processing image signals generated by the image sensor integrated circuit for attempting to decode the bar code symbol.

Laser scanning code symbol reading system employing programmable decode time-window filtering

Abstract: A method and system for reading code symbols using a code symbol reading system having a programmable decode time-window filter mode of operation During this mode of operation, only decoded code symbols that have been scanned within a selected (eg central) portion of the laser scan line field are processed according to a special decode time-window filtering function In particular, if the decoded bar code symbol is a programming-type bar code symbol, then the system controller applies the function represented by the programming-type bar code symbol; and if the decoded bar code symbol is a non-programming-type bar code symbol, then the system controller either transmits symbol character data associated therewith to the host system or stores the symbol character data within memory aboard the bar code symbol reading system

System and Method for Reading Code Symbols Using a Variable Field of View

Abstract: A system and method are presented for improving the performance of full range code scanners. A distance detection module determines the distance of the code symbol from the code symbol reader. In response to the detected distance, the sweep angle of the scanning element is changed to ensure that the code symbol is within the code symbol reader's field of view. The sweep angle is larger when the code symbol is in the near range, and smaller when the code symbol is in the far range.

Microwave synthesizer using an on-chip Brillouin oscillator

Abstract: Low-phase-noise microwave oscillators are important to a wide range of subjects, including communications, radar and metrology. Photonic-based microwave-wave sources now provide record, close-to-carrier phase-noise performance, and compact sources using microcavities are available commercially. Photonics-based solutions address a challenging scaling problem in electronics, increasing attenuation with frequency. A second scaling challenge, however, is to maintain low phase noise in reduced form factor and even integrated systems. On this second front, there has been remarkable progress in the area of microcavity devices with large storage time (high optical quality factor). Here we report generation of highly coherent microwaves using a chip-based device that derives stability from high optical quality factor. The device has a record low electronic white-phase-noise floor for a microcavity-based oscillator and is used as the optical, voltage-controlled oscillator in the first demonstration of a photonic-based, microwave frequency synthesizer. The synthesizer performance is comparable to mid-range commercial devices.

Package-on-package based integrated circuit chip imager

Abstract: An apparatus for use in decoding a bar code symbol includes a first integrated circuit chip with a wafer level camera, at least one light source, and a plurality of contact pads on a surface of the chip and a second integrated circuit chip with a processor, memory, plurality of contact pads on a surface of the chip, and plurality of contact pads on another surface of the chip. The apparatus includes a PCB having a plurality of contact pads disposed on at least one surface of the PCB and wherein the first and second integrated circuit chips are vertically stacked on the PCB and the plurality of contact pads on the first and second integrated circuit chips interface with the contact pads of the second integrated circuit chip and PCB. The apparatus is operative for processing image signals generated by the WLC for attempting to decode the bar code symbol.

The Medipix3RX: a high resolution, zero dead-time pixel detector readout chip allowing spectroscopic imaging

Abstract: The Medipix3 chips have been designed to permit spectroscopic imaging in highly segmented hybrid pixel detectors. Spectral degradation due to charge sharing in the sensor has been addressed by means of an architecture in which adjacent pixels communicate in the analog and digital domains on an event-by-event basis to reconstruct the deposited charge in a neighbourhood prior to the assignation of the hit to a single pixel. The Medipix3RX chip architecture is presented. The first results for the characterization of the chip with 300 μm thick Si sensors are given. ~ 72e− r.m.s. noise and ~ 40e− r.m.s. of threshold dispersion after chip equalization have been measured in Single Pixel Mode of operation. The homogeneity of the image in Charge Summing mode is comparable to the Single Pixel Mode image. This demonstrates both modes are suitable for X-ray imaging applications.

Radio-frequency integrated circuit (rfic) chip(s) for providing distributed antenna system functionalities, and related components, systems, and methods

Abstract: Radio-frequency (RF) integrated circuit (RFIC) chip(s) allow for the integration of multiple electronic circuits on a chip to provide distributed antenna system functionalities. RFIC chips are employed in central unit and remote unit components, reducing component cost and size, increasing performance and reliability, while reducing power consumption. The components are also easier to manufacture. The RFIC chip(s) can be employed in distributed antenna systems and components that support RF communications services and/or digital data services.

Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver

Abstract: This paper demonstrates a four-channel transceiver chip for medical ultrasonic imaging, interfacing to the capacitive micromachined ultrasonic transducers (CMUTs). The high-voltage transmitter (Tx) uses a three-level pulse-shaping technique with charge recycling to improve the power efficiency. The design requires minimum off-chip components and is scalable for more channels. The receiver is implemented with a transimpedance amplifier (TIA) topology and is optimized for tradeoffs between noise, bandwidth, and power dissipation. The test chip is characterized with both acoustic and electrical measurements. Comparing the three-level pulser against traditional two-level pulsers, the measured Tx efficiency shows 56%, 50%, and 43% more acoustic power delivery with the same total power dissipation at 2.5, 3.3, and 5.0 MHz, respectively. The CMUT receiver achieves the lowest noise efficiency factor compared with that of the literature (2.1 compared to a previously reported lowest of 3.6, in units of mPA ·√(mW/Hz). In addition, the transceiver chip is tested as a complete system for medical ultrasound imaging applications, in experiments including Tx beamformation, pulse-echo channel response characterization, and ultrasonic Doppler flow rate detection.

Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors

Abstract: It is projected that increasing on-chip integration with technology scaling will lead to the so-called dark silicon era in which more transistors are available on a chip than can be simultaneously powered on. It is conventionally assumed that the dark silicon will be provisioned with heterogeneous resources, for example dedicated hardware accelerators. In this paper we challenge the conventional assumption and build a case for homogeneous dark silicon CMPs that exploit the inherent variations in process parameters that exist in scaled technologies to offer increased performance. Since process variations result in core-to-core variations in power and frequency, the idea is to cherry pick the best subset of cores for an application so as to maximize performance within the power budget. To this end, we propose a polynomial time algorithm for optimal core selection, thread mapping and frequency assignment for a large class of multi-threaded applications. Our experimental results based on the Sniper multi-core simulator show that up to 22% and 30% performance improvement is observed for homogeneous CMPs with 33% and 50% dark silicon, respectively.

Inherent polarization entanglement generated from a monolithic semiconductor chip

Abstract: Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral filtering or post-selection. After splitting the twin-photons immediately after they emerge from the chip, we perform a variety of correlation tests on the photon pairs and show non-classical behaviour in their polarization. Combined with the BRW's versatile architecture our results signify the BRW design as a serious contender on which to build large scale implementations of optical quantum processing devices.

Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloads

Abstract: Chip multiprocessor (CMP) techniques have been implemented in embedded systems due to tremendous computation requirements. Three-dimension (3D) CMP architecture has been studied recently for integrating more functionalities and providing higher performance. The high temperature on chip is a critical issue for the 3D architecture. In this article, we propose an online thermal prediction model for 3D chips. Using this model, we propose novel task scheduling algorithms based on rotation scheduling to reduce the peak temperature on chip. We consider data dependencies, especially inter-iteration dependencies that are not well considered in most of the current thermal-aware task scheduling algorithms. Our simulation results show that our algorithms can efficiently reduce the peak temperature up to 8.1ˆC.

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications

Abstract: High-speed signaling over high density interconnect on organic package substrates or silicon interposers offers an attractive solution to the off-chip bandwidth limitation problem faced in modern digital systems. In this paper, we describe a signaling system co-designed with the interconnect to take advantage of the characteristics of this environment to enable a high-speed, low area, and low-power die to die link. Ground-Referenced Signaling (GRS) is a single-ended signaling system that eliminates the major problems traditionally associated with single-ended design by using the ground plane as the reference and signaling above and below ground. This design employs a novel charge pump driver that additionally eliminates the issue of simultaneous switching noise with data independent current consumption. Silicon measurements from a test chip implementing two 16-lane links, with forwarded clocks, in a standard 28 nm process demonstrate 20 Gb/s operation at 0.54 pJ/bit over 4.5 mm organic substrate channels at a nominal 0.9 V power supply voltage. Timing margins at the receiver are >0.3 UI at a BER of 10-12. We estimate BER 10-25 at the eye center.

Inherent polarization entanglement generated from a monolithic semiconductor chip

Abstract: Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral filtering or post-selection. After splitting the twin-photons immediately after they emerge from the chip, we perform a variety of correlation tests on the photon pairs and show non-classical behaviour in their polarization. Combined with the BRW's versatile architecture our results signify the BRW design as a serious contender on which to build large scale implementations of optical quantum processing devices.

Quantification of the chip segmentation in metal machining: Application to machining the aeronautical aluminium alloy AA2024-T351 with cemented carbide tools WC-Co

Abstract: The chip segmentation process has a significant effect on the cutting force fluctuation during machining which could affect tool vibration and tool wear. This paper deals with a quantitative analysis of the chip segmentation phenomenon in metal machining. The notion of intensity of the phenomenon has been introduced. Various parameters have been proposed for this purpose. These parameters are based on dimensional characteristics of the segmented chip and the strain distribution within the chip. A Finite Element based modelling has been developed to simulate the chip formation process in the case of machining aeronautical aluminium alloy AA2024-T351 with WC-Co based cutting tools. From the simulated chip morphologies, introduced chip segmentation parameters are assessed. The impact of the cutting speed and tool geometry on the chip segmentation intensity is clearly highlighted. The relevance of each parameter is discussed. Cutting force and contact length fluctuations with respect to the cutting speed variation when segmentation occurs are discussed and deeply analysed. A correlation between average cutting force reduction and segmentation intensity when the cutting speed increases as well as between chip formation process and cutting force oscillation has been established thanks to the introduced parameters, showing thus their usefulness.

A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits

Abstract: A digital-domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used in a differential-type 11-bit SAR ADC. It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch as well as the two parasitic capacitances connected in parallel with each of the bridge capacitor and the LSB bank of split-CDAC. The proposed ADC does not require any additional analog circuits for calibration, because it utilizes one of the two split-CDACs to measure the error codes of the other split-CDAC. During the normal A/D conversion step, the 11.5-bit raw SAR code output of ADC is added to the pre-measured error codes to generate the 11-bit calibrated output code. The analog block of the ADC was fabricated in a 0.13- μm CMOS process, and the digital block was implemented in a FPGA. The measured SNDR and SFDR are 61.6 dB (ENOB 9.93 bits) and 78 dB at the Nyquist rate with a 5 kHz sine wave input. INL and DNL are measured to be +0.96/-0.98 LSB, and +0.96/-0.97 LSB, respectively. This work extends the prior work by utilizing an additional 0.5-bit raw SAR code to eliminate the missing code, and by employing a temporal averaging with a FIR LPF to measure the error code reliably in spite of the supply noise.

A 100,000 fps vision sensor with embedded 535GOPS/W 256×256 SIMD processor array

Abstract: A vision chip operating with 1.9pJ/OP efficiency has been fabricated in 0.18μm CMOS. Each of the 256×256 pixel-processors (dimensions 32×32μm), contains 14 binary and 7 analog registers coupled to a photodiode, an arithmetic logic unit, diffusion and asynchronous propagation networks. At the chip's periphery, facilities exist to allow pixel address extraction, analog or digital readout. The chip has been exploited to conduct real-time image processing operations at 100,000fps, locating a closed-shape object from amongst clutter.

1Mb 0.41 µm 2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing

Abstract: This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90nm CMOS technology and mushroom phase-change memory (PCM) process. To ensure reliable search operation with such compact cells, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding, and 2) a clocked self-referenced sensing scheme (CSRSS). The 1Mb chip demonstrates reliable low voltage search operation (VDDmin~750mV) and a match delay of 1.9 ns under nominal operating conditions.

A 76–84-GHz 16-Element Phased-Array Receiver With a Chip-Level Built-In Self-Test System

Abstract: This paper presents a 16-element phased-array receiver for 76-84-GHz applications with built-in self-test (BIST) capabilities. The chip contains an in-phase/quadrature (I/Q) mixer suitable for automotive frequency-modulation continuous-wave radar applications, which is also used as part of the BIST system. The chip achieves 4-bit RF amplitude and phase control, an RF to IF gain of 30-35 dB at 77-84 GHz, I/Q balance of and at 76-84 GHz, and a system noise figure of 18 dB. The on-chip BIST covers the 76-84-GHz range and determines, without any calibration, the amplitude and phase of each channel, a normalized frequency response, and can measure the gain control using RF gain control. System-level considerations are discussed together with extensive results showing the effectiveness of the on-chip BIST as compared with standard S-parameter measurements.

64-kb Hybrid Josephson-CMOS 4 Kelvin RAM With 400 ps Access Time and 12 mW Read Power

Abstract: We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2 niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.

A Transparent Logic Circuit for RFID Tag in a-IGZO TFT Technology

Abstract: This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology. The RFID logic circuit generates 16-bit code programmed in read-only memory. All circuits are implemented in a pseudo-CMOS logic style using transparent a-IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300-nm to 800-nm wavelength. The RFID logic chip generates Manchester-encoded 16-bit data with a 3.2-kHz clock frequency and consumes 170 μW at VDD=6 V. It employs 222 transistors and occupies a chip area of 5.85 mm 2 .

A four-electrode low frequency impedance spectroscopy measurement system using the AD5933 measurement chip

Abstract: This paper presents the design of a four electrode impedance measurement circuit dedicated to bioimpedance embedded applications. It extends the use of the AD5933 measurement chip to allow it to operate in a four electrode configuration in order to limit the effects of the parasitic impedances between the medium under test and the electrodes. The circuit has shown a good measurement accuracy on various test circuits. In association with a four microband electrode system it has been successfully used to characterize small physiological samples (50 μl) with conductivities ranging from 0.14 to 1.2 S m−1. It can be used as an alternative bioimpedance measurement approach for embedded applications operating in the four electrode configuration.

A 260GHz broadband source with 1.1mW continuous-wave radiated power and EIRP of 15.7dBm in 65nm CMOS

Abstract: Terahertz spectroscopy using silicon technology is gaining attraction for future portable and affordable material identification equipment. To do this, a broadband THz radiation source is critical. Unfortunately, the bandwidth of the prior CMOS works is not sufficient. In [1], the 300GHz signal source achieves 4.5% tuning range by changing the coupling among multiple oscillators. In [2], the DAR array has 3% tuning range with radiation capability. Alternative to the continuous device-tuning method, THz time-domain spectroscopy utilizing the broadband spectrum of picosecond pulses is widely used in the optics community [3]. In this paper, a high-power pulse-based sub-millimeter-Wave radiation source using 65nm bulk CMOS technology is reported. The architecture of this transmitter is shown in Fig. 8.2.1, where four differential core oscillator pairs are mutually coupled through four quadrature oscillators. Each core oscillator pair generates 2nd-harmonic signals at 260GHz that are power-combined after radiating through eight on-chip antennas. Four shunt switches, controlled by narrow pulses (width≈45ps) modulate the radiation. The pulses are generated by local digital circuit blocks with programmable repetition rate up to 5GHz. This way, the broadband spectrum of the pulses is upconverted to the carrier frequency of 260GHz. Without modulation, the chip achieves a continuous-wave radiated power of 1.1mW. Under modulation, the measured bandwidth of the source is 24.7GHz, which makes it suitable for many FTIR-based THz spectrometers. In addition, if the switches are modulated by digital data, this chip can also be used as a transmitter for sub-millimeter/THz wireless communications.

Photonic wire biosensor microarray chip and instrumentation with application to serotyping of Escherichia coli isolates

Abstract: A complete photonic wire molecular biosensor microarray chip architecture and supporting instrumentation is described. Chip layouts with 16 and 128 independent sensors have been fabricated and tested, where each sensor can provide an independent molecular binding curve. Each sensor is 50 μm in diameter, and consists of a millimeter long silicon photonic wire waveguide folded into a spiral ring resonator. An array of 128 sensors occupies a 2 × 2 mm2 area on a 6 × 9 mm2 chip. Microfluidic sample delivery channels are fabricated monolithically on the chip. The size and layout of the sensor array is fully compatible with commercial spotting tools designed to independently functionalize fluorescence based biochips. The sensor chips are interrogated using an instrument that delivers sample fluid to the chip and is capable of acquiring up to 128 optical sensor outputs simultaneously and in real time. Coupling light from the sensor chip is accomplished through arrays of sub-wavelength surface grating couplers, and the signals are collected by a fixed two-dimensional detector array. The chip and instrument are designed so that connection of the fluid delivery system and optical alignment are automated, and can be completed in a few seconds with no active user input. This microarray system is used to demonstrate a multiplexed assay for serotyping E. coli bacteria using serospecific polyclonal antibody probe molecules.

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

Abstract: A random intrinsic chip ID generation method using retention fails is implemented in 32 nm SOI embedded DRAM. A dynamic key algorithm employs a unique pair of 4 Kb binary strings for an ID record for secure authentication. These strings are generated by controlling a wordline low voltage to search for a number of fails matching the corresponding challenge numbers. The algorithm further includes field-tolerant authentication by detecting a number of common bits analytically guaranteed for successful recognition, while preventing ID spoofing during the read operation. This results in 100% successful unique ID generation and recognition in two temperature and three voltage conditions per chip for a total of ~ 420 k ID pair comparisons in 266 chips. The analytical model predicts a 99.999% successful recognition rate for 106 parts. Finally, a method to enable a field-tolerant ID using multiple domains will be discussed.

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip

Abstract: The performance of multiprocessor systems, such as chip multiprocessors (CMPs), is determined not only by individual processor performance, but also by how efficiently the processors collaborate with one another. It is the communication architecture that determines the collaboration efficiency on the hardware side. Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultra-high communication bandwidth and low latency to multiprocessor systems. Thermal sensitivity is an intrinsic characteristic of photonic devices used by ONoCs as well as a potential issue. This paper systematically modeled and quantitatively analyzed the thermal effects in ONoCs. We used an 8 × 8 mesh-based ONoC as a case study and evaluated the impacts of thermal effects in the average power efficiency for real MPSoC applications. We revealed three important factors regarding ONoC power efficiency under temperature variations, and proposed several techniques to reduce the temperature sensitivity of ONoCs. These techniques include the optimal initial setting of microresonator resonant wavelength, increasing the 3-dB bandwidth of optical switching elements by parallel coupling multiple microresonators, and the use of passive-routing optical router Crux to minimize the number of switching stages in mesh-based ONoCs. We gave a mathematical analysis of periodically parallel coupling of multiple microresonators and show that the 3-dB bandwidth of optical switching elements can be widened nearly linearly with the ring number. Evaluation results for different real MPSoC applications show that, on the basis of thermal tuning, the optimal device setting improves the average power efficiency by 54% to 1.2 pJ/bit when chip temperature reaches 85 °C. The findings in this paper can help support the further development of this emerging technology.

Control loop management and differential delay correction for vector signaling code communications links

Abstract: Vector signaling code communications systems rely on group transmission of code symbols using multiple signaling channels that may have differing propagation characteristics, resulting in differing received signal levels, waveforms, and symbol arrival times, and thus that should be actively monitored and adjusted to minimize differential signal characteristics. Information obtained during symbol decode may be analyzed to identify channel operational characteristics during normal operation and perform non-disruptive channel adjustments, including per-channel adjustment of sample-and-hold timing to realign code symbol groups. Initialization or start-up adjustment may also be performed using intentionally-transmitted training patterns.

Humidity-to-Frequency Sensor in CMOS Technology With Wireless Readout

Abstract: A remotely powered microsystem for humidity measurement is presented. The core of the active transponder consists of a humidity-to-frequency chip fabricated in a standard complementary metal-oxide-semiconductor (CMOS) technology, which contains both the humidity sensor and the readout circuit. The sensor is constructed using the polyimide passivation layer and the top metal layer available in the technology used. Power and data transmissions, to and from the chip, respectively, use the same pair of inductively coupled coils with a 13.56 MHz carrier. The humidity readout is transmitted by load shift keying to the external circuit. The chip is fabricated with commercial 0.6-μm CMOS technology and occupies an area of 4.8 mm2. The sensor's capacitance exhibited good linearity against relative humidity (RH) levels from 15% to 85%. The normalized sensitivity is 0.073% per %RH at 35°C. The circuit level calibration limited spread from process and mismatch variations to about 10%. The chip has a total power consumption of 1.39 mW. The device has two purposes; either as a stand-alone wireless humidity sensor or to evaluate the hermeticity of packages, such as in biomedical implants.

A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels

Abstract: Delta-Integration, a novel readout method, is introduced in an effort to solve the noise and speed issues impeding the performance of in-cell touch screen panels. In the proposed method, a differential sensing scheme effectively cancels common noise components and locally occurring noise is spatially low-pass filtered. Due to the consequently enhanced Signal- to-Noise Ratio, the proposed scheme is simply implemented by a comparator and a counter only in place of a complex ADC. The comparator is designed to have a `dead-zone' for noise-immune characteristics. In addition, a new global charge amplifier that has much wider bandwidth and higher current-driving capability than the conventional one is proposed for high speed operation. The prototype chip consumes a static power of 1.15 mW and the total chip area without panel loads is 2.5 mm2.

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost

Abstract: Metal-Oxide Resistive Random Access Memory (ReRAM) technology is gaining popularity due to its superior write bandwidth, high density, and low operating power. An ReRAM array structure can be built with three different approaches: a traditional design with a dedicated access transistor (1T1R) or an access diode (1D1R) for each cell, or an intrinsic cross-point structure (0T1R), where the metal-oxide is directly sandwiched between the horizontal and vertical wires. Each of these different structures has its advantages and disadvantages, and it is a complicated process to perform a systematic comparison of delay, energy, area, and cost of one over others for a given cell parameters set and technology. In this paper, we analyze both advantages and disadvantages for ReRAM arrays built in 1T1R, 1D1R, and 0T1R structures. Based on the analysis, we propose a design flow and provides key insights into architectural tradeoffs. We do this in three stages: first, we use a matrix-based mathematical model to determine the optimal array size, read/write bandwidth, and other key characteristics. This acts as input to the second stage to explore the design space of ReRAM banks and the entire chip. Finally, we estimate the chip-level cost using the area, metal layers, pin count, and cooling requirements. Using the proposed model, we also present a case study in which we compare the energy, performance, and area of a 1D1R cross-point design and a 0T1R design, and show that the 1D1R structure is more promising for a cost-driven memory design.