Showing papers on "Chip published in 2019"

A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations

Abstract: Memristors and memristor crossbar arrays have been widely studied for neuromorphic and other in-memory computing applications. To achieve optimal system performance, however, it is essential to integrate memristor crossbars with peripheral and control circuitry. Here, we report a fully functional, hybrid memristor chip in which a passive crossbar array is directly integrated with custom-designed circuits, including a full set of mixed-signal interface blocks and a digital processor for reprogrammable computing. The memristor crossbar array enables online learning and forward and backward vector-matrix operations, while the integrated interface and control circuitry allow mapping of different algorithms on chip. The system supports charge-domain operation to overcome the nonlinear I–V characteristics of memristor devices through pulse width modulation and custom analogue-to-digital converters. The integrated chip offers all the functions required for operational neuromorphic computing hardware. Accordingly, we demonstrate a perceptron network, sparse coding algorithm and principal component analysis with an integrated classification layer using the system. A programmable neuromorphic computing chip based on passive memristor crossbar arrays integrated with analogue and digital components and an on-chip processor enables the implementation of neuromorphic and machine learning algorithms.

An integrated silicon photonic chip platform for continuous-variable quantum key distribution

Abstract: Quantum key distribution (QKD) is a quantum communication technology that promises unconditional communication security. High-performance and cost-effective QKD systems are essential for the establishment of quantum communication networks1–3. By integrating all the optical components (except the laser source) on a silicon photonic chip, we have realized a stable, miniaturized and low-cost system for continuous-variable QKD (CV-QKD) that is compatible with the existing fibre optical communication infrastructure4. Here, the integrated silicon photonic chip is demonstrated for CV-QKD. It implements the widely studied Gaussian-modulated coherent state protocol that encodes continuous distributed information on the quadrature of laser light5,6. Our proof-of-principle chip-based CV-QKD system is capable of producing a secret key rate of 0.14 kbps (under collective attack) over a simulated distance of 100 km in fibre, offering new possibilities for low-cost, scalable and portable quantum networks. A sender and a receiver for continuous-variable quantum key distribution are packed onto separate silicon photonic chips. By using an external 1,550-nm laser, a secret key rate of 0.14 kbps is transmitted over a simulated distance of 100 km in fibre.

Development, Implementation, and Characterization of a 64-Element Dual-Polarized Phased-Array Antenna Module for 28-GHz High-Speed Data Communications

Abstract: Silicon-based millimeter-wave (mm-wave) phased-array technologies are enabling directional wireless data communications at Gb/s speeds. In this paper, we review and discuss the challenges of implementing a multichip phased-array antenna module for mm-wave applications using organic buildup substrate technology. A prototype test vehicle has been fabricated and studied to evaluate the antenna and interconnect performance, dielectric properties, package substrate warpage conditions at different temperatures, chip- and board-level joint process reliability, and thermal management feasibility for cooling. Based on the learning from the test vehicle, an organic-based multilayered phased-array antenna package for 28-GHz mm-wave radio access applications is implemented. The package incorporates 64 dual-polarized antenna elements and features an air cavity common to all antennas. Direct probing measurements on a single-antenna element of the package show over 3 GHz of bandwidth and 3-dBi gain at 28 GHz. A phased-array transceiver module has been developed with the package; the module includes four SiGe BiCMOS ICs attached using flip-chip assembly. Module-level measurements in the TX mode show a 35-dB near-ideal output power increase for 64-element power combining; 64-element radiation pattern measurements are reported with a steering range of ± 50° without tapering in off-boresight directions, and 64-element radiation pattern measurements with tapering show achievement of a sidelobe level lower than −20 dB. The transceiver modules achieved 20.64-Gb/s throughput with 256 QAM and 800-MHz bandwidth in direct over-the-air link measurement results.

System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration

Abstract: A brand new 3D integrated circuit (3DIC) solution, System on Integrated Chips (SoIC^™), has been successfully developed to integrate active and passive chips into a new integrated SoC system to meet ever-increasing market demands on higher computing efficiency, wilder data bandwidth, higher functionality packaging density, lower communication latency, and lower energy consumption per bit data. 3D packaging is challenging and requires overcoming three major challenges - thermal, power delivery, and yield. The SoIC, as industry-first 3D logic-on-logic and memory-on-logic chiplet stacking technology platform, enables the heterogeneous integration (HI) of known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies, all to be integrated in a single, compact new system chip. From external appearance, SoIC looks like a general SoC chip with multiple pre-designed heterogeneous functional chips embedded. As SoIC is fabricated using "front-end" process, it can be holistically integrated into variant "back-end" advanced packaging technology platforms such as flip chip, integrated fan-out (aka InFO), 3DIC, and 2.5D with Si interposer (e.g. CoWoS^™) [1-2] to provide a miniaturized and highly integrated HI SiP for the future HPC, AI, 5G, and edge computing applications. With the innovative bonding scheme, SoIC enables the strong bonding pitch scalability for chip I/O to realize a high density die-to-die interconnects. The bond pitch starts from sub-10 μm rule. Short die-to-die connection of SoIC has the merits of smaller form-factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption comparing to the current industry state-of-the-art packaging solutions. In this paper, we demonstrated for the first time an integration of SoIC chip into InFO_PoP without increasing its form-factor. The SoIC was made on a logic-on-logic stacking to validate the design rules, process maturity, and reliability.

High-speed measurement-device-independent quantum key distribution with integrated silicon photonics

Abstract: Measurement-device-independent quantum key distribution (MDI-QKD) removes all detector side channels and enables secure QKD with an untrusted relay. It is suitable for building a star-type quantum access network, where the complicated and expensive measurement devices are placed in the central untrusted relay and each user requires only a low-cost transmitter, such as an integrated photonic chip. Here, we experimentally demonstrate a 1.25 GHz silicon photonic chip-based MDI-QKD system using polarization encoding. The photonic chip transmitters integrate the necessary encoding components for a standard QKD source. We implement random modulations of polarization states and decoy intensities, and demonstrate a finite-key secret rate of 31 bps over 36 dB channel loss (or 180 km standard fiber). This key rate is higher than state-of-the-art MDI-QKD experiments. The results show that silicon photonic chip-based MDI-QKD, benefiting from miniaturization, low-cost manufacture and compatibility with CMOS microelectronics, is a promising solution for future quantum secure networks.

9.8 A 28GHz 20.3%-Transmitter-Efficiency 1.5°-Phase-Error Beamforming Front-End IC with Embedded Switches and Dual-Vector Variable-Gain Phase Shifters

Abstract: Millimeter-wave beamforming front-end ICs have been studied intensively as the service of 5G wireless communication is scheduled to begin in the near future [1–4]. The ICs include circuit elements such as PAs, LNAs, phase shifters, variable gain blocks, and switches to support antenna arrays for RF/hybrid beamforming. Due to the large number of antennas required for beamforming, the beamforming IC should include as many circuit elements as possible in a chip. The IC also needs high phase- and gain-control resolutions not only for controlling the beams precisely but also for error corrections and calibrations [1]. However, higher-bit controls of the phase and gain as well as high transmitting power increase the chip size in conventional structures, posing a trade-off between them. The front-end IC structure proposed here increases both transmitting power and gain/phase resolutions without increasing either the chip size or the power consumption.

Ghost imaging using a large-scale silicon photonic phased array chip.

Abstract: We experimentally demonstrate the use of a large-scale silicon-photonic optical phased array (OPA) chip as a compact, low-cost, and potentially high-speed light illuminating device for ghost imaging (GI) applications. By driving 128 phase shifters of a newly developed silicon OPA chip using rapidly changing random electrical signals, we successfully retrieve a slit pattern with over 90 resolvable points in one dimension. We then demonstrate 2D imaging capability by sweeping the wavelength. With the potential of integrating high-speed phase modulators, tunable lasers, grating couplers, and CMOS driver circuit on the same silicon platform, this work paves the way towards realizing ultrahigh-speed and low-cost single-chip GI devices.

Nonlinear integrated quantum electro-optic circuits

Abstract: Future quantum computation and networks require scalable monolithic circuits, which incorporate various advanced functionalities on a single physical substrate. Although substantial progress for various applications has already been demonstrated on different platforms, the range of diversified manipulation of photonic states on demand on a single chip has remained limited, especially dynamic time management. Here, we demonstrate an electro-optic device, including photon pair generation, propagation, electro-optical path routing, as well as a voltage-controllable time delay of up to ~12 ps on a single Ti:LiNbO 3 waveguide chip. As an example, we demonstrate Hong-Ou-Mandel interference with a visibility of more than 93 ± 1.8%. Our chip not only enables the deliberate manipulation of photonic states by rotating the polarization but also provides precise time control. Our experiment reveals that we have full flexible control over single-qubit operations by harnessing the complete potential of fast on-chip electro-optic modulation.

High-Density Electrical Recording and Impedance Imaging With a Multi-Modal CMOS Multi-Electrode Array Chip.

Abstract: Multi-electrode arrays, both active or passive, emerged as ideal technologies to unveil intricated electrophysiological dynamics of cells and tissues. Active MEAs, designed using complementary metal oxide semiconductor technology (CMOS), stand over passive devices thanks to the possibility of achieving single-cell resolution, the reduced electrode size, the reduced crosstalk and the higher functionality and portability. Nevertheless, most of the reported CMOS MEA systems mainly rely on a single operational modality, which strongly hampers the applicability range of a single device. This can be a limiting factor considering that most biological and electrophysiological dynamics are often based on the synergy of multiple and complex mechanisms acting from different angles on the same phenomena. Here, we designed a CMOS MEA chip with 16,384 titanium nitride electrodes, 6 independent operational modalities and 1,024 parallel recording channels for neuro-electrophysiological studies. Sixteen independent active areas are patterned on the chip surface forming a 4 × 4 matrix, each one including 1,024 electrodes. Electrodes of four different sizes are present on the chip surface, ranging from 2.5 × 3.5 μm2 up to 11 × 11.0 μm2, with 15 μm pitch. In this paper, we exploited the impedance monitoring and voltage recording modalities not only to monitor the growth and development of primary rat hippocampal neurons, but also to assess their electrophysiological activity over time showing a mean spike amplitude of 144.8 ± 84.6 μV. Fixed frequency (1 kHz) and high sampling rate (30 kHz) impedance measurements were used to evaluate the cellular adhesion and growth on the chip surface. Thanks to the high-density configuration of the electrodes, as well as their dimension and pitch, the chip can appreciate the evolutions of the cell culture morphology starting from the moment of the seeding up to mature culture conditions. The measurements were confirmed by fluorescent staining. The effect of the different electrode sizes on the spike amplitudes and noise were also discussed. The multi-modality of the presented CMOS MEA allows for the simultaneous assessment of different physiological properties of the cultured neurons. Therefore, it can pave the way both to answer complex fundamental neuroscience questions as well as to aid the current drug-development paradigm.

Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

Abstract: This paper investigates design considerations and challenges of integrating on-chip antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a compact front-end receiver for 5G communication systems. Solutions to overcome these challenges are offered and realized in digital 28-nm CMOS. A monolithic on-chip antenna is designed and optimized in the presence of rigorous metal density rules and other back-end-of-the-line (BEoL) challenges of the nanoscale technology. The proposed antenna structure further exploits ground metallization on a PCB board acting as a reflector to increase its radiation efficiency and power gain by 37.3% and 9.8 dB, respectively, while decreasing the silicon area up to 30% compared to the previous works. The antenna is directly matched to a two-stage low noise amplifier (LNA) in a synergetic way as to give rise to an active integrated antenna (AIA) in order to avoid additional matching or interconnect losses. The LNA is followed by a double-balanced folded Gilbert cell mixer, which produces a lower intermediate frequency (IF) such that no probing is required for measurements. The measured total gain of the AIA is 14 dBi. Its total core area is 0.83 mm 2 while the total chip area, including the pad frame, is 1.55 × 0.85 mm 2 .

Silicon-based four-mode division multiplexing for chip-scale optical data transmission in the 2 μ m waveband

Abstract: Based on a silicon platform, we design and fabricate a four-mode division (de)multiplexer for chip-scale optical data transmission in the 2 μm waveband for the first time, to the best of our knowledge. The (de)multiplexer is composed of three tapered directional couplers for both mode multiplexing and demultiplexing processes. In the experiment, the average crosstalk for four channels is measured to be less than −18 dB over a wide wavelength range (70 nm) from 1950 to 2020 nm, and the insertion losses are also assessed. Moreover, we further demonstrate stable 5 Gbit/s direct modulation data transmission through the fabricated silicon photonic devices with non-return-to-zero on–off keying signals. The experimental results show clear eye diagrams, and the penalties at a bit error rate of 3.8×10−3 are all less than 2.5 dB after on-chip data transmission. The obtained results indicate that the presented silicon four-mode division multiplexer in the mid-infrared wavelength band might be a promising candidate facilitating chip-scale high-speed optical interconnects.

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI

Abstract: Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 $\times $ 1800 $\mu \text{m}^{\mathbf {2}}$ .

The Accelerator Wall: Limits of Chip Specialization

Abstract: Specializing chips using hardware accelerators has become the prime means to alleviate the gap between the growing computational demands and the stagnating transistor budgets caused by the slowdown of CMOS scaling. Much of the benefits of chip specialization stems from optimizing a computational problem within a given chip’s transistor budget. Unfortunately, the stagnation of the number of transistors available on a chip will limit the accelerator design optimization space, leading to diminishing specialization returns, ultimately hitting an accelerator wall. In this work, we tackle the question of what are the limits of future accelerators and chip specialization? We do this by characterizing how current accelerators depend on CMOS scaling, based on a physical modeling tool that we constructed using datasheets of thousands of chips. We identify key concepts used in chip specialization, and explore case studies to understand how specialization has progressed over time in different applications and chip platforms (e.g., GPUs, FPGAs, ASICs)1. Utilizing these insights, we build a model which projects forward to see what future gains can and cannot be enabled from chip specialization. A quantitative analysis of specialization returns and technological boundaries is critical to help researchers understand the limits of accelerators and develop methods to surmount them. Keywords-Accelerator Wall; Moore’s Law; CMOS Scaling

Calculation of non-deformed chip and gear geometry in power skiving using a CAD-based simulation

Abstract: Power skiving is a new machining process that allows the manufacturing of external and internal gears while achieving high throughputs. Although the process was first described during the nineteenth century, it is not until lately that advances in machine tool technology allowed for the process to be implemented on an industrial scale. This paper presents a novel simulation model that enables the accurate prediction of the non-deformed chip geometry, the form and dimensions of the chips produced during the cutting process as well as the characteristics of the gear gap. The simulation model is embedded on a CAD environment in order to take advantage of their increased accuracy. Through the simulation code, the virtual simulation of the manufacturing process is realised. The simulation model was verified with the use of analytical equations regarding the form of the gear. Chip geometry and dimensions for internal and external gears machined with different conditions are also presented.

Fiber-to-chip fusion splicing for low-loss photonic packaging

Abstract: Silicon photonic devices are poised to enter high-volume markets such as data communications, telecommunications, biological sensing, and optical phased arrays. Permanently attaching a fiber to the photonic chip with high optical efficiency, however, remains a challenge. We present a robust, low-loss packaging technique of permanent optical edge coupling between a fiber and a chip using fusion splicing that is low-cost and scalable for high-volume manufacturing. We fuse a SMF-28 cleaved fiber to the chip via a CO2 laser and reinforce it with optical adhesive. We demonstrate minimum loss of 1.0 dB per facet with 0.6 dB penalty over a 160 nm bandwidth from 1480 to 1640 nm.

A Highly Integrated D-Band Multi-Channel Transceiver Chip for Radar Applications

Abstract: This paper presents a low-power, highly-integrated D-Band transceiver chip realized in a 0.13 µm SiGe BiCMOS technology. The integration level includes three receiver (RX) channels, one transmitter (TX) channel, local oscillator (LO) signal generation and distribution network, frequency dividers and serial peripheral interface (SPI) for digital reconfigurability. The receiver achieves a peak gain of 14 dB at 118 GHz, while the transmitter achieves an output power of −6 dBm at 118 GHz. The VCO is realized in a push-push Colpitts topology. Additionally, its output is multiplied by two using a frequency doubler. Hence the transmitter output signal is continuously tunable in the frequency range 117 − 126 GHz, while achieving a measured phase noise of − 93.5 dBc /Hz at 1 MHz offset at 120 GHz. The entire transceiver draws 195 mA from a single 1.8 V supply. A single RX channel draws 19 mA, while a single TX consumes 25 mA. The circuit including pads occupies a chip area of only 3.5 mm × 2.75 mm, which is limited only by the separation necessary for isolation between the channels. The transceiver provides a competitive performance and is suitable for continuous-wave radar applications around 120 GHz.

Channel Modeling and Characterization for Wireless Networks-on-Chip Communications in the Millimeter Wave and Terahertz Bands

Abstract: Wireless networks-on-chip (WiNoC) communications are envisioned as a promising technology to support the interconnection of hundreds of cores in the chip multi-processor design. To meet the future demand for Tera-bit-per-second (Tbps) ultra-fast links in WiNoC, the millimeter wave (mmWave) and Terahertz (THz) bands with ultra-broad spectrum resource are attractive for WiNoC communications. In this paper, a hybrid WiNoC architecture and the CMOS-based stratified chip design are described, in which the flip-chip (FC) package and heat sink are considered. In the WiNoC stratified medium, electromagnetic fields are rigorously analyzed by using Sommerfeld integration, which is verified with full-wave simulation. Based on the developed channel model, the WiNoC propagation is thoroughly characterized by analyzing the path loss, the channel capacity, and reliability. Simulation results show that 0.95 Tbps wireless link with the error rate below 10−14 is achievable for WiNoC communications in the mmWave and THz bands. Furthermore, the impact and guidelines of the chip design on the WiNoC wave propagation are investigated. In particular, the wave propagation performance in the THz WiNoC channel can be improved by decreasing the underfill thickness, proper choice of the silicon thickness, and inserting a bottom layer below the silicon substrate.

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time

Abstract: A new MRAM reference and sensing circuit that can achieve $\mu \text{A}$ resolution and 17.5 nS read access from −40 °C to 125 °C is presented in this paper. A trimmable current-mode latch-type sense amplifier (CLSA) with hybrid-resistance-reference (HRR) and cell location compensation is proposed to resolve small read margin of MRAM. Silicon data measurement is presented to demonstrate a logic-process compatible, fully functional 16-Mb perpendicular MRAM in 40-nm CMOS process. Similar read circuit design concept can be applied to other technology nodes. Another test chip designed in 22 nm achieves wafer level average raw bit-error-rate (BER) of ~0.2 ppm and less than 2-ppm BER for 95th percentile chip.

Multi-Wavelength Optical Transceivers Integrated on Node (MOTION)

Abstract: We report on efforts to develop a high speed, low cost, low energy chip scale optical module for co-packaging on a first-level organic substrate for HPC and Data Center applications.

Wideband adaptive microwave frequency identification using an integrated silicon photonic scanning filter

Abstract: Photonic-assisted microwave frequency identification with distinct features, including wide frequency coverage and fast tunability, has been conceived as a key technique for applications such as cognitive radio and dynamic spectrum access. The implementations based on compact integrated photonic chips have exhibited distinct advantages in footprint miniaturization, light weight, and low power consumption, in stark contrast with discrete optical-fiber-based realization. However, reported chip-based instantaneous frequency measurements can only operate at a single-tone input, which stringently limits their practical applications that require wideband identification capability in modern RF and microwave applications. In this article, we demonstrate, for the first time, a wideband, adaptive microwave frequency identification solution based on a silicon photonic integrated chip, enabling the identification of different types of microwave signals from 1 to 30 GHz, including single-frequency, multiple-frequency, chirped-frequency, and frequency-hopping microwave signals, and even their combinations. The key component is a high Q-factor scanning filter based on a silicon microring resonator, which is used to implement frequency-to-time mapping. This demonstration opens the door to a monolithic silicon platform that makes possible a wideband, adaptive, and high-speed signal identification subsystem with a high resolution and a low size, weight, and power (SWaP) for mobile and avionic applications.

Polymeric fully inertial lab-on-a-chip with enhanced-throughput sorting capabilities

Abstract: In biology and medicine, the application of microfluidics filtration technologies to the separation of rare particles requires processing large amounts of liquid in a short time to achieve an effective separation yield. In this direction, the parallelization of the sorting process is desirable, but not so easy to implement in a lab on a chip (LoC) device, especially if it is fully inertial. In this work, we report on femtosecond laser microfabrication (FLM) of a poly(methyl methacrylate) (PMMA) inertial microfluidic sorter, separating particles based on their size and providing an enhanced-throughput capability. The LoC device consists of a microchannel with expansion chambers provided with siphoning outlets, for a continuous sorting process. Different from soft lithography, which is the most used technique for LoC prototyping, FLM allows developing 3D microfluidic networks connecting both sides of the chip. Exploiting this capability, we are able to parallelize the circuit while keeping a single output for the sorted particles and one for the remaining sample, thus increasing the number of processed particles per unit time without compromising the simplicity of the chip connections. We investigated several device layouts (at different flow rates) to define a configuration that maximizes the selectivity and the throughput.

A hybrid memristor–CMOS chip for AI

Abstract: An integrated co-processor chip based on a memristor crossbar array and complementary metal–oxide–semiconductor (CMOS) control circuitry can be used to implement neuromorphic and machine learning algorithms.

Wideband on-chip terahertz spectrometer based on a superconducting filterbank

Abstract: Terahertz spectrometers with a wide instantaneous frequency coverage for passive remote sensing are enormously attractive for many terahertz applications, such as astronomy, atmospheric science, and security. Here we demonstrate a wide-band terahertz spectrometer based on a single superconducting chip. The chip consists of an antenna coupled to a transmission line filterbank, with a microwave kinetic inductance detector behind each filter. Using frequency division multiplexing, all detectors are read-out simultaneously, creating a wide-band spectrometer with an instantaneous bandwidth of 45 GHz centered around 350 GHz. The spectrometer has a spectral resolution of F/ΔF =380 and reaches photon-noise limited sensitivity. We discuss the chip design and fabrication, as well as the system integration and testing. We confirm full system operation by the detection of an emission line spectrum of methanol gas. The proposed concept allows for spectroscopic radiation detection over large bandwidths and resolutions up to F/ΔF ∼ 1000, all using a chip area of a few cm2. This will allow the construction of medium resolution imaging spectrometers with unprecedented speed and sensitivity.

A Microwatt Dual-Mode Electrochemical Sensing Current Readout With Current-Reducer Ramp Waveform Generation

Abstract: An electrochemical sensing chip with an integrated current-reducer pattern generator and a current-mirror based low-noise chopper-stabilization potentiostat circuit is presented. The pattern generator, utilizing the current reducer technique and pseudo resistors, creates a sub-Hz ramp signal for the cyclic voltammetric (CV) measurement without large-size passive components. The proposed design adopts the chopper-stabilization and low-noise biasing technique for the potentiostat and a counter-based time-to-digital converter to reduce the amplitude noise effects and to convert the sensing current signal to digital codes for further data processing. The design is fabricated using a 0.18-μm CMOS process and achieves a 41 pA current resolution in the current range of ±5 μA while maintaining the R2 linearity of 0.998. The system consumes 16 μW from a 1.2 V supply when a 5 μA sensing current is detected. The power efficiency of the readout interface is 0.31, and the sensing current dynamic range is 108 dB. The design is fully integrated into a single chip and is successfully tested in the dual-mode (CA/CV) measurements with commercial gold electrodes in a potassium ferricyanide solution in sub-millimolar concentrations.

Versatile digital polymerase chain reaction chip design, fabrication, and image processing

Abstract: We present a family of digital polymerase chain reaction (dPCR) chips made of silicon that are (9 × 9) mm2 in size, have a unique layout design, and have between 26,448 and 1,656,000 reaction wells. The chip layout was split into six fields sized 4200 × 2785 μm2 that contain reaction wells with a gap of a few μm separating the fields from each other. We also developed a universal fluorescence imaging method capable of processing images from those chips. It comprised automatic image acquisition, image stitching, alignment mark registration, rotation correction, determination of reaction wells’ positions, and result processing. The chip design, with fully automated image processing, provided a fast and reliable system for the absolute quantitative analysis of dPCR. Combined with ease-of-use, this family of dPCR chips offers a pathway to enable fast and affordable digital microfluidic diagnostic applications.

Versatile platform for performing protocols on a chip utilizing surface acoustic wave (SAW) driven mixing

Abstract: We present and demonstrate a dextrous microfluidic device which features a reaction chamber with volume flexibility. This feature is critical for developing protocols directly on chip when the exact reaction is not yet defined, enabling bio/chemical reactions on chip to be performed without volumetric restrictions. This is achieved by the integration of single layer valves (for reagent dispensing) and surface acoustic wave excitation (for rapid reagent mixing). We show that a single layer valve can control the delivery of fluid into, an initially air-filled, mixing chamber. This chamber arrangement offers flexibility in the relative volume of reagents used, and so offers the capability to not only conduct, but also develop protocols on a chip. To enable this potential, we have integrated a SAW based mixer into the system, and characterised its mixing time based on frequency and power of excitation. Numerical simulations on the streaming pattern inside the chamber were conducted to probe the underlying physics of the experimental system. To demonstrate the on-chip protocol capability, the system was utilised to perform protein crystallization. Furthermore, the effect of rapid mixing, results in a significant increase in crystal size uniformity.

Switched-Beam Endfire Planar Array With Integrated 2-D Butler Matrix for 60 GHz Chip-to-Chip Space-Surface Wave Communications

Abstract: A two-dimensional Butler matrix feed network is designed, implemented, and integrated with a 60 GHz 2 × 2 circular patch planar array for chip-to-chip communications. The realized antenna module is a thin multilayer microstrip structure with a footprint small enough to fit over a typical multicore chip. The network enables endfire (azimuthal) scan of the array main beam in the four diagonal directions, which is demonstrated for the first time in this letter. The antenna module provides a seamless and practical way to achieve reconfigurable interchip communication in multicore multichip (MCMC) systems. A hybrid space-surface wave interconnect is proposed that takes advantage of surface-wave coupling. The matrix is a four-input, four-output, i.e., 4 × 4, network consisting of four interconnected quadrature (90 $^\circ$ ) hybrid couplers. A multiantenna module (MAM) consisting of five antenna modules that emulates diagonal interchip communication in MCMC systems is fabricated. The simulation and measurement of transmission coefficients between the antenna modules on the MAM are performed and compared.

Ultra High Density IO Fan-Out Design Optimization with Signal Integrity and Power Integrity

Abstract: With the development of internet and the rise of artificial intelligence industry, the high performance semiconductor integrated circuits have become a hot product in the semiconductor industry. The 2.5D IC package with ultra-high density I/O is the first structure applied on high performance computing (HPC) like GPU. Applied on GPU or HPC, there is an ASIC die and multiple HBM dice on silicon interposer. Between ASIC die and HBM die, there are lots of high speed signal lines between them and over hundreds of thousands of small vias. But the productivity of silicon interposer is always issue to realize the ultra-high density I/O products. To consider the productivity and performance, TSV-less structure like FOCoS (Fan-Out Chip on Substrate) is proposed by few years ago. There are Chip First FOCoS and Chip Last FOCoS for different process and application. In this paper, a real case with an ASIC die and 2 HBM dice is designed in 2.5D IC and Chip Last FOCoS structures. In this real case, the interposer design and Fan-Out RDL is utilized SiP-id (System in Package intelligent design) design platform to accelerate the ultra-high density I/O routings. In addition, the electrical performance including signal integrity (SI) and power integrity (PI) are compared between 2.5D IC and Chip Last FOCoS. From the analysis results, the dynamic power noise between the two structures is showed in this paper and the electrical performance of HBM2 and 28Gbps SerDes I/Os are displayed as well.

Systems Engineering of Cryogenic CMOS Electronics for Scalable Quantum Computers

Abstract: We report on our systems engineering activities concerning cryogenic CMOS electronics as building blocks for scalable quantum computers. Following the V-model of engineering, the topic is approached both in top-down and in bottom-up fashion. We show the main results from the top-down study using system modeling and simulations. In a bottom-up fashion, a prototype chip was designed and implemented in a commercial 65nm CMOS process. The chip contains a DC digital-to-analog-converter (DC-DAC) and a Pulse-DAC as building blocks for an integrated quantum bit control. The DC-DAC is able to tune a qubit into its operating point. The Pulse-DAC generates pulse patterns with 250MHz sampling frequency to perform gate operations on a qubit.