Showing papers on "Chip published in 2020"

Ultra-dense optical data transmission over standard fibre with a single chip source.

Abstract: Micro-combs - optical frequency combs generated by integrated micro-cavity resonators – offer the full potential of their bulk counterparts, but in an integrated footprint. They have enabled breakthroughs in many fields including spectroscopy, microwave photonics, frequency synthesis, optical ranging, quantum sources, metrology and ultrahigh capacity data transmission. Here, by using a powerful class of micro-comb called soliton crystals, we achieve ultra-high data transmission over 75 km of standard optical fibre using a single integrated chip source. We demonstrate a line rate of 44.2 Terabits s−1 using the telecommunications C-band at 1550 nm with a spectral efficiency of 10.4 bits s−1 Hz−1. Soliton crystals exhibit robust and stable generation and operation as well as a high intrinsic efficiency that, together with an extremely low soliton micro-comb spacing of 48.9 GHz enable the use of a very high coherent data modulation format (64 QAM - quadrature amplitude modulated). This work demonstrates the capability of optical micro-combs to perform in demanding and practical optical communications networks. Microcombs provide many opportunities for integration in optical communications systems. Here, the authors implement a soliton crystal microcomb as a tool to demonstrate more than 44 Tb/s communications with high spectral efficiency.

Micro triboelectric ultrasonic device for acoustic energy transfer and signal communication.

Abstract: As a promising energy converter, the requirement for miniaturization and high-accuracy of triboelectric nanogenerators always remains urgent. In this work, a micro triboelectric ultrasonic device was developed by integrating a triboelectric nanogenerator and micro-electro-mechanical systems technology. To date, it sets a world record for the smallest triboelectric device, with a 50 µm-sized diaphragm, and enables the working frequency to be brought to megahertz. This dramatically improves the miniaturization and chip integration of the triboelectric nanogenerator. With 63 kPa@1 MHz ultrasound input, the micro triboelectric ultrasonic device can generate the voltage signal of 16.8 mV and 12.7 mV through oil and sound-attenuation medium, respectively. It also achieved the signal-to-ratio of 20.54 dB and exhibited the practical potential for signal communication by modulating the incident ultrasound. Finally, detailed optimization approaches have also been proposed to further improve the output power of the micro triboelectric ultrasonic device. Miniaturizing efficient triboelectric nanogenerators remains a challenge. Here, the authors propose a MEMS-based micro triboelectric device for acoustic energy transfer and signal communication which is capable of generating the voltage signal of 16.8 mV and 12.7 mV through oil and sound-attenuation medium respectively with 63kPa at 1 MHz ultrasound input.

Chip Placement with Deep Reinforcement Learning

Abstract: In this work, we present a learning-based approach to chip placement, one of the most complex and time-consuming stages of the chip design process. Unlike prior methods, our approach has the ability to learn from past experience and improve over time. In particular, as we train over a greater number of chip blocks, our method becomes better at rapidly generating optimized placements for previously unseen chip blocks. To achieve these results, we pose placement as a Reinforcement Learning (RL) problem and train an agent to place the nodes of a chip netlist onto a chip canvas. To enable our RL policy to generalize to unseen blocks, we ground representation learning in the supervised task of predicting placement quality. By designing a neural architecture that can accurately predict reward across a wide variety of netlists and their placements, we are able to generate rich feature embeddings of the input netlists. We then use this architecture as the encoder of our policy and value networks to enable transfer learning. Our objective is to minimize PPA (power, performance, and area), and we show that, in under 6 hours, our method can generate placements that are superhuman or comparable on modern accelerator netlists, whereas existing baselines require human experts in the loop and take several weeks.

Minimization of test time in system on chip using artificial intelligence-based test scheduling techniques

Abstract: System on chip (SoC) is a microchip which integrates many semiconductor devices into a single chip. The complete system that is integrated with many components and circuits has to be tested for its performance. At the same time, testing of SoC should not affect the final cost of the chip. The production cost of each and every chip can be reduced by minimizing the test time of each SoC. The testing time of each SoC can be minimized by using test scheduling techniques more efficiently and effectively. In this paper, artificial intelligence-based natural-inspired techniques such as ACO, MACO, ABC, bat and firefly algorithms are proposed to perform effective test scheduling, thereby reducing the total cost of the chip. The proposed algorithms are implemented on d695 and p22810 benchmark circuits for various values of TAM widths. The performance of the various algorithms was evaluated, and it is inferred that among the several algorithms used bat algorithm performs much better in reducing the overall testing time of SoC, and hence, the SoC cost is also reduced.

A “sample-in-multiplex-digital-answer-out” chip for fast detection of pathogens

Abstract: Point-of-care (POC) testing offers rapid diagnostic results. However, the quantification of current methods is performed using standard curves and external references, and not direct and absolute quantification. This paper describes an integrated multiplex digital recombinase polymerase amplification (ImdRPA) microfluidic chip which combines DNA extraction, multiplex digital RPA and fluorescence detection together in one chip, creating a “sample-in-multiplex-digital-answer-out” system. Multi-layer soft lithography technology was used, with polydimethylsiloxane (PDMS) as the chip material and a glass slide as the substrate. This microfluidic chip has a six-layer structure and screw microvalve control function. The sample preparation for the chip involved magnetic bead-based nucleic acid extraction, which was completed within 15 min without any instrument dependence. The dRPA region was divided into 4 regions (3 positive detection areas and 1 negative control area) and included a total of 12 800 chambers, with each chamber being able to contain a volume of 2.7 nL. The screw valve allowed for the reaction components of each specific goal to be pre-embedded in different regions of the chambers. The reagents were passively driven into the dRPA region using vacuum-based self-priming introduction. Furthermore, we successfully demonstrated that the chip can simultaneously detect three species of pathogenic bacteria within 45 min and give digital quantitative results without the need to establish a standard curve in contaminated milk. Moreover, the detection limit of this ImdRPA microfluidic chip was found to be 10 bacterial cells for each kind of pathogen. These characteristics enhance its applicability for rapid detection of foodborne bacteria at the point-of-care (POC). We envision that the further development of this integrated chip will lead to rapid, multiplex and accurate detection of foodborne bacteria in a feasible manner.

AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs

Abstract: Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for DNN chips. However, designing DNN chips is non-trivial because: (1) mainstream DNNs have millions of parameters and operations; (2) the large design space due to the numerous design choices of dataflows, processing elements, memory hierarchy, etc.; and (3) an algorithm/hardware co-design is needed to allow the same DNN functionality to have a different decomposition, which would require different hardware IPs to meet the application specifications. Therefore, DNN chips take a long time to design and require cross-disciplinary experts. To enable fast and effective DNN chip design, we propose AutoDNNchip - a DNN chip generator that can automatically generate both FPGA- and ASIC-based DNN chip implementation given DNNs from machine learning frameworks (e.g., PyTorch) for a designated application and dataset. Specifically, AutoDNNchip consists of two integrated enablers: (1) a Chip Predictor, built on top of a graph-based accelerator representation, which can accurately and efficiently predict a DNN accelerator's energy, throughput, and area based on the DNN model parameters, hardware configuration, technology-based IPs, and platform constraints; and (2) a Chip Builder, which can automatically explore the design space of DNN chips (including IP selection, block configuration, resource balancing, etc.), optimize chip design via the Chip Predictor, and then generate optimized synthesizable RTL to achieve the target design metrics. Experimental results show that our Chip Predictor's predicted performance differs from real-measured ones by < 10% when validated using 15 DNN models and 4 platforms (edge-FPGA/TPU/GPU and ASIC). Furthermore, accelerators generated by our AutoDNNchip can achieve better (up to 3.86X improvement) performance than that of expert-crafted state-of-the-art accelerators.

Design and fabrication of a SiN-Si dual-layer optical phased array chip

Abstract: A SiN-Si dual-layer optical phased array (OPA) chip is designed and fabricated. It combines the low loss of SiN with the excellent modulation performance of Si, which improves the performance of Si single-layer OPA. A novel optical antenna and an improved phase modulation method are also proposed, and a two-dimensional scanning range of 96°×14° is achieved, which makes the OPA chip more practical.

Ultrasensitive SO2 sensor for sub-ppm detection using Cu-doped SnO2 nanosheet arrays directly grown on chip

Abstract: Ultrasensitive trace detection of toxic and harmful gases has become an important research field with increasing of human needs. This work introduces a chemiresistive type of SO2 sensor based on Cu-doped SnO2 nanosheet arrays (Cu-SnO2 NSAs), which are directly grown on the chip of Au electrodes via a facile homogeneous precipitation method. The vertically-aligned Cu-SnO2 nanosheets with ultrathin thickness (

Demonstrating delay-based reservoir computing using a compact photonic integrated chip.

Abstract: Photonic delay-based reservoir computing (RC) has gained considerable attention lately, as it allows for simple technological implementations of the RC concept that can operate at high speed. In this paper, we discuss a practical, compact and robust implementation of photonic delay-based RC, by integrating a laser and a 5.4 cm delay line on an InP photonic integrated circuit. We demonstrate the operation of this chip with 23 nodes at a speed of 0.87 GSa/s, showing performances that is similar to previous non-integrated delay-based setups. We also investigate two other post-processing methods to obtain more nodes in the output layer. We show that these methods improve the performance drastically, without compromising the computation speed.

AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs

Abstract: Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for domain-specific hardware accelerators (i.e., DNN chips). However, designing DNN chips is non-trivial because: (1) mainstream DNNs have millions of parameters and billions of operations; (2) the design space is large due to numerous design choices of dataflows, processing elements, memory hierarchy, etc.; and (3) there is an algorithm/hardware co-design need for the same DNN functionality to have a different decomposition that would require different hardware IPs and thus correspond to dramatically different performance/energy/area tradeoffs. Therefore, DNN chips often take months to years to design and require a large team of cross-disciplinary experts. To enable fast and effective DNN chip design, we propose AutoDNNchip - a DNN chip generator that can automatically produce both FPGA- and ASIC-based DNN chip implementation (i.e., synthesizable RTL code with optimized algorithm-to-hardware mapping) from DNNs developed by machine learning frameworks (e.g., PyTorch) for a designated application and dataset without humans in the loop. Specifically, AutoDNNchip consists of 2 integrated enablers: (1) a Chip Predictor, which can accurately and efficiently predict a DNN accelerator's energy, throughput, latency, and area based on the DNN model parameters, hardware configurations, technology-based IPs, and platform constraints; and (2) a Chip Builder, which can automatically explore the design space of DNN chips (including IP selections, block configurations, resource balancing, etc.), optimize chip designs via the Chip Predictor, and then generate synthesizable RTL code with optimized dataflows to achieve the target design metrics. Experimental results show that our Chip Predictor's predicted performance differs from real-measured ones by

A digital microfluidic system with 3D microstructures for single-cell culture.

Abstract: Despite the precise controllability of droplet samples in digital microfluidic (DMF) systems, their capability in isolating single cells for long-time culture is still limited: typically, only a few cells can be captured on an electrode. Although fabricating small-sized hydrophilic micropatches on an electrode aids single-cell capture, the actuation voltage for droplet transportation has to be significantly raised, resulting in a shorter lifetime for the DMF chip and a larger risk of damaging the cells. In this work, a DMF system with 3D microstructures engineered on-chip is proposed to form semi-closed micro-wells for efficient single-cell isolation and long-time culture. Our optimum results showed that approximately 20% of the micro-wells over a 30 × 30 array were occupied by isolated single cells. In addition, low-evaporation-temperature oil and surfactant aided the system in achieving a low droplet actuation voltage of 36V, which was 4 times lower than the typical 150 V, minimizing the potential damage to the cells in the droplets and to the DMF chip. To exemplify the technological advances, drug sensitivity tests were run in our DMF system to investigate the cell response of breast cancer cells (MDA-MB-231) and breast normal cells (MCF-10A) to a widely used chemotherapeutic drug, Cisplatin (Cis). The results on-chip were consistent with those screened in conventional 96-well plates. This novel, simple and robust single-cell trapping method has great potential in biological research at the single cell level. A novel microfluidic device enables researchers to isolate and culture single cells for use in drug testing and other experiments. To date, the high voltages required to capture cells on electrodes of a digital microfluidic (DMF) device have led to a reduced lifespan for the device and potentially damaged the cells. A team led by Yanwei Jia of the University of Macau overcame this by incorporating 3D microstructures into a DMF chip. This constrains the shape of cell culture droplets to isolate and capture single cells. With the use of low evaporation temperature oil and a surfactant, the system enabled them to use one quarter of the voltage of other designs for droplet transportation. The ability to isolate and culture individual cells will be of great value in addressing biological questions at the single-cell level.

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Abstract: Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding of the wireless intra-chip channel. This paper first demonstrates that such assumptions do not hold in the context of commercial chips by evaluating losses and dispersion in them. Then, we leverage the system’s monolithic nature to engineer the channel , this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it , pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce the path loss and delay spread of a simulated commercial chip by 47 dB and $7.3\times $ , respectively, enabling intra-chip wireless communications over 10 Gb/s and only 3.1 dB away from the dispersion-free case.

Reliable UHF Long-Range Textile-Integrated RFID Tag Based on a Compact Flexible Antenna Filament.

Abstract: This paper details the design, fabrication and testing of flexible textile-concealed Radio Frequency Identification (RFID) tags for wearable applications in a smart city/smart building environment. The proposed tag designs aim to reduce the overall footprint, enabling textile integration whilst maintaining the read range. The proposed RFID filament is less than 3.5 mm in width and 100 mm in length. The tag is based on an electrically small (0.0033 λ 2 ) high-impedance planar dipole antenna with a tuning loop, maintaining a reflection coefficient less than −21 dB at 915 MHz, when matched to a commercial RFID chip mounted alongside the antenna. The antenna strip and the RFID chip are then encapsulated and integrated in a standard woven textile for wearable applications. The flexible antenna filament demonstrates a 1.8 dBi gain which shows a close agreement with the analytically calculated and numerically simulated gains. The range of the fabricated tags has been measured and a maximum read range of 8.2 m was recorded at 868 MHz Moreover, the tag’s maximum calculated range at 915 MHz is 18 m, which is much longer than the commercially available laundry tags of larger length and width, such as Invengo RFID tags. The reliability of the proposed RFID tags has been investigated using a series of tests replicating textile-based use case scenarios which demonstrates its suitability for practical deployment. Washing tests have shown that the textile-integrated encapsulated tags can be read after over 32 washing cycles, and that multiple tags can be read simultaneously while being washed.

Control and Calibration Recipes for Photonic Integrated Circuits

Abstract: This article presents the key ingredients and the best practices for implementing simple, effective and robust control and calibration procedures for arbitrary photonic integrated circuit (PIC) architectures. Three main features are presented and discussed: a technique to cancel out the effects of mutual crosstalk among thermal tuners, the exploitation of labelling to identify different optical signals, the use of input modulated signal to automatically reshape the frequency response of the device. Examples of application are then illustrated to show the validity and generality of the approach, namely a cross-bar interconnect matrix router, a variable bandwidth filter and third order coupled microring filter. Further, the automatic and dynamic generation of the lookup table of add/drop hitless filters operating on a dense wavelength division multiplexing grid is demonstrated. The lookup table achieved with the proposed approach can dynamically update itself to new conditions of the chip or new requirements of operation, such as variations in channel modulation format or perturbation induced by neighboring devices due to a change in their working point.

Improving the Power Efficiency of Micro-LED Displays with Optimized LED Chip Sizes

Abstract: Micro-LED (light-emitting diode) is a potentially disruptive display technology, while power consumption is a critical issue for all display devices. In this paper, we develop a physical model to evaluate the power consumption of micro-LED displays under different ambient lighting conditions. Both power efficiency and ambient reflectance are investigated in two types of full color display structures: red/green/blue (RGB) micro-LEDs, and blue-LED pumped quantum dots color-conversion. For each type of display with uniform RGB chip size, our simulation results indicate that there exists an optimal LED chip size, which leads to 30–40% power saving. We then extend our model to analyze different RGB chip sizes, and find that with optimized chip sizes an additional 12% average power saving can be achieved over that with uniform chip size.

Multimodal Integrated Sensor Platform for Rapid Biomarker Detection

Abstract: Precision metabolomics and quantification for cost-effective rapid diagnosis of disease are the key goals in personalized medicine and point-of-care testing. At present, patients are subjected to multiple test procedures requiring large laboratory equipment. Microelectronics has already made modern computing and communications possible by integration of complex functions within a single chip. As More than Moore technology increases in importance, integrated circuits for densely patterned sensor chips have grown in significance. Here, we present a versatile single complementary metal–oxide–semiconductor chip forming a platform to address personalized needs through on-chip multimodal optical and electrochemical detection that will reduce the number of tests that patients must take. The chip integrates interleaved sensing subsystems for quadruple-mode colorimetric, chemiluminescent, surface plasmon resonance, and hydrogen ion measurements. These subsystems include a photodiode array and a single photon avalanche diode array with some elements functionalized to introduce a surface plasmon resonance mode. The chip also includes an array of ion sensitive field-effect transistors. The sensor arrays are distributed uniformly over an active area on the chip surface in a scalable and modular design. Bio-functionalization of the physical sensors yields a highly selective simultaneous multiple-assay platform in a disposable format. We demonstrate its versatile capabilities through quantified bio-assays performed on-chip for glucose, cholesterol, urea, and urate, each within their naturally occurring physiological range.

A Broadband On-Chip Bandpass Filter Using Shunt Dual-Layer Meander-Line Resonators

Abstract: A miniaturized broadband on-chip bandpass filter (BPF) is presented based on shunt dual-layer meander-line resonators and several metal-insulator-metal (MIM) capacitors. To understand the operational mechanism of the proposed BPF structure, it is analyzed using a simplified LC equivalent circuit model for further investigation of the transmission zeros (TZs) distributions. To validate the proposed idea, the BPF with three TZs is implemented in a commercial 0.13- $\mu \text{m}$ SiGe (Bi)-CMOS process. The measured results show that the BPF has a center frequency at 18 GHz with a very broad bandwidth of 66.7%, and the minimum insertion loss within the passband is 2.9 dB. The chip, excluding the GSG pads, is about 0.318 mm $\times0.392$ mm.

Chip-based soliton microcomb module using a hybrid semiconductor laser

Abstract: Photonic chip-based soliton microcombs have shown rapid progress and have already been used in many system-level applications. There has been substantial progress in realizing soliton microcombs that rely on compact laser sources, culminating in devices that only utilize a semiconductor gain chip or a self-injection-locked laser diode as the pump source. However, generating single solitons with electronically detectable repetition rates from a compact laser module has remained challenging. Here we demonstrate a current-initiated, Si3N4 chip-based, 99-GHz soliton microcomb driven directly by a compact, semiconductor-based laser. This approach does not require any complex soliton tuning techniques, and single solitons can be accessed by tuning the laser current. Further, we demonstrate a generic, simple, yet reliable, packaging technique to facilitate the fiber-chip interface, which allows building a compact soliton microcomb package that can benefit from the fiber systems operating at high power (> 100 mW). Both techniques can exert immediate impact on chip-based nonlinear photonic applications that require high input power, high output power, and interfacing chip-based devices to mature fiber systems.

Flip-Chip Integration of InP to SiN Photonic Integrated Circuits

Abstract: We present our hybrid InP to SiN TriPleX integration interface with a novel alignment technique and its application to complex photonic integrated circuits. The integration interface comprises vertical alignment stops, which simplify the alignment process and allow for array integration with the same simplicity as for single dies. Horizontal alignment is carried out by utilizing optical backscatter reflectometry to get an active feedback signal without the need to operate the chip. Thus, typical contacting limitations of active flip-chip alignment are overcome. By using this method, we demonstrate the integration of InP DFB lasers with more than 60 mW of optical power coupled to a SiN waveguide with an averaged coupling loss of -2.1 dB. The hybrid integration process is demonstrated for single dies as well as full arrays. We evaluate the feasibility of the assembly process for complex photonic integrated circuits by integrating an InP gain chip to a SiN TriPleX external cavity. The process proves to be well suited and allows monitoring chip quality during assembly. A fully functional hybrid integrated tunable laser is fabricated, which is capable of full C-band tuning with optical output power of up to 60 mW.

A Production-worthy Fan-Out Solution - ASE FOCoS Chip Last

Abstract: The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match Outsourced Semiconductor Assembly and Testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can flip chips on a ball grid array substrate, and FOCoS constructs from multi-chips with short distance between chip to chip by multi-chip system for interposer less structure, which has the potential for heterogeneous integration and functional chip in one package. Heterogeneous integration refers to the integration of separately manufactured components into a higher level assembly. In this study, the yield of the production over 99% and of FOCoS chip last package was presented. To reduce the wafer warpage effect, we used three dimensional finite element method (3D-FEM) and advanced Metrology Analyzer (aMA) can find the optimum thickness and Coefficient of Thermal Expansion (CTE) of the glass carrier. About FOCoS chip last device, large-size packages with 8 complex chips especially with fine line RDL and different size μbump joint structures inside have been successfully developed. In reliability examination, the test vehicle also passed the JEDEC and IPC qualification, respectively. Finally, ASE has successfully established the FOCoS chip production line, and further developed it in a larger area, and higher integration complexity to meet the growing needs of the 5G era.

Design of a 100-GHz Double-Sideband Low-IF CW Doppler Radar Transceiver for Micrometer Mechanical Vibration and Vital Sign Detection

Abstract: This article presents a fully integrated 100-GHz continuous-wave Doppler radar transceiver with the double-sideband low-intermediate-frequency (IF) architecture for mechanical vibration and vital sign detection. Fabricated in a 65-nm CMOS process, the whole radar chip transceiver consumes 262 mW with a size of 0.9 mm $\times2.0$ mm. Instead of utilizing a fundamental 100-GHz voltage controlled oscillator (VCO) in the chip, a push–push frequency doubler with the 50-GHz external source is adopted to drive the transceiver. Under a dedicated design on the system architecture and circuit blocks, the chip could transmit 4-dBm saturated power ( $P_{\mathrm {sat}}$ ) over 93–105 GHz with a 40-mV 1-kHz IF carrier and achieve good I/Q performance of phase mismatch $\mu \text{m}$ displacement from 1.5 m, the human vital-sign signal from 2 m, and even a small bullfrog’s hybrid respiratory motion from 0.6 m. To the best of our knowledge, this is the first 100-GHz CMOS Doppler radar transceiver chip with the low-IF architecture for the biological vital sign detection.

High-Sensitivity MEMS Pressure Sensor Utilizing Bipolar Junction Transistor with Temperature Compensation

Abstract: The paper presents MEMS pressure sensor chip utilizing novel electrical circuit with bipolar-junction transistor-based (BJT) differential amplifier with negative feedback loop (PDA-NFL). Pressure sensor chips with two circuits have been manufactured and tested: the first chip uses circuit with vertical n-p-n (V-NPN) BJTs and the second – circuit with horizontal p-n-p (L-PNP) BJTs. The demonstrated approach allows for increase of pressure sensitivity while keeping the same chip size regarding the chip with Wheatstone bridge circuit: 3.6X for circuit utilizing V-NPN BJTs and 2.4X for circuit utilizing L-PNP BJTs. Significant reduction of both noise and temperature instability of output signal has been demonstrated: output signal noise is about 15 μV (Usup = 5 V) and temperature errors have only 2–3 times higher values regarding the chip with Wheatstone bridge circuit.

A 16.1-bit Resolution 0.064-mm 2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS

Abstract: A novel direct resistive-sensor-to-digital readout circuit is presented, which achieves 16.1-bit ENOB while being very compact and robust. The highly digital time-based architecture employs a single voltage-controlled oscillator (VCO), counter, and digital feedback loop for the readout of an external single-ended highly nonlinear resistive sensor, such as an NTC thermistor. In addition to the inherent first-order noise shaping due to the oscillator, the second loop in SMASH configuration creates second-order noise shaping. Fabricated in 180-nm CMOS, the readout circuit achieves 16.1 bit of resolution for 1-ms conversion time and consumes only $171~\mu \text{W}$ , resulting in an excellent 2.4-pJ/c.s. FOMW for a resistive sensor interface while occupying only 0.064 mm 2. The specific closed-loop architecture tackles the VCO nonlinearity, achieving more than 14 bits of linearity. Multiple prototype chip samples have been measured in a temperature-controlled environment from −40 °C to 125 °C for the readout of commercial external NTC thermistors. A maximum temperature inaccuracy of 0.3 °C is achieved with only one-point trimming at room temperature. Since the circuit architecture decouples the sensor excitation from the feedback, high electromagnetic interference (EMI) immunity at the sensor node is demonstrated as well.

A multi-volume microfluidic device with no reagent loss for low-cost digital PCR application

Abstract: A multi-volume multi-level vertical branching microchannel microfludic chip is presented in this study for low-cost and easy-operation digital PCR (dPCR). The chip with multi-volume design can achieve a dynamic range of over 104 for nucleic acid quantification with only 1792 chambers, which consist of two types of chambers with different volumes and quantities. Meanwhile, the dPCR chip realizes 100 % sample compartmentalization without any loss. In addition, the chip can partition samples autonomously in a simple way through negative pressure provided by a degassed PDMS layer. Furthermore, a glass-PDMS-glass “sandwich” structure was employed in the chip to form a robust support. The quantitative capability of the digital PCR chip is evaluated by measuring a 10-fold serial dilution of the KRAS plasmid template. Owing to its characteristics of easy operation process, low cost, relative wide dynamic range, and no sample loss, the proposed dPCR chip is expected to further promote the extensive application of digital PCR, especially in the POCT field.

Large-Scale Integrated Multi-Lines Optical Phased Array Chip

Abstract: We design and integrate four optical phased arrays (OPAs) in a single chip. Each OPA possesses different output grating period. Furthermore, we use optical switches to select one or more OPAs for beam scanning. We demonstrate the longitudinal scanning by tuning the laser wavelength. The experimental results show that the scanning range of the four-lines chip reaches 28.54° when the wavelength ranges from 1520 nm to 1570 nm, and the eight-lines one reaches 19.04° with wavelength range of 1520 nm-1540 nm. We greatly improve the wavelength tuning efficiency for longitudinal scanning.

The bPOL12V DCDC converter for HL-LHC trackers: towards production readiness

Abstract: We present the electrical and radiation characterisation of the most recent prototype of the bPOL12V DCDC converter, a stacked assembly of two ASICs inside a QFN32 package. The use of a reference voltage generator chip in 130nm CMOS on top of the ASIC integrating the control system and power train enables improved radiation tolerance and the trimming of the output voltage during the production phase. Prototype samples have been exposed to X-rays, proton and neutron irradiations, as well as subject to long-term electrical stress to evaluate their reliability in the application. The results confirm that only a few minor modifications are required to achieve production readiness.