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Cipher

About: Cipher is a research topic. Over the lifetime, 9409 publications have been published within this topic receiving 110309 citations. The topic is also known as: cypher & cryptographic algorithm.


Papers
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Proceedings ArticleDOI
01 Feb 2009
TL;DR: In this scheme, CABAC engine serves the purpose of encryption cipher without affecting the coding efficiency of H.264/AVC by keeping the original bitrate, generating completely compliant bitstream and utilizing negligible computational cost.
Abstract: This paper proposes a new method for the protection of copyrighted multimedia content. Here the problems of compression and selective encryption (SE) have been simultaneously addressed for the state of the art video codec H.264/AVC. SE is performed in the context adaptive variable length coding (CAVLC) module of video codec. For this purpose, CAVLC is converted to an encryption cipher using permutation of equal length codes from a specific variable length coding (VLC) table. In our scheme, entropy coding engine serves the purpose of encryption step without aecting the coding eciency

27 citations

Journal ArticleDOI
TL;DR: The security analysis shows that the new hybrid system consisting of a permutation-substitution network based on two different encryption techniques: chaotic systems and the Latin square is secure enough to resist brute-force attack, differential attack, chosen-plain text attack, known-plaintext attack and statistical attack.
Abstract: In this paper, we introduce a new hybrid system consisting of a permutation-substitution network based on two different encryption techniques: chaotic systems and the Latin square. This homogeneity between the two systems allows us to provide the good properties of confusion and diffusion, robustness to the integration of noise in decryption. The security analysis shows that the system is secure enough to resist brute-force attack, differential attack, chosen-plaintext attack, known-plaintext attack and statistical attack. Therefore, this robustness is proven and justified.

27 citations

01 Jan 2002
TL;DR: This report investigates the significance of FPGA implementations of the block ciphers KHAZAD and MISTY1 and proposes designs that unroll the cipher rounds and pipeline them in order to optimize the frequency and throughput results.
Abstract: The technical analysis used in determining which of the NESSIE candidates will be selected as a standard block cipher includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGA’s) are highly attractive options for hardware implementations of encryption algorithms and this report investigates the significance of FPGA implementations of the block ciphers KHAZAD and MISTY1. A strong focus is placed on high throughput circuits and we propose designs that unroll the cipher rounds and pipeline them in order to optimize the frequency and throughput results. In addition, we implemented solutions that allow to change the plaintext and the key on a cycle-by-cycle basis with no dead cycle. The resulting designs fit on a VIRTEX1000 FPGA and have throughput between 8 and 9 Gbits/s. This is an impressive result compared with existing FPGA implementations of block ciphers within similar devices.

27 citations

Journal ArticleDOI
TL;DR: A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper.

27 citations

Journal ArticleDOI
TL;DR: It is shown that SPA can be practically applied to a CMOS digital hardware circuit to determine the bit values of an NLFSR and SPA therefore has applicability toNLFSR-based stream ciphers.
Abstract: Linear feedback shift registers (LFSRs) and nonlinear feedback shift register (NLFSRs) are major components of stream ciphers. It has been shown that, under certain idealised assumptions, LFSRs and LFSR-based stream ciphers are susceptible to cryptanalysis using simple power analysis (SPA). In this study, the authors show that SPA can be practically applied to a CMOS digital hardware circuit to determine the bit values of an NLFSR and SPA therefore has applicability to NLFSR-based stream ciphers. A new approach is used with the cryptanalyst collecting power consumption information from the system on both edges (triggering and non-triggering) of the clock in the digital hardware circuit. The method is applied using simulated power measurements from an 80-bit NLFSR targeted to an 180 nm CMOS implementation. To overcome inaccuracies associated with mapping power measurements to the cipher data, the authors offer novel analytical techniques which help the analysis to find the bit values of the NLFSR. Using the obtained results, the authors analyse the complexity of the analysis on the NLFSR and show that SPA is able to successfully determine the NLFSR bits with modest computational complexity and a small number of power measurement samples.

27 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023155
2022309
2021343
2020415
2019509
2018487