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Circuit switching

About: Circuit switching is a research topic. Over the lifetime, 7103 publications have been published within this topic receiving 99834 citations. The topic is also known as: circuit switched & Circuit-switched.


Papers
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Journal ArticleDOI
TL;DR: The analysis shows that cut-through switching is superior (and at worst identical) to message switching with respect to the above three performance measures.

1,008 citations

Journal ArticleDOI
TL;DR: Various network topologies and switching strategies are covered here, including interconnection networks for communication among processors and memory modules.
Abstract: Concurrent processing depends on interconnection networks for communication among processors and memory modules. Various network topologies and switching strategies are covered here.

859 citations

Proceedings ArticleDOI
30 Aug 2010
TL;DR: This work proposes a hybrid packet and circuit switched data center network architecture (or HyPaC) which augments the traditional hierarchy of packet switches with a high speed, low complexity, rack-to-rack optical circuit-switched network to supply high bandwidth to applications.
Abstract: Data-intensive applications that operate on large volumes of data have motivated a fresh look at the design of data center networks. The first wave of proposals focused on designing pure packet-switched networks that provide full bisection bandwidth. However, these proposals significantly increase network complexity in terms of the number of links and switches required and the restricted rules to wire them up. On the other hand, optical circuit switching technology holds a very large bandwidth advantage over packet switching technology. This fact motivates us to explore how optical circuit switching technology could benefit a data center network. In particular, we propose a hybrid packet and circuit switched data center network architecture (or HyPaC for short) which augments the traditional hierarchy of packet switches with a high speed, low complexity, rack-to-rack optical circuit-switched network to supply high bandwidth to applications. We discuss the fundamental requirements of this hybrid architecture and their design options. To demonstrate the potential benefits of the hybrid architecture, we have built a prototype system called c-Through. c-Through represents a design point where the responsibility for traffic demand estimation and traffic demultiplexing resides in end hosts, making it compatible with existing packet switches. Our emulation experiments show that the hybrid architecture can provide large benefits to unmodified popular data center applications at a modest scale. Furthermore, our experimental experience provides useful insights on the applicability of the hybrid architecture across a range of deployment scenarios.

680 citations

Journal ArticleDOI
TL;DR: The author uses the congestion measures for a multilayer bandwidth-allocation algorithm, emulating some function of virtual circuit setup, fast circuit switching, and fast packet switching at these levels and sheds insight on traffic engineering issues such as appropriate link load, traffic integration, trunk group and switch sizing, and bandwidth reservation criteria for two bursty services.
Abstract: The major benefit of a broadband integrated ATM (asynchronous transfer mode) network is flexible and efficient allocation of communications bandwidth for communications services. However, methods are needed for evaluating congestion for integrated traffic. The author suggests evaluating congestion at different levels, namely the packet level, the burst level, and the call level. Congestion is measured by the probabilities of packet blocking, burst blocking, and call blocking. He outlines the methodologies for comparing these blocking probabilities. The author uses the congestion measures for a multilayer bandwidth-allocation algorithm, emulating some function of virtual circuit setup, fast circuit switching, and fast packet switching at these levels. The analysis also sheds insight on traffic engineering issues such as appropriate link load, traffic integration, trunk group and switch sizing, and bandwidth reservation criteria for two bursty services. >

656 citations

Patent
01 May 2001
TL;DR: In this article, a new generation Fast Circuit Switch (packet/circuit) communication processors and platform which enables a new Internet Exchange Networking Processor Architecture at the edge and core of every communication system.
Abstract: A system and method for delivering increases speed, security, and intelligence to wireline and wireless systems. The present invention includes a new generation Fast Circuit Switch (packet/circuit) Communication processors and platform which enables a new Internet Exchange Networking Processor Architecture at the edge and core of every communication system, for next generation Web Operating System or Environment (WOE) to operate on with emphasis of a non-local processor or networking processor with remote web computing capabilities. A Unified Network Communication & Processor System or UniNet is a New generation network architecture of packet/circuit communication processors or Internet networking processor, that increases speeds over any communication channels and topologies, synchronizing, enabling, improving, controlling and securing all of the data transmission of web applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data corn backbone. The present invention is capable of operating on any topology with distributed intelligence and data switching/routing, which is located at the edge. This method not only alleviates the ever increasing data processing bottleneck which is currently done by the data communication and telecom switch and routers, but it also enables new and next generation Internet Processor architecture. The UniNet is also a flexible solution for the novel concept that the capability of a network interface should depend on the level of service assigned to a service access point, not the capacity of the total network, such as transaction services with a short burst of messages with short access delay. The present invention increases channel capacity by using a parallel or multi-channel structure in such wireless and wireline at the edge or the core of. This new architecture of the present invention uses parallel bitstreams in a flexible way and distributed switching/routing technique, is not only to avoid the potential bottlenet of centralized switches, but also to increase speed with intelligence that is seamlessly integrating into the Fiber Optic Backbone such as WDM and SONET of the MAN/WAN network with a Real-time guarantees, different types of traffic (such as Stringent synchronous, isochronous, and asynchronous data messages) with different demands, and privacy & security of multi access and integrated services environment.

567 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20237
202220
202132
202085
2019111
2018143