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Classic RISC pipeline

About: Classic RISC pipeline is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 5076 citations.


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Book
01 Jan 1988
TL;DR: RISC Architecture: An Overview, MIPS Processor Architecture Overview, FPU Overview, Floating Point Exceptions, and Instruction Pipeline.
Abstract: 1. RISC Architecture: An Overview. 2. MIPS Processor Architecture Overview. 3. CPU Instruction Set Summary. 4. Memory Management System. 5. Caches. 6. Exception Processing. 7. FPU Overview. 8. FPU Instruction Set Summary and Instruction Pipeline. 9. Floating Point Exceptions. Appendixes. Index.

487 citations

Journal ArticleDOI
10 Dec 1992
TL;DR: A new RISC system architecture called a Compressed Code RISC Processor is presented, which depends on a code-expanding instruction cache to manage compressed programs.
Abstract: The difference in code size between RISC and CISC processors appears to be a significant factor limiting the use of RISC architectures in embedded systems. Fortunately, RISC programs can be effectively compressed. An ideal solution is to design a RISC system that can directly execute compressed programs. A new RISC system architecture called a Compressed Code RISC Processor is presented. This processor depends on a code-expanding instruction cache to manage compressed programs. The compression is transparent to the processor since all instructions are executed from cache. Experimental simulations show that a significant degree of compression can be achieved from a fixed encoding scheme. The impact on system performance is slight and for some memory implementations the reduced memory bandwidth actually increases performance.

288 citations

Patent
25 Mar 1994
TL;DR: In this paper, an expanded RISC instruction contains data fields which designate indirect registers that point to emulation registers that correspond to registers in the target computer, and a field in the expanded instruction restricts the emulated width to that required by a particular emulated instruction.
Abstract: A RISC architecture computer configured for emulating the instruction set of a target computer to execute software written for the target computer, e.g., an Intel 80X86, a Motorola 680X0 or a MIPS R3000. The apparatus is integrated with a core RISC computer to form a RISC computer that executes an expanded RISC instruction. The expanded RISC instruction contains data fields which designate indirect registers that point to emulation registers that correspond to registers in the target computer. The width of the emulation registers is at least the width of those in the target computer. However, a field in the expanded RISC instruction restricts the emulated width to that required by a particular emulated instruction. Additionally, the expanded RISC instruction contains a field which designates the emulation mode for condition codes and selects logic to match the condition codes of the target computer. Target instructions are parsed and dispatched to sequences of one or more expanded RISC instructions to emulate each target instruction.

211 citations

Proceedings ArticleDOI
12 May 1981
TL;DR: The architecture of RISC I and its novel hardware support scheme for procedure call/return are presented and it appears possible to build a single chip computer faster than VAX 11/780 and to have a much shorter design time.
Abstract: The Reduced Instruction Set Computer (RISC) Project investigates an alternative to the general trend toward computers with increasingly complex instruction sets: With a proper set of instructions and a corresponding architectural design, a machine with a high effective throughput can be achieved. The simplicity of the instruction set and addressing modes allows most instructions to execute in a single machine cycle, and the simplicity of each instruction guarantees a short cycle time. In addition, such a machine should have a much shorter design time.This paper presents the architecture of RISC I and its novel hardware support scheme for procedure call/return. Overlapping sets of register banks that can pass parameters directly to subroutines are largely responsible for the excellent performance of RISC I. Static and dynamic comparisons between this new architecture and more traditional machines are given. Although instructions are simpler, the average length of programs was found not to exceed programs for DEC VAX 11 by more than a factor of 2. Preliminary benchmarks demonstrate the performance advantages of RISC. It appears possible to build a single chip computer faster than VAX 11/780.

210 citations

Journal ArticleDOI
K. Diefendorff1, M. Allen1
TL;DR: Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, the authors'-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed.
Abstract: Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110's instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described. >

205 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20211
20203
20181
20175
20163
201514