Showing papers on "Clock gating published in 1967"
Patent•
07 Nov 1967TL;DR: In this article, a J-K master-slave flip-flop system with a simplified gating system was presented, in which no clock pulse connections are required for the transfer transistors.
Abstract: Disclosed is a J-K master-slave flip-flop system having a simplified gating system and in which no clock pulse connections are required for the transfer transistors. Clock pulses are fed to input gates. Additional clocks may be added by tying the input gates to clock lines. The clock pulse are ANDed together at the input gate so that the J-K master-slave flip-flop system is suitable for use in large arrays.
11 citations
Patent•
12 Dec 19671 citations