Showing papers on "Clock gating published in 1968"

Data synchronizing system

Abstract: A system is described for acquiring incoming serial data, particularly of PCM code types, and establishing synchronization between the incoming data and a local clock generator. The system includes input signal conditioning circuits which applies the incoming data to a phase lock loop containing the local clock generator. The phase lock loop includes circuits for acquiring the input data and synchronizing the local clock generator therewith in spite of low signal-to-noise ratios and the loss of a large percentage of the input data bits in transmission. The local clock generator circuits include circuits which compare the phase of the clock generator output with the phase of the incoming data bits on a maximum likelihood phase estimate basis. The local clock generator outputs are applied to detect the incoming bits and reconstruct them into a noise-free output data stream.

Clock-synchronizing circuits

Abstract: A system for the generation of clock signals in a data processing apparatus is disclosed, in which the clock signals are developed from a source of higher frequency pulses. The clock signals are applied to an apparatus in which data signals are represented in nonreturn-to-zero (NRZ) manner, and the clock signals are synchronized to the occurrence of changes in data item representation. It is recognized that the synchronization of the signals may vary and, in particular that there is a condition of spurious synchronization in which the clock signals may occur 180* out of phase with data changes. The system proposed is arranged to recognize both variations in synchronism and the spurious synchronism condition and to correct the relative timing between clock and data change signals to bring the system into true synchronism by modifying the application of the higher frequency pulses to a clock signal generating countdown arrangement.

Asynchronous sequential divide by three logic circuit

Abstract: The particular state assignments used result in a two-level realization that can be economically implemented with integrated logic gates. With successive level changes of the input clock signal the circuit produces a succession of states of the internal state variable which are fed back to control, along with the clock, these internal variables. Each variable has a period three times the period of the clock and may be monitored as the output but the duty cycle and phase of each differ.

Bistable flip-flop circuit with improved control of clock threshold

Abstract: A bistable flip-flop circuit for use preferably in monolithic semiconductor integrated circuits having a master flip-flop at the circuit input and a slave output at the circuit output with coupling transistors between the two master and slave flip-flops. The emitters of the transistors coupled through a resistor to the clock pulse input so that the master flip-flop changes state responsive to the rise time of the clock pulse and the slave flip-flop changes state during the fall time of the clock pulse throughout an extended temperature range.

Gating circuit for displaced pulses

Abstract: A gating circuit useful for separating data pulses from clock pulses in a double frequency detection system includes a signal generator that provides a sawtooth waveform having ramp portions of the same slope and a flyback interval of fixed magnitude. When the sawtooth signal is above a variable threshold, an input gate is enabled to allow the clock pulses to initiate flyback. The proportions of the sawtooth waveform above and below the threshold remain constant, so that early or late arrival of a clock pulse does not affect the gating of succeeding clock pulses. Thus, an output gate is made to operate to block clock pulses while passing data pulses.