Showing papers on "Clock gating published in 1969"
Patent•
NEC1
TL;DR: In this article, the phase differences between incoming clock signals from other stations and a reference clock signal of a particular station were detected and the insertion or deletion of pulses into or from the reference clock pulse train in response to the sensed phase differences.
Abstract: A synchronization system for use in a time-division communication system makes almost exclusive use of digital circuits. Those circuits include means for detecting the phase differences between incoming clock signals from other stations and a reference clock signal of a particular station, and means for controlling the insertion or deletion of pulses into or from a reference clock pulse train in response to the sensed phase differences.
17 citations
Patent•
15 Dec 1969
TL;DR: In this paper, a two-phase clock circuit with true and complementary output terminals has been proposed to drive logic circuitry whose operation requires the definition of two substantially nonoverlapping clock phases.
Abstract: A two phase clock circuit particularly useful for driving logic circuitry whose operation requires the definition of two substantially non-overlapping clock phases. The clock circuit includes a square wave oscillator having true and complementary output terminals, each driving a different power amplifier. Each oscillator output terminal is connected to its associated power amplifier through a NOR gate. The second terminal of each NOR gate is connected to the output of the opposite power amplifier so that neither power amplifier can begin to form a clock pulse until the clock pulse formed by the other power amplifier has terminated, or in other words, until the output voltage of the other power amplifier has fallen to a defined threshold level.
14 citations
Patent•
26 Aug 1969
TL;DR: In this article, a variable-width pulse is derived from the phase relation of a non-return-to-zero PCM signal and the local clock, and a constant width pulse of one-bit clock period is inverted to provide a control bias to adjust the bias of the varactor diode.
Abstract: The local bit clock is provided by an astable multivibrator having a varactor diode included in the cross coupling thereof to adjust the phase of the bit clock. A variable-width pulse is derived from the phase relation of a nonreturn-to-zero PCM signal and the local clock. A constant width pulse of one-bit clock period is derived from the PCM signal and inverted. These two pulse signals are algebraically combined and integrated to provide a control bias to adjust the bias of the varactor diode and, hence, clock phase to achieve and maintain bit synchronization.
7 citations
Patent•
09 Oct 1969
TL;DR: In this article, an active limiter is used to provide a very fast response in the feedback path without producing unwanted modes in the output signal from the clock generator, which is used with a storage system including a storage medium and wherein the storage medium includes a reference track to produce a reference signal which is coupled as an input to the clock generators.
Abstract: A clock generator which produces a stabilized clock output signal and which is used with a storage system including a storage medium and wherein the storage medium includes a reference track to produce a reference signal which is coupled as an input to the clock generator. The clock generator includes a variable voltage-controlled oscillator and incorporates a feedback path to control the output from the clock generator. The feedback path includes an active limiter so as to provide for a very fast response in the feedback path without producing unwanted modes in the output signal from the clock generator. The active limiter includes a pair of voltage sensors for sensing excessive plus or minus excursions of the feedback signal relative to the reference potential and wherein the voltage sensors control an electronic switch to short out the feedback path when the excursion of the feedback signal is above a particular level in a plus or minus direction relative to the reference potential. The electronic switch operates in an oscillatory manner until the level of the feedback signals falls within the permissible range of excursion.
5 citations
Patent•
17 Mar 1969
TL;DR: In this article, a combination of a clock and a light switch is presented in a SUITABLE HOUSING, where a face plate is used to hide the light switch and the clock.
Abstract: IN COMBINATION, A CLOCK AND A LIGHT SWITCH ASSEMBLY ARE MOUNTED IN A SUITABLE HOUSING THEREFOR. THE HOUSING IS PROVIDED WITH A FACE PLATE SIZED TO BE SECURED OVER AN OPENING IN THE HOUSING SO THAT APERTURES PROVIDED IN THE FACE PLATE RECEIVE THE CLOCK AND THE LIGHT SWITCH ASSEMBLY. A DECORATIVE STRIKE PLATE IS DISPOSED OVER THE HOUSING, BEING POSITIONED ADJACENT TO THE FACE PLATE TO EXPOSE THE CLOCK AND SWITCH OF THE LIGHT SWITCH ASSEMBLY. AN ELECTRICAL CIRCUIT ASSOCIATED WITH THE CLOCK AND THE LIGHT SWITCH ASSEMBLY PERMITS THE OPERATION OF THE LIGHT SWITCH ASSEMBLY TO BE SELECTIVELY INTERRUPTED WHILE THE OPERATION OF THE CLOCK REMAINS UNDISTURED. IF PREFERRED, THE LIGHT SWITCH ASSEMBLY MAY BE REPLACED BY A SOCKET ASSEMBLY.
4 citations
Patent•
IBM1
TL;DR: In this paper, a gating transistor with a small capacitor coupled between the base of the transistor and ground is used to control a bistable multivibrator at high speed.
Abstract: A gating circuit suitable for operating a circuit such as a bistable multivibrator at high speed wherein a gating transistor has a small capacitor coupled between the base of the transistor and ground. A gating pulse is coupled through a resistor to the base of the gating transistor to temporarily store a charge in the capacitor. A set pulse signal applied in the next instant of time to the emitter of the gating transistor causes the gating transistor to be turned on to produce at the collector of the gating transistor, a current pulse that is sufficient to control the bistable multivibrator circuit.
2 citations