Showing papers on "Clock gating published in 1976"

Automatic clock tuning and measuring system for LSI computers

Abstract: An automatic clock tuning and measuring system is provided for data processing system wherein fixed frequency clock pulses are selectively delayed and distributed in accordance with a clock path and delay selection made by a computing means. A reference generator is connected to the fixed frequency clock pulses source for delaying the clock pulses a reference amount which is selected by the computing means in accordance with the predetermined delay associated with the selected path. An automatic time measuring means is connected to both the reference generator and the clock distribution means for providing an output indicative of the time comparison condition of a delayed clock pulse and the reference delayed clock pulse. The output time comparison or non-comparison of the delayed clock pulse and the reference delayed clock pulse is utilized through the computer means to adjust the amount of delay introduced by the automatic delay means or is utilized to adjust the delay increment established in the reference generator to provide the clock tuning and measuring respectively.

Clock system having adaptive synchronization feature

Abstract: A clock cycle is provided by a delay device, the output of which is coupled via an inverter to the input thereof, which inverter is combined in a gate structure so as to enable such clock cycle and derivative clock pulses coupled to be generated as a signal passes through the delay device. The gate structure is coupled to receive a so-called stall signal inhibiting the clock system from generating an output. The stall signal so inhibits such clock system only after the present clock cycle is completed. Further, the gate structure is coupled so that a stall signal received and then cleared before the end of the clock cycle will have no effect on the system. The system also responds to a removal or clearing of a stall signal by immediately beginning another clock cycle after the relatively insignificant delay introduced by the gate structure.

Automatic data synchronizer

Abstract: Disclosed is a device for automatically synchronizing incoming digital data with a local clock. Incoming clock pulses are compared with the local clock pulses after being delayed by a sufficient amount to produce synchronization between the incoming and local clock pulses. The incoming data pulses are delayed by the same amount as the incoming clock pulses so that they too are synchronized with the local clock. Both digital delays are variable and may be used to provide both fractional clock period delays or multiple clock period delays for accurate synchronization over a relatively long communications cycle.

Data clock separator with missing clock detect

Abstract: Decoding apparatus for separating clock and data pulses from a double-frequency pulse train, including a retriggerable window one-shot, a bit shift compensation circuit, clock rate tracking means, data bit and clock bit gates, means for keeping track of whether a specific pulse is a data pulse or a clock pulse, and means for actuating the data bit and clock bit gates, based on the status of the system and the state of the window one-shot. The apparatus also provides means for detecting when a clock pulse is missing, including circuitry which simulates the detection of a clock pulse to the rest of the device to keep the system status and timing properly synchronized to the pulse train data.

Data communications system with improved digital phase-locked loop retiming circuit

Abstract: A digital timing recovery circuit is disclosed for synchronously transmitting digitally encoded data in a multiterminal configuration between a data processor and a plurality of data terminals associated therewith. Phase shifted synchronous data from the data processor is continuously compared with a newly generated synchronous clock generated at a repeater interposed along the communication line for minimization of the time differential between the retiming clock and the transmitted data. The data transitions enable a digitally implemented one-shot, which generates pulses, the leading edges of which pulses enable a difference counter, while the leading edges of the retiming clock pulses disable the counter. The difference counter output is sampled in a digital phase locked loop to derive the number of cycles of a stable oscillator which occur between the two aforementioned leading edges of the generated pulses. A difference of less than a predetermined count such as two, results in no correction of the retiming clock, a difference count greater than such predetermined amount, such as a count of three through seven, advances the clock by adding a pulse to the retiming clock, and a difference of more than a predetermined number of counts, such as eight, retards the clock by subtracting a pulse from the retiming clock. Thus, continuous digital adjustment of the synchronous clock is provided to maintain the counter difference below a predetermined count, such as two, which serves to resynchronize bit-shifted data with the retiming clock for retransmission into the communications channel.

Automatic phasing circuit to transfer digital data from an external interface circuit to an internal interface circuit

Abstract: The phasing circuit transfers digital data from an external interface circuit to an internal interface circuit with no bit errors and no violation of bit count integrity under control of an external clock having a given frequency and a given phase and an internal clock having a frequency equal to the given frequency and a phase that is different than the given phase. The phasing circuit includes a data output from the external interface circuit, a first clock output to couple the external clock from the external interface circuit, a data input to the internal interface circuit, at least a second clock output to couple the internal clock from the internal interface circuit, at least first and second D-type flip flops having their D inputs and Q outputs coupled in cascade with each other, the data output and the data input and logic circuitry coupled to the clock input of each of the first and second flip flops, the second clock output and a selected one of the data output and the first clock output to select the internal clock or an inverted version of the internal clock as the clock for the first flip flop to provide the desired digital data transfer.

Standby apparatus for clock signal generators

Abstract: A clock output signal is aligned in phase to conicide with the phase of signals derived from a master clock. In the event that there is a malfunction of the master, standby control circuitry modifies the phase of the clock output signal incremental quantities until it is in phase with the phase of signals from a standby clock. The clock output signal is thereafter maintained aligned in phase to coincide with the phase of the signals derived from the standby clock.

Sinewave clock driver with adjustable delay

Abstract: A sinewave clock distribution network and a clock driver for use in the network permit simplified distribution and synchronization in very high speed logic and digital transmission systems. The sinewave central clock is connected through a branching network to a plurality of clock drivers located in the vicinity of digital circuits to which clock pulses are to be supplied. Each clock driver includes a receiver amplifier which is AC coupled to the clock line. The output of the receiver amplifier is connected to a phase shift RC network which includes an adjustable capacitance. By adjusting the capacitance in the RC network, the timing or delay of the clock signal can be varied to permit synchronization of the clock signals at various points in the distribution network. The phase delayed signal from the RC network is coupled to a limiter which limits the input sinewave to form a squarewave for use by the digital circuits.

Clock supervision in digital systems

Abstract: A method for the supervision of clock signals in a digital data system in which data is clocked progressively by clock signals through a number of registers includes supervisory flip flops associated with each register with a clock supervision bit progressively clocked through the flip flops which together from a supervision chain. The absence of one or more of the clock signals prevents the clock supervision bit from propagating to the end of the chain. By monitoring said clock supervision bit after propagation through the supervision chain it can be determined whether clock signals are supplied correctly to all registers.

Digitally regulated inverter

Abstract: An inverter for direct current power generation is shown in which both voltage regulation and logical control of the output are achieved by digitally controlling the application of clock signals to the inverter circuit. A standard clock source is used to drive the inverter and digital circuitry, timed from the same clock source, is used to control the gating of clock pulses to the inverter. Entire clock pulses including both positive going and negative going transitions are blocked so as to preserve the balanced excitation of the inverter transformer. Logical control signals can also be used to disable the application of clock pulses.

Mos power stage for generating non-overlapping two-phase clock signals

Abstract: This relates to an MOS power stage of a two-phase clock signal generator arranged on the same integrated circuit chip as the circuit to be driven. The generator consists of one MOSFET inverter, the output of which is multiplexed by the two clock signals. In this manner, power loss in the MOSFET is reduced.

Clock signal and auxiliary signal transmission system

Abstract: The transmission system enables clock signals and auxiliary signals to be transmitted over a single channel, thereby avoiding the necessity of providing an independent auxiliary signal channel. This is accomplished by shifting in time the rising edges of the basic clock signal in the sending circuit as a function of the auxiliary signals to be transmitted, and then detecting this time-shift at the receiving circuit to recover the auxiliary signals. The clock signal is regenerated at the receiving circuit from the falling edges of the received clock signals.

Clock sequencing apparatus having more states than clock phase outputs

Abstract: This invention relates to a clock sequencing apparatus which allows for clock stoppage at the end of a particular clock sequence without a false decoding of clock pulses at the beginning of what would have been the next clock sequence. This result is accomplished by providing a multi-state sequential apparatus having more states than clock phases. The apparatus will detect a stop condition on the last clock phase of a clock sequence and instead of changing to the state associated with the first clock phase of the next clock sequence, it will instead change state to one or more additional "dead time" states which will allow other logic circuitry to discontinue gating of the clock phases before the apparatus returns to the state associated with the first phase of the next clock sequence. The apparatus will then remain at the state associated with the first phase of the next clock sequence until the clock is restarted and the process is repeated.

Bit clock reproducer

Abstract: PURPOSE:To produce easily a stabilized bit clock by setting the n-notation counter with the output of m-notation counter which puts out a pulse when the same level continues by m-clock and by counting the oscillator output as an input clock.

Logic transfer circuit employing MOS transistors

Abstract: This relates to an MOS logic synchronizing circuit operating with a single phase clock waveform. A logic inverter has two parallel-connected switching MOST's, the gate of one (M4) being connected to clock and the gate of the other (M2) being coupled to the logic input via the source-drain path of a third MOST (M1) whose gate is connected to clock. Input signal change is delayed by a full clock period.