Showing papers on "Clock gating published in 1978"

Multiple clock selection system

Abstract: A system for switching among a plurality of input clock signals to produce an output clock signal which avoids the presence of spurious signals during the process of switching from one to another of said plurality of input clock signals. When it is desired to switch from one input clock signal to a new input clock signal, clock output logic is inhibited from supplying any clock output signal for a selected time period, after which the newly selected input clock signal is supplied as the clock output signal. The time period is dependent on the clock pulse rate of the newly selected input clock signal and is sufficiently long to assure that no spurious signals will occur thereafter.

Fault-tolerant clock system

Abstract: A fault-tolerant clock system for providng digital timing signals (system clock signals) is provided by a plurality of clock sources. Each clock source receives as inputs the generated clock signals from all the other clock sources and contains receiver circuitry to derive a system clock signal from said clock sources which is the consensus clock signals of the other sources. Each clock source generates and distributes to the other clock sources a clock signal which is phase locked to the derived system clock from its clock receiver. In a system of (2r+2) clock sources (r+2) of them will remain phase locked to each other despite up to r clock source failures. Any clock receiver responsive to any (2r+1) of the clock sources can therefore derive a correct system clock despite up to r clock source failures.

Variable symmetry multiphase clock generator

Abstract: The clock generator, which is shown as being a part of a data processor, includes a recirculating shift register and gate combination for deriving a set of four clock phase signals from a master clock signal. The generator also includes two gates and a D flop which form sequential circuitry. The latter controls the shift register to impart a desired nonsymmetry to the clock signals, and to vary that symmetry, as necessary to minimize the clock cycle time and to maximize the processor operating speed. To this end, the circuitry normally makes the clock pulse widths a minimum, consistent with the processor requirements, and, on demand, doubles the widths of only those clock pulses which are actually timing the slowest processor portion, thereby lengthening only those specific clock cycles which contain the demanded widened clock pulses.

Fault-tolerant clock signal distribution arrangement

Abstract: A fault-tolerant clock signal distribution system for a plurality of equipment units is disclosed. Fault tolerance is achieved by independent bussing of clock signals from each of a pair of duplicated clock sources to a plurality of clock receiver units, each receiver unit associated with one of the plurality of equipment units and including sequential logic apparatus operative to examine the two clock signal trains bussed to the clock receiver unit and to ignore that signal train that phase lags the other. In case the phase leading clock source or its transmission bus fails, the remaining clock signal takes over. Because the outputs of the duplicated clock sources are distributed over separate busses, either source may comprise the phase-leading clock at any particular clock receiver unit. The phase difference between the two clock source outputs is kept small enough such that any resultant irregularity in the clock receiver unit output upon failure of one of the two clock sources or transmission busses will not affect the normal operation of the equipment units served by the clock distribution arrangement.

High reliability active-standby clock arrangement

Abstract: A clock pulse circuit is disclosed in which two clock pulse generators operate in an active-standby circuit arrangement to provide a highly reliable single clock output signal comprising a sequence of repetitive pulses. The arrangement comprises a plurality of counters to count pulses generated by each of the clock pulse generators. Comparison circuitry connected to the counters generates an inequality signal indicative of an apparent failure of one of the generators. Logic circuitry responsive to the inequality signal will cause subsequent clock output pulses to be derived from the operating pulse generator. In one embodiment of this invention an actual failure is distinguished from an allowable phase drift of the generator output signal. Another embodiment utilizes additional counters responsive to complementary generator output signals to maintain an uninterrupted sequence of clock output pulses regardless of a failure in either pulse generator.

Logic for generating multiple clock pulses within a single clock cycle

Abstract: Clock logic for generating multiple clock pulses during a single clock cycle. In response to a signal indicative of a clock cycle, effectively two clock pulses are produced in a relatively short period of time. Such logic, which includes a delay element, causes first a load pulse to be produced thereby enabling the loading of information into, for example, a register. Additionally, and within the same clock cycle as the load pulse and in response to the same signal, an increment pulse is produced to, for example, increment a counting function which may be included in such register.

Self-calibrating electric clock circuit

Abstract: A clock circuit designed to keep time based upon a known frequency of an alternating current power supply is provided with a d.c. power backup system to operate the clock circuit during periods of a.c. power failure. The clock circuit includes a high frequency oscillator which generates a large number of timing pulses for each alternating current power cycle. During periods of normal operation on alternating current power, the number of oscillator timing pulses occurring between successive null points in the alternating current power supply waveform are counted and stored. When the clock circuit is operated from the d.c. power supply during periods of a.c. power failure, the last count of timing pulses between successive null points in the a.c. cycle is loaded as an initial count into a counter. The counter is decremented down to zero, whereupon the counter registers the passage of a period of time corresponding to the time interval between two null points in the a.c. power cycle, at that time no longer present. This count is used to update a time recorder to maintain accurate time even during periods of power failure.

Clock voltage generator for semiconductor memory with reduced power dissipation

Abstract: A clock generator for producing internal waveforms for an MOS dynamic RAM or the like provides a preselected delay period between input and output clocks. A pair-delay circuit including two transistor stages produces the desired delay, a driver circuit provides the necessary high level output. A pair of series transistors in the output of the pair-delay, with the node between the series transistors being precharged, provides precise control of the delay over a wide range. Power dissipation is reduced in the driver circuit by avoiding the possibility of d.c. current paths when the reset clock goes high.

Switching circuit for regulating the repetition rate of clock pulses

Abstract: The invention relates to a novel switching circuit for regulating the repetition rate of clock pulses generated by a clock pulse generator. This repetition rate regulation of the clock pulses thereby controls the sampling instants at which a data signal is sampled. The best possible sampling interest is found by sampling at a first zero crossing of a distorted data pulse after its maximum value. The circuit of the invention generates a first signal which corresponds to the sign of the difference between the actual and the desired values of the data signal at the sampling instants; the circuit also generates a second signal which corresponds to the sign of the desired value of the data signal. A delay element delays the second signal by a period of the clock pulse. A multiplier circuit multiplies the first signal by the delayed second signal and produces an output control signal which regulates the repetition rate of the clock pulse generator.

Clock supervisory system

Abstract: PURPOSE:To facilitate an easy cut-off of the fault and thus to realize an earlier detection of the clock-system fault by separating the input clock break detection circuit from the output clock phase step-out detection circuit of the phase lock oscillator, thus enhancing the reliability for supply and distribution of the clock. CONSTITUTION:Phase lock oscillator PLO3 is constituted with phase detector 31, LPF3(LPF32, oscillator 33 and local divider 34 each. Then the output clock frequency of oscillator 3 is divided through divider circuit 4 to deliver clock frequencies 4fN, 2fN and fN each to the output terminal. The step-out detection is given to oscillator 3 via output clock supervisory circuit 11 which supplies the output of detector 31, and the beat signal is generated in case the phase step-out is detected. At the same time, the phase step-out detection is given to the input clock via output clock supervisory circuit 11 which uses the output of lock route switch circuit 1 and circuit 4 as the input. Then the output of circuit 11 is applied to circuit 1 via clock route switch control circuit 2 to facilitate the switching of the clock route.