Showing papers on "Clock gating published in 1979"

Low power consumption data processing system

Abstract: A data processing system which contains a read-only memory circuit, an arithmetic circuit, and a control circuit on a single semiconductor chip including a clock generating circuit for supplying system clocks to all of the circuits on the chip and the clock generating circuit is structured such that on the input of an external halt signal, the clock circuits will cease supplying system clocks during a period that provides for information contained within the system on the semiconductor chip.

Redundant clock signal generating circuitry

Abstract: A clock signal generator for providing redundant clock signals includes two clock modules that utilize phase-locked loop oscillators for generating clock and reference signals and for diagnosing malfunctions of the generated clock and reference signals. One clock module is selected as the master, and the other clock module is the slave, being phase and frequency locked to the master. Switching the master between the clock modules may be externally initiated by select signals and also is automatically initiated when malfunctions are detected. The master and slave clock modules are always phase and frequency locked to one another, even if both clock modules are malfunctioning. When both clock modules experience simultaneous malfunctions, the master is selected in accordance with the externally generated select signals. Since the master and slave clock modules are always phase and frequency locked, switching the master is transparent to clock signal utilization circuitry. The redundant clock signal generator may be advantageously utilized in time-division-multiplex communication systems where uninterruped clock signals are necessary for signal transmission and reception.

Microprocessor having dual frequency clock

Abstract: A microcomputer having a microprocessor operative in response to a dual frequency clock, such microprocessor being adapted to read data stored in a programmable memory in response to address and read enable signals supplied to a programmable memory and being adapted to process such data in response to the clock pulses supplied by the dual frequency clock. The dual frequency clock produces clock pulses at a relatively low rate until such time as either a sensing device is activated or a time duration has passed, in which case the mine is to selfdestruct. When the sensor is activated the microprocessor commands the dual frequency clock to produce relatively high frequency clock pulses to enable the microprocessor to rapidly determine whether the mine should or should not be detonated. Relatively low power is consumed by the microcomputer during the period of time the processor is "counting time" and computing whether the predetermined period of time has arrived, i.e., whether the time for "self destruction" has arrived. When the sensor detects a potential enemy object, relatively rapid computation occurs in response to the relatively high frequency clock pulses to determine whether the mine should be detonated.

Phase locked loop clock synchronizing circuit with programmable controller

Abstract: A clock synchronization unit for controlling frequency and phase of a local clock and synchronism with an external clock signal, employs a programmable controller as a part of a phase-locked loop. The controller provides highly accurate control of the clock, including verification of the accuracy of the clock control signal before applying it to the clock oscillator as well as control of the magnitude to the clock oscillator to avoid rapid changes in frequency. In one particular embodiment, the programmable controller comprises duplicated microprocessors which perform operations in step. In a master/slave oscillator arrangement, the controller controls the slave clock oscillator as well as the master to assure tracking of the slave to the master.

Redundant clock system utilizing nonsynchronous oscillators

Abstract: A clock system is disclosed having two identical clocks not synchronized with each other. Each of the clocks includes a circuit for selecting the output of one of the clocks as the present system output. Further, each clock includes logic for detecting errors in the operation of itself, and of the other. When an error is detected in the operation of the clock selected to be the present system output, a switchover sequence control switches the output signal of the nonselected clock to become the new system output. The switchover sequence control includes a feature which ensures that the interval between pulses in the system output is greater than a predetermined period in order to minimize detrimental effects on circuitry utilizing the clock system output.

Low power consumption integrated circuit for a combined timepiece and calculator

Abstract: An integrated circuit device having a combined time-keeping mode and calculator mode comprises a generator stage for generating basic clock signals and system clock signals, a processor stage responsive to a supply of the system clock signals for executing arithmetic operations required for the timekeeping mode and the calculator mode key input members for introducing information into the processor stage as key input signals, and a clock control for controlling the supply of the system clock signals. The processor stage is adapted to develop a command signal to indicate the completion of the arithmetic operations. The clock control is responsive to the rising and trailing edges of the key input signals for enabling the supply of the system clock signals. The generation of the command signal causes the clock control to prevent the system clock signals from being fed to the processor stage.

Clock check circuit

Abstract: An apparatus adapted to check for the continuous presence of an incoming clock pulse train comprising an exclusive OR gate, to the input of which are coupled the clock pulse train and a second train of clock pulses delayed by one half the period of the incoming clock pulse train. A third train of clock pulses delayed by three quarters of the clock period is utilized to strobe the OR gate output into a pair of flip-flops. If the two inputs to the OR gate are the same a fault exists and a flip-flop is set to indicate on which excursion the fault occurred.

Pixel clock for scanner

Abstract: A clock circuit for clocking video image signals in a raster scanner. The clock circuit includes an inverting gate enabled during scanning with gate output feedback to gate input through an adjustable time delay, the delay inherent in the gate being summed with the delay of the adjustable time delay to provide gate switching and clock output. A register compares clock scan line frequency with preselected scan line resolution and a phase comparator compares scan duration with register output to control clock frequency.

Diversity switch correlation system

Abstract: A multiple-channel microwave communications system with an improved diversity switch permitting the system to be constructed without the necessity of equalizing channel delays wthin a 1/2 bit period by adjusting coaxial cable lengths. The average clock frequency is made to be the on-line channel frequency. The off-line clock frequency is forced to assume the on-line clock frequency by shifting the off-line clock one-half bit, that is 180°, when it is advanced or delayed more than 180°. Phase shifters of 180° are provided in each channel but with only the off-line channel permitted to shift. In addition, the bit content of the dual channel receiving system is aligned over a plus or minus three-bit range by a correlation loop circuit.

Variable frequency logic clock

Abstract: A logic clock signal generator implemented with delay lines having a plurality of taps, wherein the taps are selectively feedback coupled to the input to produce a clock signal having a plurality of selectively variable time periods.

Clock pulse amplifier and clipper

Abstract: A voltage regulator circuit for reducing the noise sensitivity of digital logic circuits by controlling the voltage amplitude range of the clock signal. The circuit includes sensing means connected to the clock input for determining the range of the voltage amplitude of the input clock signal, a regulator circuit connected to the sensing circuit for limiting the voltage swing of the clock signal, and a clock output connected to the regulator circuit for supplying an output clock signal having a predetermined voltage amplitude range.