Showing papers on "Clock gating published in 1984"

Data processing apparatus with clock signal control by microinstruction for reduced power consumption and method therefor

Abstract: Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.

Automatic signal delay adjustment method

Abstract: A method for automatically adjusting the propagation time delay of an electrical circuit, such as an integrated circuit chip. In a preferred embodiment, the method is employed to de-skew the clock outputs provided by a plurality of clock distribution chips having different signal propagation times. In a preferred implementation of the method, feedback circuitry including a multi-tapped delay line and an accurate constant delay are employed in conjunction with a phase comparator for automatically adjusting the propagation delay of each chip to provide substantially the same constant delay relative to a main system clock for the clock outputs provided by the clock distribution chips.

Automatic signal delay adjustment apparatus

Abstract: Apparatus for automatically adjusting the propagation time delay of an electrical circuit, such as an integrated circuit chip. In a preferred embodiment, automatic de-skewing circuitry is provided on each of a plurality of clock distribution chips for de-skewing the clock outputs from different chips. In a preferred implementation of the de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate constant delay are employed in conjunction with a phase comparator for automatically adjusting the propagation delay of each chip to provide substantially the same constant delay relative to a main system clock for the clock outputs provided by the clock distribution chips.

Clock adjustment method and apparatus for synchronous data communications

Abstract: The disclosed clock adjustment method and apparatus utilizes a periodically transmitted positive or negative predetermined fixed increment clock phase adjustment signal to phase adjust the clocks of the system. The transmitter clock is periodically compared with a common reference clock and a fixed increment clock adjustment signal is transmitted to the receiver which adjusts its clock by applying the fixed increment clock adjustment signal to the common reference clock. The utilization of a predetermined fixed increment clock phase adjustment signal eliminates the need to send the resolution of the clock adjustment and hence reduces the number of data bits required to send clock information over the communication channel.

Glitch lockout circuit for memory array.

Abstract: Glitch lockout circuit for a static random access memory (RAM) which prevents the writing or reading of incorrect data when a system clock is switched from a standard clock source to an alternate clock source. A dummy bit line (60) is added to the memory arrangement which is always precharged during a first clock phase (PHI1) and discharged during a second clock phase (PHI2). The state of the dummy bit line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase. Thus, if the dummy bit line stays low, the second clock phase will stay low and none of the RAM cells will be accessed.

Synchronized selectable rate clocking system

Abstract: A data processing system is provided with multiple system clock sources operating at different frequencies for selectively and synchronously driving a plurality of clock pulse generators. The clock pulse generators include four-stage ring counters which may be controlled to produce either four or eight phase clocking signals. When a change is to be made from one system clock source to another, the clock pulse generators are stopped. A phase capture register stores an indication of the last phase generated. While the clock pulse generators are stopped, the change over to the new system clock source is made. The clock pulse generators are restarted at a first time or a second, later time depending upon whether the stored phase indication indicates that the clock pulse generators were stopped at one of phases 5-8 or one of phases 1-4.

Clock oscillator for a cardiac pacer having frequency compensation for temperature and voltage fluctuations

Abstract: A temperature and voltage stable clock circuit for use in implantable cardiac pacers employs CMOS devices to minimize current drain. The circuit includes a timing capacitor which is alternately charged to and discharged between two established threshold voltages during respective charge and discharge cycles, the periods of which determine the clock frequency. To render the frequency of the clock circuit independent of changes in capacitor charge and discharge currents brought about by changes in temperature, the threshold voltage is increased with temperature so that the charge and discharge cycles remain constant. To render the frequency of the clock circuit independent of changes in the power supply voltage, a Wilson current source is used to maintain a constant charge and discharge current to the timing capacitor.

Circuit for selectively extending a cycle of a clock signal

Abstract: A circuit comprising first, second and third latches selectively extends a cycle of a clock signal of a memory system in response to a control signal. A second clock signal having a frequency which is a predetermined multiple of the clock signal of the memory system is coupled to an input of the second and third latches. The first latch receives first and second control signals indicating the detection of parity errors in the memory system and suspends or delays the normal transition of the third latch which provides the memory system clock signal, thereby extending a cycle of the clock signal. The second latch resets the first latch which thereafter resets the third latch causing the clock signal to return to normal cycle operation.

Adaptively tuned clock recovery circuit

Abstract: An adaptively tuned clock recovery circuit suitable for digroup terminal equipment comprises a reference pattern generator which generates two ones followed by fourteen zeros generated at the transmit clock rate. The pattern is applied to a tunable resonant circuit in the receive clock recovery circuit and the phase-difference between the free oscillations of the resonant circuit during the fourteen zeros and the transmit clock is detected. The resonant circuit frequency is automatically altered by switching capacitor in or out until the phase-difference is diminished to a predetermined value, whereupon the tuning process stops and the equipment is returned to normal operation.

Integrated memory circuit of a series-parallel-series type

Abstract: In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided, to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information, which is provided by means of pulse duration variation, for adapting the time delay of the memory circuit (FIG. 1).

Multiple clock power down method and structure

Abstract: A method and structure is provided for powering down a plurality of clocks in a predetermined sequence. In one embodiment, a clock is powered down when it reaches a predefined logical level following the receipt of a power down signal. In another embodiment, a clock is powered down in response to a power down signal when the clock reaches a predefined level, and all clocks derived from that clock reach predefined levels. This is accomplished by including an edge sense circuit for determining when a clock reaches a predefined level, circuitry for combining a plurality of logical signals which indicate when the clock has reached said predefined level, and when all clocks derived from that clock have been powered down. Means and structure are also provided for powering down internal read/write control signals in response to a power down signal, thereby minimizing power consumption which would occur if the read/write control signals were switching during the power down cycle.

Clock signal test circuit

Abstract: An integrated circuit which has serially connected clock drivers for generating sequential clock signals further includes test circuitry for testing for the occurence of the clock signals. The test circuitry includes a current source for each of the sequential clock signals each of which is enabled upon receiving its associated clock signal. Consequently, the current sources are sequentially enabled until a clock signal fails to occur at which time no more clock signals occur so that no more current sources are enabled. The current sources are connected to a probe pad which is accessible external to the integrated circuit. Test apparatus for detecting the enabled current sources can be connected to the integrated circuit at the probe pad.

Modem clock with automatic gain control

Abstract: A modem receiver having a timing recovery circuit is disclosed. The timing recovery circuit includes circuitry for extracting timing information, multiplication circuitry responsive to the timing information for providing a clock envelope signal and processing circuitry for controlling the gain of the clock envelope signal as a function of the average power of the clock envelope signal.

High speed CMOS clock generator

Abstract: A -CMOS clock generator circuit is controlled by two clocks, one always going high before the other when entering an active cycle, and always going low before the other in entering a precharge cycle; this one clock precharges a capacitor through a P-channel transistor, and holds a drive node discharged. Two sets of semi-connected N-channel output transistors are used, with the gates of the top two driven by the drive node, and the gates of the bottom two driven by a CMOS inverter which has the second clock as its input. The inverter output also drives the gate of a P-channel transistor between the capacitor and the drive node. Another P-channel transistor with the first clock on its gate couples the drive node to the intermediate node of the first output pair. The second clock transfers the charge from the capacitor to the drive node, which also causes the capacitor to boot the drive node above the supply. When the first clock goes low it discharges the booted node to the supply rather than to ground.

Circuit arrangement for clock generation in communication installations, especially TDM digital exchanges.

Abstract: of EP01000761. A circuit arrangement for telecommunications systems, in particular PCM telephone exchange systems, with a duplicated exchange clock supply arrangement (CCG', CCG") in which the respective first of the two exchange clock generators supplies an exchange clock signal (T', T") which is generated independently of the respective other exchange clock generator, and the respective other (slave) exchange clock generator supplies an exchange clock signal which is synchronised so as to be at least approximately in phase with the exchange clock signal supplied by the respective first (master) exchange clock generator, and in which each of the two exchange clock generators, servo-synchronised by a supplied master clock signal (M', M"), generates an intermediate clock signal (H', H") with a clock period which at the maximum is equal to the maximum permissible phase difference between the exchange clock signals supplied by the two exchange clock generators, and in which, in each of the two exchange clock generators, the intermediate clock signal is supplied to a respective frequency divider (BKU, U) for the acquisition of the exchange clock signal, and in which the respective slave exchange clock generator compares its exchange clock signal with the exchange clock signal of the respective master exchange clock generator (PD) and when a phase difference is established which exceeds a limit value in the order of one intermediate clock period (h) by means of a regulating device in the case of a lagging slave exchange clock signal shortens-and in the case of a leading exchange clock signal lengthen-one half period of the slave exchange clock signal by the length of one intermediate clock period, and in which the exchange clock signal supplied by the respective master exchange clock generator is monitored and in the event of the failure thereof the regulating device of the hitherto slave exchange clock generator is disconnected, whereby the hitherto slave exchange clock generator now becomes the master exchange clock generator whose exchange clock signal is now supplied to the hitherto master exchange clock generator which has now become the slave exchange clock generator, characterised in that when it establishes a leading or lagging of the initially slave exchange clock signal the regulating device (UVR) of the initially slave exchange clock generator lengthens or shortens respectively the half period of the exchange clock signal supplied by itself with a time delay which is at least equal to the time interval required to disconnect the regulating device of the slave exchange clock generator in the event of the failure of the master exchange clock signal.

Phase shifting circuit for a clock signal

Abstract: 1 Phase shifting circuit for a clock signal in a clock signal generation circuit having a clock oscillator (OS) emitting the clock signal, a clock signal distribution circuit (SR) having a plurality of outputs and receiving the clock signal (11) emitted by the clock oscillator, and outputting at its outputs clock signals (T2, T3, Tn) derived therefrom, always at the same frequency and with mutually shifted phases lying in a fixed first grid, and having a control arrangement (STA) effecting the phase control which selects one of the outputs (eg T2) of the clock signal distribution circuit (SR), characterized in that the output of the clock signal distribution circuit selected by the control arrangement (STA) is connected to a delay line (LK) having a number of series-connected delay elements (L), which delay elements emit at the output side clock signals (L1, L2, , Li, Lm) with mutually shifted phases lying in a second grid narrower by a given factor with respect to the first grid, and in that in each case only one delay element (eg L2) of the delay line selected by the control arrangement (STA) outputs at the output side the clock signal that is phase-shifted by the clock signal distribution circuit (SR) and the delay line (LK)

Boosted phase driver

Abstract: An FET double boosted clock driver for producing a clock signal having an amplitude greater than the drain supply voltage. The clock output of a second clock driver is capacitively coupled to the clock output of a first clock driver. The second clock driver boosts the voltage on the source of an enhancement mode (output) FET of the first clock driver. The output FET has its gate connected to a bootstrapped node and its drain connected to a drain voltage source (VDD). A depletion mode FET forms a feedback path between the source of the output node FET and the bootstrapped node. When the bootstrapped node is bootstrapped to VDD+VT, the output FET precharges the clock output to VDD. When the potential of the clock output approaches VDD, the depletion mode FET discharges the bootstrapped node to an input clock. Thus, the potential of the gate of the output FET is clamped to the drain supply voltage when the output is subsequently boosted by the capacitively coupled second clock driver, without adversely effecting the timing and the precharging of the enhancement mode output FET.

Method and apparatus for fault testing a clock distribution network of a processor

Abstract: @ A method and apparatus for fault testing a clock distribution network (11) which provides a plurality of clock signal lines (25) to the logic networks (12) which comprise a data processor (10). The fault testing apparatus includes a decoder (24) for selecting one of the clock signal lines to be tested, and a test latch (40) which is clocked by the selected clock signal line. The selected clock signal line is tested by setting the test latch to a first logic value (e.g., binary ZERO) and maintaining a second value (e.g. binary ONE) at the test latch input. If the second logic value is stored in the test latch when the clock distribution network is inhibited, then a stuck-on fault is indicated for the selected clock signal line. If the second logic value fails to be stored in the test latch when the clock distribution network is enabled, then a struck-off fault is indicated for the selected clock signal line. Each clock signal line in the clock distribution network may be tested in this manner.

Internally gated variable pulsewidth clock generator

Abstract: This disclosure relates to a variable pulsewidth gated clock generator which is able to provide output clock signals with the same rise rate as an external driving clock with the output signal being varied in duration according to logic conditions within the integrated circuit. The circuit of the present invention as disclosed includes a latch which is set by the first phase of a two-phase clock to set the internal logic of the circuit to generate a large output signal during the second phase of the two-phase clock.

Integrated circuit for a clock or a clock radio with analog time display

Abstract: The subject matter of the invention is an integrated circuit for a clock or a clock radio with analog time announcement. The integrated circuit has a plurality of terminals for controlling and regulating the time-display means and an individual, bidirectional terminal for inputting a plurality of additional functions of the clock or of the clock radio, such as repeat waking, alarm triggering, automatic slumber setting etc., and for the purpose of triggering these additional functions. The integrated circuit itself contains an additional combinational network which is connected to the individual bidirectional terminal and contains a plurality of J/K flip-flops, to the inputs of which the input and output variables are applied via gate circuits for the purpose of inputting or triggering the additional functions.