Showing papers on "Clock gating published in 1985"

A self correcting clock recovery curcuit

Abstract: Conventional approaches to the problem of extracting clock from NRZ data do not automatically hold the clock in the center of the data eye. Other means must be used to keep the clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The circuit is both simple and self correcting.

A self correcting clock recovery circuit

Abstract: Conventional approaches to the problem of extracting clock from NRZ data do not automatically hold the clock in the center of the data eye. Other means must be used to keep the clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The circuit is both simple and self correcting.

Power-down circuits for dynamic MOS integrated circuits

Abstract: A power-down circuit for saving operational power dissipation of a dynamic MOS integrated circuit during idling conditions. A clock divider generates a divided clock signal in response to an internal clock signal inputted thereto. The divided signal is synchronized with the internal clock signal and has a repetition rate which is slower than that of the internal clock signal. A control circuit delivers the control signal when a triggering signal is inputted thereto. A clock selecting circuit transfers either the internal clock signal or the divided clock signal to the dynamic MOS integrated circuit in response to the control signal.

Fault-tolerant real time clock

Abstract: Three hardware real time clock subcircuits are connected in a triple modular redundancy configuration to assure continued operation if one subcircuit fails. A power supply or processor failure will not cause a clock supplying other processors to fail. Output of voted master clock pulses to the counter in every subcircuit is inhibited until all power supplies are turned on and stabilized, and the time base of the real time clock pulses is variable. The output pulses of all subcircuits are voted on and the voter output is the real time clock. The master clock can be the processor clock.

Self-checking digital fault detector for modular redundant real time clock

Abstract: A self-checking detector for detecting faults in a multiple redundant clock system includes a majority voter circuit for receiving the clock signals from the redundant clock circuits and for providing a voted output, a comparison circuit for comparing each of the clock signals with the voted output, and failure signal producing circuits responsive to the outputs from the comparison circuit for producing a first failure signal upon a clock failure being detected and for producing a second failure signal upon a failure of the majority voter being detected. The detector further includes power-up reset circuitry for inhibiting its operation during a power-up interval, and a reset circuit enabling either automatic or manual reset of the detector for verification of the detected fault.

Boost word-line clock and decoder-driver circuits in semiconductor memories

Abstract: A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.

CMOS d-type flip-flop circuits

Abstract: A CMOS D-type flip-flop circuit stage for avoiding the possibilty of feedthrough includes a non-overlapping clock generator section having a true clock output and a complement clock output. The flip-flop circuit includes a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate. The flip-flop circuit further includes a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate. The clock generator provides a two-phase non-overlapping clock for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.

Redundant synchronous clock system

Abstract: A synchronous clock circuit is provided on each module of an electronic digital system formed of a plurality of modules. Each clock circuit has two control pins which are used by control logic to determine whether or not the clock on a particular module is disabled, is operating as the master clock for the system, or is providing a backup function for the master clock. The common clock line is supplied through a buffer to the components on the module which require clocking. Logic circuitry on the backup clock mode insures the backup clock is in a ready condition in case there should be either failure of the master clock oscillator or if the master clock module is removed from the unit. All of the clock circuits of the different modules may be constructed in an identical manner, with the control of the function of the circuitry being provided simply by control of the logic level on the two terminals. A clock detecting time-out circuit is provided on each of the modules, which has a timing period which is slightly longer than the clock period. If the master clock fails to produce a clock pulse at the time that it should, the clock detect timing circuit, which is coupled to the buffer of the backup module, will sense that a failure has occurred and will control the turn-on of the clock circuit for the backup module.

Clock recovery apparatus and method for a ring-type data communications network

Abstract: A clock recovery apparatus provides a digital data stream from an incoming stream of raw data on a ring-type data com­ munications network. The apparatus employs a clock genera­ tor having a fixed operating frequency for providing a clock sig­ nal, a receiving circuitry for receiving the incoming data stream, a phase comparison circuit for comparing the phase of the incoming data stream with the clock signal, and a phase se­ lection circuit responding to the phase comparison circuit for discretely changing the relative phase difference of the data stream and the clock when the phase difference between them exceeds a predetermined phase tracking criterion. The clock is then employed for generating the digital data stream output. The output is preferably employed by a digital regenerator cir­ cuit which employs the same clock as used in the data clock re­ covery circuit. The apparatus can change the clock generator output phase, keeping the frequency fixed, or can insert a delay, of variable discrete increments, in the input data path.

Synchronous clock frequency conversion circuit

Abstract: A conversion system that provides compatibility between the internal system bus architecture of one computer and an external bus that operates on a different frequency includes a clock logic circuit for generating a clock signal that is synchronized with the internal clock for the computer system The clock circuit includes a delay line that provides a plurality of phase displaced signals at the operating frequency of the computer system Each of these phase displaced signals is multiplexed in accordance with the relationship of its phase to that of a signal at the clock frequency of the external bus By multiplexing the phase displaced signals in the appropriate manner, pulses are generated with a time period corresponding to that of the desired external bus clock frequency

Redundant clock combiner

Abstract: A redundant clock combiner device includes a clock selecting latch that recovers a clock signal even if both externally supplied clocks fail. The clock selection occurs, and an output clock provided, even if the non-prioritized clock signal is restored before the prioritized clock signal.

Clock acquisition indicator circuit for NRZ data

Abstract: A clock acquisition indicator circuit for NRZ "data", "which requires" two clock signals advanced and retarded by 90-degrees from the recovered clock. The circuit partitions each cycle of recovered clock into a half-cycle in which transitions should occur and a half-cycle in which transitions should not occur. The transitions ideally occur at only one instant in each cycle (when the clock goes positive), but the widening of the window to an entire half-cycle centered on this instant allows for phase noise on the NRZ data transitions and phase jitter in the recovered clock. The remaining half-cycle (which is centered on the instant when the clock goes negative) is a window during which transitions should not occur. The density of transitions in each of these windows is output as analog voltages which may be processed to determine the prevailing state from among three possible conditions.

CMOS logic circuit with single clock pulse

Abstract: A dynamic, multistage CMOS logic circuit is driven with a single source of clock pulses. The clock pulses operate odd-numbered stages. A static delay circuit provides clock pulses to even-numbered stages. The dynamic and static circuits are designed according to a discipline that guarantees the elimination of race conditions in the dynamic circuit despite the presence of uncontrollable variations in pullup and pulldown delays in the fabrication process.

Distributed clock synchronization in a digital data switching system

Abstract: A clock synchronization system in a digital data switching system, such as a digital PBX. The system has a local clock generating timing signals at a frequency greater than a nominal frequency, a circuit for lowering the local clock frequency and a comparator coupled to a second clock operating substantially at the nominal frequency for activating the lowering circuit so that the local clock is synchronized with the second clock. The system is distributed by placing the local clock and the lowering frequency on the control module of the switching system and placing the comparator to one or more of the line card modules which is receiving the second clock signals. Communication between the comparator and lowering circuit may be over a single line.

A New Discipline for CMOS Design: an Architecture for Sound Synthesis

Abstract: A number of logic forms and clocking schemes for cMOS integrated circuits are in common use. The most common logic form consists of two networks of transistors, the gates of which are connected to the input variables. An n-channel network defines the boolean condition under which the output is connected to ground (logic zero). A p-channel network defines the complementary condition under which the output is connected to a logical one. Since in many cMOS processes the output of a single pass transistor cannot be guaranteed to exceed the logic threshold of a typical inverter, pass transistor networks are either forbidden or a complementary transmission gate employing both p and n-channel devices is used. Clocking schemes for cMOS presently offer tradeoffs over a wide range in the risk vs efficiency space. In one scheme, a single phase clock and its complement are distributed, and used to control either transmission gates or transistors controlling power to the p and n-channel switching networks. Proper operation in either case requires that the logic delay of the stage exceeds the skew between the two clock lines. In a much safer approach, a two-phase clock is used, both the clock and its complement being distributed for each phase. In this case risk is eliminated at the expense of doubling the clock wiring. Yet another form is popular in gate-level designs. A single clock is distributed, and locally inverted at masterslave storage elements. Risk in this case is eliminated at the expense of a minimum storage element employing ten or more transistors. In this paper we describe a logic form that retains much of the simplicity, elegance, and compactness of the familiar 2-phase nMOS form, with the added advantage of fully static operation. Formal semantics for circuits implemented in this form are easily derived without detailed circuit or switch-level simulation.

Edge triggered clock distribution system

Abstract: A clock distribution system having a generator for generating a train of pulses, a transition circuit connected to the output of the generator for generating a clock signal having spaced apart transitions of a desired polarity, a distribution circuit distributing the clock signal to a plurality of boards which utilize the clock signal, and a flip-flop on each of the boards which utilize the clock signal Each of the flip-flops is connected to the distribution circuit for receiving the clock signal and for generating clock pulses which are defined by the spaced apart transitions

Clock signal arrangement for regenerating a clock signal

Abstract: A clock signal arrangement comprises two phase-controlled loop (PLL) circuits each producing a regenerated clock signal c and r, respectively and a high-frequency oscillator signal, two time window signal generators each connected to one of the PLL circuits and also a logic circuit connected to the time window signal generators. The clock signal arrangement has for its object the regeneration of a clock signal which has a very high degree of accuracy as regards its frequency and phase. To that end, time window signals whose mutual position is a measure of the phase difference between the regenerated clock signals and whose width depends on the period duration of the oscillator signals are generated in each of the time window signal generators. In the logic circuit the time window signals clock one of the clock signals, which is only conveyed to an output terminal of the clock signal arrangement if the phase difference is less than half the duration of the period.

Phase comparison procedure

Abstract: The invention concerns a procedure for phase and frequency comparison of two digital clock signals using a trigger circuit, which is set and reset alternately by signals derived from the two clock signals, and is characterised in that two dividers are provided, to divide the frequency of the two clock signals by m and n respectively, in that the divided clock signals are compared using the trigger circuit, which is alternately set and reset and in that blocking devices are provided, to block the divider outputs if the phase difference is greater than an amount x and in that the blocking is lifted to allow a pulse of one divided clock signal to pass if a pulse is generated for the other divided clock signal. The procedure enables current- or voltage-controlled oscillators in phase-locked loop circuits to be continuously controlled. A good use of the procedure is in circuits which require counter structures, since the dividers can be used as counters.

Apparatus and method for stabilizing the frequency of a clock signal generated by an on-chip clock generator

Abstract: @ For generating from a system clock a high frequency clock signal, the pulse generator has two consecutive delay lines (10a1, 10a3) and additional evaluating circuitry (10a4...10a12) to obtain the intermediate pulses in correct timing relationship with respect to the oroginal system clock pulses. Each of the consecutive system clock pulses propagates through the first (10a1) and into the second (10a3) delay line whose tap outputs are latched (11...L4) as delay indications when the next system clock pulse occurs. From tap outputs of the first delay line (PS, PN, PF) each system pulse can be obtained in several different time positions. The latched delay indications are evaluated in AND gates (10a6, 10a7, 10a8) to obtain three delay indicator signals (SLOW, NORM, FAST) of which only one is active. The delay indicator signals and the tap output signals of the first delay line are combined (10a9...10a12) to obtain an intermediate pulse that has a time position exactly between two consecutive system clock pulses.

Serial port synchronizer

Abstract: Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

Two clock boot circuit

Abstract: A plurality of circuit embodiments, implemented in MOS, for receiving two non-overlapping clock signals provide a booting function to each clock signal and in response to respective control signals directs one or the other of the booted clock signals to a single output line. The control signal for the first clock can change during the alternate second clock time and is stable during the first clock time. Similarly, the control signal for the second clock can change during the alternate first clock time and is stable during the second clock time. For both control signals, a low level enables the respective boot circuit.

Clock selection system

Abstract: PURPOSE: To improve the clock source by providing a circuit into a selector control device to produce the control signal which selects the transition or non-transition of the clock source according to the output state of the clock source. CONSTITUTION: A clock selecting part 2 selects a stable clock source CK1 or an ordinary clock source CK2 and the output of the part 2 is impressed to a using device 3. The outputs of both sources CK1 and CK2 are monitored by a clock monitor part 7 and a single signal, for example, is impressed to a selection controller 9 during the output of the clock. Then the clock selecting signal SEL 8 is applied to the controller 9 from outside and a circuit 9-1 is set into the controller 9 to select the output of the source CK1 or CK2 with the shift order. Then the output control signal is sent to the part 2 from the controller 9. Thus the selector 2 is actuated with the stable clock. COPYRIGHT: (C)1987,JPO&Japio

Autonomous power supply for observation device, in particular with stereoscopic effect

Abstract: The autonomous power supply for observation device with capacitive-effect electrooptical cells includes a low-voltage power source, clock or synchronization circuits, switches and circuits processing the clock signals or synchronization to control circuit creating intermittent high voltage.

Driving circuit for a shared sense amplifier with increased speed clock generation circuit for reading addressed memory cells

Abstract: A cut-off clock φ 5 generated by a cut-off clock generation circuit PG is supplied to a decode circuit DEC. The decode circuit DEC decodes the cut-off clock φ 5 to produce two types of cut-off clocks φ 5L and φ 5R . The two types of cut-off clocks φ 5L and φ 5R are supplied to a control clock generation circuit as shown in FIG. 3 or 11, which in turn produces control clocks φ 2L and φ 2R . The control clocks φ 2L and φ 2R are supplied to a shared sense amplifier of FIG. 1, to control on-off operations of transfer transistors 7 L , 8 L , 7 R and 8 R .

Clock system for control systems with digital information processing

Abstract: The invention relates to a clock system for control systems with digital information processing. The object of the invention is to implement a clock system for a control system with digital information generation in which a phase-synchronous processing of the digital information is carried out at the zero passage of the mains voltage of the power component, thereby minimising the cost of eliminating the effects of noise and thus of suppressing noise. … This is achieved by using a monoflop to shift the phase angle of the mains voltage, which is converted via optocouplers or transformers and threshold value switches into a square-wave voltage, in such a way that the clock coincides precisely with the zero passage of the mains voltage and the clock width is then set via a further monoflop.

Time base correction circuit

Abstract: A time base correction circuit for correcting time base error commonly present in two or more signals having components in different frequency bands, wherein the number of stages of the respective clock response delay elements is reduced A single clock generator supplies clock pulse signals for plural clock response delay elements The clock generator output is connected directly to the clock response delay element to which is applied the input signal having the highest frequency component Frequency dividers are connected between the clock generator and each of the other clock response delay elements

Boosted clock driver circuit

Abstract: An FET double boosted clock driver for producing a clock signal having an amplitude greater than the drain supply voltage. The clock output of a second clock driver (CLOCK 4) is capacitively coupled to the clock output of a first clock driver (CLOCK 38). The second clock driver boosts the voltage on the source of an enhancement mode (output) FET (T8A) of the first clock driver. The output FET has its gate connected to a bootstrapped node (N4) and its drain connected to a drain voltage source (VDD). A depletion mode FET (T7A) forms a feedback path between the source of the output node FET and the bootstrapped node. When the bootstrapped node is bootstrapped to VDD + VT, the output FET precharges the clock output to VDD. When the potential of the clock output approaches VDD, the depletion mode FET (T7A) discharges the bootstrapped node to an input clock (02). Thus, the potential of the gate of the output FET (T8A) is clamped to the drain supply voltage (VDD) when the output is subsequently boosted by the ca- pacltively coupled second clock driver, without adversely effecting the timing and the precharging of the enhancement mode output FET.

Multi-phase synchronizing circuit.

Abstract: A receiving clock phase synchronizing circuit in a signal transmission system in which a plurality of signal channels are time-incrementally multiplexed maintaining a clock pulse phase difference relative to one another. The clock pulse phase synchronizing circuit comprises a circuit (11) for detecting frame bits, a circuit (12) for generating gate signals to divide the individual channels, circuits (14-1, 14-2 and 14-3) which, responsive to said gate signals, reproduce discrimination clock pulses that correspond to each of the channels, and a circuit (15) that selects a reproduced discrimination clock pulse responsive to a gate signal and produces it. The synchronizing circuit generates discrimination clock pulses that are in synchronism in phase with each of the channels.