Showing papers on "Clock gating published in 1986"

Optical Clock Distribution To Silicon Chips

Abstract: Timing constraints for state-of-the-art very large scale integrated circuits (VLSI) in silicon are rapidly approaching communication limits available with layered two-dimensional metal and polysilicon wiring approaches. For such communication-limited systems, reliable clock distribution is a key concern. The range of finite differences in signal delays over clock wires of various lengths for large chips creates a timing skew that is significant when compared to the switching time of transistors in the circuit. The high bandwidth and three-dimensionality of imaging optical systems suggest that optical clock distribution systems have the potential to overcome the timing barriers presented by planar wiring. Clock signals can be holographically mapped to detector sites within small functional cells on a chip surface. Within each functional cell, the clock is distributed with negligible delays via surface wires, reducing skew effects to the variation in reaction times of the photodetectors on the chip. This paper includes the presentation of an optical clock distribution system assuming holographic mapping of beams from an off-chip optical source. Computer simulations of the electronic response of optical clock detection circuits in standard 4 µm CMOS technology have been performed.

Method for reducing effects of electrical noise in an analog-to-digital converter

Abstract: Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.

Master clock system for a parallel variable speed constant frequency power system

Abstract: A clock control system for a multiple channel electric power system includes a master clock circuit and control circuitry in each parallel connected channel. The channel control circuits are intially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.

Deterministic clock control apparatus for a data processing system

Abstract: A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a system clock for the system. The system clock includes a normal system clock signal and at least one early system clock signal. The basic clock is provided through a delay tap generating a normal basic clock signal and at least one early basic clock signal. In addition, a control state machine receiving the normal basic clock signal and the at least one early basic clock signal and responsive to the clock control signal is provided for starting and stopping the system clock. The clock control signal is synchronized with the earliest system clock and supplied to the clock control state machine.

Multiple redundant clock circuit

Abstract: In a data processing device which consists of a plurality of parallel-operating modules, each of the four modules is provided with its own clock circuit. Synchronization is realized at the level of the cycle of the high frequency oscillation. This is realized in that each of the clock circuits includes a two-out-of-three majority decision device which is fed by the output clock signals of the other three clock circuits. The majority decision may have a simple logic structure and is connected to the actual clock function generator in order to reduce, using a readjustment circuit, the deviation between the clock function signal and the majority signal by a factor substantially smaller than one for each transition of the majority signal.

Write circuit for an erasable programmable read only memory device of a microcomputer

Abstract: A write circuit for an EPROM device of a microcomputer comprises a first circuit (28) responsive to an external clock signal (WCLK) and machine clock signals (O 1 , O 2 ) for supplying a clock signal (CLK) to a program counter (23) of the microcomputer so as to successively increment an address produced in the program counter, where the external clock signal (WCLK) has a frequency lower than those of the machine clock signals (O 1 , 0 2 ) and the clock signal (CLK) has different frequencies during normal and write-in operation modes so that the address produced in the program counter (23) is successively incremented in synchronism with the machine clock signals (O 1 , 0 2 ) during the normal operation mode and is successively incremented in synchronism with the external clock signal (WCLK) during the write operation mode, and a second circuit responsive to the machine clock signals and the bit data of a LSB (least significant bit) of the address from the program counter for generating a bit line clock signal (BCLK) for inhibiting a write-in data from being written into the EPROM device during a time period in which the address changes

Automatic alignment of a synchronous data system using a local reference clock and external clock with an unknown delay between the two clocks

Abstract: An alignment circuit for use in a synchronous data transfer system for logically comparing the phase of a returned clock signal having an unknown phase relative to a local clock such that the local clock or its inverse can be used to retime returned remote data without the possibility of generating errors due to the lack of set-up time and hold time requirements for actuating a D flip-flop gate at its clock input with respect to the data arriving a the D input of the D flip-flop. The phase of the local clock relative to the return clock is detected and compared with a threshold phase shift value. If the phase shift is negligible, the remote data is clocked by the inverted local clock. If the phase shift exceeds the threshold value, the remote data is clocked by the local clock.

Digital integrated circuit

Abstract: A digital integrated circuit incorporates a plurality of multi-port flip-flop circuits which are interconnected by a plurality of gate circuits. A separate source of clock pulses is provided for each of the ports of the multi-port flip-flop circuits, and each clock pulse source is selectively effective to cause the multi-port flip-flop circuits to perform independent functions. During operation under one source of clock pulses, the flip-flops perform their ordinary function as D type flip-flops. During operation under another source of clock pulses, the flip-flops function as one or more shift registers in order to set the flip-flops to a predefined initial state in accordance with serial input data, and/or to provide serial output data in response to the state of the flip-flops following a preceding operation. When a further source of clock pulses is effective, a plurality of flip-flops may be connected to function as a random number generator or as a signature generator so as to perform repetitive operations such as cycling the address inputs of a ROM and providing output signals corresponding to the operation of the ROM.

Design methodology for stoppable clock systems

Abstract: Many approaches have been developed for designing large, highly parallel computer systems. Classical synchronous approaches are susceptible to synchronisation problems at the clock pulse level. Newer asynchronous approaches, on the other hand, avoid such problems but are expensive to implement. This paper proposes a compromise approach that builds on the well developed synchronous system design techniques and, at the same time, avoids the clock pulse level synchronisation problems. In this approach, a system has a totally synchronous core with a 'stoppable' clock and uses an asynchronous interface for external communication. With the clock not running, the asynchronous interface receives and sends information in the form of packets, setting up the proper input values and initial state for the synchronous core. The clock is then started, and the synchronous core behaves as a sequential state machine initialised to the proper state and subjected to the proper input values. When the core has finished its computation, the clock is stopped and the process is repeated. A methodology for building such systems is presented in the paper.

Digital/analog phase-locked oscillator

Abstract: A phase-locked oscillator (PLO) driven or derived clock system, the frequency of which is higher by a factor N than the frequency of the bit reference clock of incoming streams of data bits. The derived clock is designed to be maintained in synchronism with the bit reference clock. Two counters are provided, both of which are driven by the derived clock. The reference counter counts to N/2 and outputs a pulse. The other counter counts to N, outputs a pulse and starts again. The two counters provide output pulses which are coincident whenever the derived or PLO clock is in synchronism with the data clock. This is determined by a phase detector which includes a pair of identical latches, each of which is set by one of the two counters. The outputs of the latches go to an AND gate, the output of which resets the latches. The outputs on the two Q leads from the latches go to an amplifier which outputs a signal which is other than zero, only when there is lack of synchronism. This signal can be positive or negative, depending on which clock leads or lags the other one. The output of the amplifier controls a voltage controlled oscillator so that the derived clock will be maintained in synchronism with the incoming data.

Integrated circuit clock bus layout delay system

Abstract: A clock bus system fabricated on an integrated circuit for distributing a train of clock pulses to circuit elements on the integrated circuit. An input terminal is connected to receive a train of clock pulses. All of the circuit elements are circumscribed by a clock bus which is also coupled to each of the circuit elements. A plurality of distribution legs which include clock bus drivers are coupled to the input terminal by conductors and provide the train of clock pulses to the clock bus at spaced-apart locations. The distribution legs coupled to the input terminal by shorter conductors include delay elements for delaying the clock pulse train by time periods corresponding to the delay inherent in longer conductors. The clock pulse trains provided to the clock bus by the distribution legs are thereby synchronized with respect to each other.

Method and circuit arrangement for switching over a clocked device having multiple operating states

Abstract: At least two by a selection signal (AW) selected operating states by turning on a respective one individual clock signal sequence (CL1 or CL2) control A change of the selection signal (AW) is initially ineffective until the next clock edge of a particular direction at the previously selected clock signal sequence (eg. B . CL1) has occurred. The case occurred clock signal state is maintained until the next clock edge the same direction now is in the allocated state to be activated operating clock signal sequence (CL2) occurred. Now this clock sequence (CL2) is applied to the clock-controlled device (DEV) connected through. This type of delayed switching secures each complete clock periods in the switched clock signal (CL) even when asynchronously occurring to change the selection signal (AW).

Clock control system for network synchronization

Abstract: PURPOSE: To attian the synchronizing control of an equipment connected always to a communication system by detecting the absence of a network synchronization clock so as to apply a prescribed fixed voltage to a clock source, thereby generating the clock internally. CONSTITUTION: The network synchronizing clock and a feedback clock from a clock source 101 are subjected to phase comparison by a phase comparing means 102, a control voltage from the means 102 is supplied to output a clock synchronously with the network synchronizing clock from the clock source 101. On the other hand, when the absence of the network synchronizing clock is detected by an input interruption detection circuit 103, a changeover means 104 selects a fixed voltage similar to the control voltage from the means 102 generated from the clock source 101 to supply the clock synchronously with the network synchronizing clock to the clock source 101. Thus, even when the network synchronizing clock is absent, the synchronizing clock is generated synchronously with the network synchronizing clock in the inside of the equipment and the equipment connected to the communication system is subjected to excellent synchronization control at all times. COPYRIGHT: (C)1988,JPO&Japio

Interconnected multiport flip-flop logic circuit

Abstract: A digital integrated circuit incorporates a plurality of multi-port flip-flop circuits which are interconnected by a plurality of gate circuits (3,4,8,9). A separate source of clock pulses is provided for each of the ports of the multi-port flip-flop circuits, and each clock pulse source is selectively effective to cause the multi-port flip-flop circuits to perform independent functions. During operation under one source of clock pulses, the flip-flops perform their ordinary function as D type flip-flops. During operation under another source of clock pulses, the flip-flops function as one or more shift registers in order to set the flip-flops to a predefined initial state in accordance with serial input data, and/or to provide serial output data in response to the state of the flip-flops following a preceding operation. When a further source of clock pulses is effective, a plurality of flip-flops may be connected to function as a random number generator or as a signature generator so as to perform repetitive operations such as cycling the address inputs of a ROM and providing output signals corresponding to the operation of the ROM.

Method and circuit for driving a stepping motor

Abstract: A method and circuit for driving a stepping motor which is driven by a motor clock output having a time variable frequency. So as to generate the time varying frequency, the constant frequency of a basic clock output is divided by constant first factor and is multiplied by a time variable second factor which is in the range between zero and the first factor. A transfer clock sequence is derived from the basic clock output by a division factor. The second factor is changed by a prescribed increment with the frequency of the transfer clock output at the respective clock times and this prescribed increment determines the frequency change of the motor clock output per clock interval. In this manner, the unavoidable frequency discontinuities can be maintained small and constant over the full frequency range of the motor clock output even by when the frequency of the basic clock output is not high whereby a reliable run-up and a reliable braking of the stepping motor are assured without stepping errors.

Variable clock bus system

Abstract: PURPOSE:To improve the efficiency of data transfer by providing a variable period clock generating means and a means selecting the period of a clock signal to be used for each data transfer depending on the condition of the data transfer. CONSTITUTION:The variable period clock generating means 4 revising the clock period dynamically during the operation of the bus is provided as the supply source of a common clock for a synchronizing bus and means 3a, 2b, 2c selecting the clock period depending on the condition of data transfer is provided. The conditions of data transfer are such as distance between devices, data transfer speed of the device and the frequency of use in the bus. Thus, the clock with an optimum period is used for the data transfer distance, data transfer speed of the device or the degree of busy state of the bus in each data transfer. For example, in case of the nearby data transfer, the clock signal with a short period is used for high speed transfer and in case of the remote data transfer, the clock with a long period is used to attain low speed transfer.

System for adjusting clock phase

Abstract: A logic circuit equipped with a scan in/out means that is provided with n+p specific scan in/out latch circuits. A first delay means which selectively generates input clocks as delay clock signals of a maximum of m = 2n steps according to selection signals of n bits, is connected in cascade with a second delay means which selectively generates input clock signals as delay clock signals of a minimum step of 1/2p times as small as the width of a minimum step of the clock signals by said first delay means, according to selection signals of p bits. By setting selection data to said n+p scan in/out latch circuits, any delay clock signal can be obtained that is delayed by a given 1/2p step relative to the input clock signal.

Transmission and reception of synchronous data and timing signals using a steady bit stream

Abstract: In an telecommunications switching system, user clock data is "massively sampled" at the source node with reference to a global clock signal, and reconstructed with no more than allowable error at the destination. Massive sampling and reconstruction of the clock signal allows users of the transmission system to send data at arbitrary data rates and to perform their own clock synchronization at a different protocol level from the hardware switching system. Direct use of the global system clock rate of approximately 192 kilobits per second (kbps) is provided for by synchronizing the user data with the global clock signal.

Access port clock synchronizer

Abstract: Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

Circuit for the clock recovery of an isochronous binary signal.

Abstract: of EP0202597The circuit described is an improvement of a known circuit for recovering the clock of an isochronous binary signal, in which set pulses are generated in dependence on the change of edges of the binary signal by a delay circuit and a comparison circuit, which reset a counter, the counter being clocked by a clock source, the frequency of which is a multiple of the clock frequency to be recovered. In the known circuit, missampling by means of the recovered clock is not impossible if the binary signal is very noisy and/or contains long sequences of identical binary values. To eliminate this deficiency, an output of the counter, at which a clock with the nominal frequency of the clock to be recovered is present, is connected to the input for the guide variable of a phase-locked loop and the output variable of the phase-locked loop is used as recovered clock.

Clock signal control circuit

Abstract: A clock signal circuit receives first and second clock signals (CLOCK 0, CLOCK 1) the pulses of which are non-overlapping with respect to each other. The first and second clock signals (CLOCK 0, CLOCK 1) are applied to the source-drain paths of respective first and second MOS transistors (36, 40), the gate electrodes of which are coupled via the source-drain paths of third and fourth MOS transistors (34, 38) to the outputs of respective first and second NOR gates (31, 32) receiving the second and first clock signals, respectively, and also receiving first and second control signals. The outputs of the NOR gates (31, 32) are further connected to a third NOR gate (42) having an output connected to the gate electrode of a fifth MOS transistor (44) connected to an output line. In operation, selected, booted clock signals are supplied to the output line.

Method and apparatus for changing synchronizing clock

Abstract: PURPOSE: To prevent malfunction of each part of the circuit used for the titled apparatus by using a clock supplied to the 1st input terminal normally as a master clock and using a substitution clock as the master clock in switching the frequency of the master clock. CONSTITUTION: A dot clock pulse DCK and a substitution clock pulse FCK are supplied to input terminals A, B of a selector 20 via terminals T 1 , T 2 . In switching the frequency of the clock DCK supplied to the 1st input terminal B, the clock FCK is used with switching. While the clock FCK is used as the master clock, the clock DCK supplied to the 1st input terminal B is switched and then the clock DCK supplied to the 1st input terminal B is outputted as the master clock. Thus, in switching the frequency of the master clock. The level period of the active side of the master clock is not decreased and the malfunction of each part of the circuit is prevented. COPYRIGHT: (C)1988,JPO&Japio

A Monolithic 1 to 50 MHz CMOS Clock Recovery and Retiming

Abstract: This paper describes a novel single-chip design of a clock recovery and data retiming circuit. The chip, when used on the receiving end of a serial data link, recovers a clock from NRZ random data transmitted at any bit rate between 1 and 50 mb/s and synchronizes the clock with the data stream. The chip has been fabricated using a 1.75 micron twin-tub CMOS process and is packaged in a 20 pin plastic DIP which dissipates 250 mW with a single 5.0V supply. In serial data link applications, the chip can be exploited as an inexpensive and easy-to-use standard component to replace many HIC and PCB designs of clock recovery circuits that generally require several discrete components, expensive resonant elements, manual adjustments, and occupy large board space.

Repeater for triplicated clock distribution

Abstract: Repeater for each triplicated clock distribution clock (OE1, OE2, OE3) supplying a clock and synchronization signal, the clock signal having a synchronizing signal consisting of a negative pulse and a positive pulse each having a duration eglae the period of the clock signal, a clock being connected by at least one repeater to a receiver. A repeater comprises an inverter (1), an inverting circuit (2), a test circuit (3), a refund and shift circuit (4) and a regeneration circuit (5). The test circuit performs a test of the duration of the pulses to detect the synchronization signal and outputting a pulse upon detection. The recovery circuit delivers a pulse of eglale duration a pulse of the synchronization signal, shifted by two periods of the clock signal. The reverse inverting circuit the forehead between the two pulses of the synchronization signal and the clock generating circuit outputs a clock and synchronization signal (HMR) at the output of the repeater.