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Showing papers on "Clock gating published in 1987"


Journal ArticleDOI
TL;DR: The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted, which has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed.
Abstract: The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed. Several examples are demonstrated.

240 citations


Journal ArticleDOI
TL;DR: Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz and an accurate phase relationship between the off-chip reference clock and the internal clock signals is obtained.
Abstract: The design of clock generation circuitry being used as a part of a high-performance microprocessor chip set is described. A self-calibrating tapped delay line is used to generate four nonoverlapping clock phases of a system clock. A charge-pump phase-locked loop (PLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between the off-chip reference clock and the internal clock signals. Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz.

221 citations


Patent
30 Dec 1987
TL;DR: In this article, the authors proposed a data-clock for data processing circuitry by developing an optimum locally generated clock signal which is selected with each received data message, which is achieved by utilizing a local crystal clock (10) which serves as an input to a multiple active parallel tap delay line (16).
Abstract: The present invention generates a data-clock for data processing circuitry by developing an optimum locally generated clock signal which is selected with each received data message. This is achieved by utilizing a local crystal clock (10) which serves as an input to a multiple active parallel tap delay line (16). A register (34) has the various delay signals input to it and a window generator (36) strobes (42) the inputs to the register so as to process the strobed levels of the various delayed clock signals. This is done to detect a level transition in any of the clock phases. Gating circuitry (26, 28) then chooses an optimum clock phase which has undergone a transition in a desired direction during the time window when the various clock phases were strobed. As a result of the present invention, utilized bandwidth may be increased and data distortion is minimized so that the number of stations connected to a data bus provided with the data clock of the invention may be increased substantially.

74 citations


Patent
19 May 1987
TL;DR: In this paper, a clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream, which is formed by frequency dividing the stable clock.
Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.

57 citations


Patent
12 Jan 1987
TL;DR: In this paper, a clock circuit for supplying a clock signal 62 to a data processor 10 is arranged to supply the clock signal at one of a range of frequencies, under the control of the data processor.
Abstract: A clock circuit for supplying a clock signal 62 to a data processor 10 is arranged to supply the clock signal at one of a range of frequencies, under the control of the data processor. The processor can instruct the circuit to supply the clock signal at a maximum frequency to provide maximum data processing capacity or it can instruct it to supply a signal at a selected lower frequency in order to reduce power consumption. The effect of the processor can be overridden by an external event, e.g. an interrupt 20, which forces the clock circuit to produce the clock signal at the maximum frequency in order to minimise the delay in processing the interrupt. The clock circuit includes synchronisation circuitry for ensuring that the clock frequency is changed without generating a glitch.

47 citations


Patent
Clasen Peter-Michael1
16 Oct 1987
TL;DR: In this paper, a system clock is produced either from clock signals (t1) recovered in a clock regenerator, based on surface wave filtered technology and having level fluctuations, or from the digital clock signals internally generated in an access controller of a ring network, in response to the level of the regenerated clock signals.
Abstract: A system clock is produced either from clock signals (t1) recovered in a clock regenerator, based on surface wave filtered technology and having level fluctuations, or from the digital clock signals (t2) internally generated in, for example, an access controller of a ring network, in response to the level of the regenerated clock signals (t1). The change in the source of the system clock is accomplished after an early detection of the level fluctuations, so that the clock signal (t1,t2) currently connected to the clock line are disconnected and, after a short delay time, the other clock signal (t1,t2) is sychronously switched to the clock line.

43 citations


Patent
20 Nov 1987
TL;DR: In this paper, a clock frequency divider is proposed for generating a basic clock signal which provides operation timing for a semiconductor integrated circuit operating in accordance with a program. But it is not suitable for the use of hardware clocks.
Abstract: A clock frequency divider for generating a basic clock signal which provides operation timing for a semiconductor integrated circuit operating in accordance with a program. The clock frequency divider comprises a frequency-dividing factor register for storing a frequency-dividing factor which can be rewritten by the program, and a frequency-dividing circuit for frequency-dividing a source clock signal having a fixed frequency in accordance with the frequency-dividing factor stored in the frequency-dividing factor register, whereby a basic clock which provides a processing rate optimum for a program to be executed being obtained.

31 citations


Patent
Hanta Nadateru1
05 Jan 1987
TL;DR: In this article, a method and apparatus for diagnosis of a logical circuit including a combinational logical circuit or a semiconductor memory and having its input and output terminals respectively connected to input-and output latches which are operated by the same clock pulse contained in a single-phase clock signal is presented.
Abstract: In a method and apparatus for diagnosis of a logical circuit including a combinational logical circuit or a semiconductor memory and having its input and output terminals respectively connected to input and output latches which are operated by the same clock pulse contained in a single-phase clock signal, diagnostic data is transferred to the diagnosed circuit through the input latches by the rise of one clock pulse in the clock signal, an output signal delivered out of the diagnosed circuit is latched into the output latch by the fall of the one clock pulse, and the latched data is compared with expected data to diagnose the logical circuit. Use of a clock signal containing clock pulses of a relatively large width can be permitted for diagnosing the logical circuit which is operating at a high operation speed.

31 citations


Patent
10 Dec 1987
TL;DR: In this article, a clock holdover circuit is proposed to provide a replacement clock signal within predetermined parameters independently of time and temperature variations, and the clock is phase compared to the reference signal so that no loss of phase occurs.
Abstract: The present invention provides a clock holdover circuit which will provide a replacement clock signal within predetermined parameters independently of time and temperature variations. The circuit of the present invention has only a single component which is time and temperature dependent. By selecting the components parameters to be within the desired tolerances, the accuracy of the circuit is maintained. In the present invention, digital circuitry is combined with an accurate local crystal frequency source to provide a replacement clock signal. The present invention allows phase consistency upon loss of a reference clock signal as well as on return of the reference clock signal. A reference clock signal is phase locked to a VCO to produce a desired output. The frequency of the output is compared to a local frequency standard to generate an offset frequency used to control a frequency synthesizer. The offset frequency is digitally stored. Upon loss of the reference clock signal, the stored offset frequency is used to drive the frequency synthesizer along with the local frequency standard so as to provide an acceptable replacement clock signal. The frequency comparator, storage, and synthesizer are all digital so as to be time and temperature independent. The local frequency standard is crystal based having known time and temperature tolerances. By choosing a local frequency standard having tolerances within a predetermined range, an acceptable clock holdover signal may be provided indefinitely. The replacement clock signal is phase compared to the reference clock signal so that no loss of phase occurs upon reference loss.

30 citations


Patent
23 Oct 1987
TL;DR: In this article, the clock skew measurement can be improved by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip, which can be used to measure clock skew.
Abstract: This application teaches that more accurate measurements of clock skew can be had by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip.

27 citations


Patent
Yarsun Hsu1, Hungwen Li1
19 Jun 1987
TL;DR: In this paper, a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to assign skew-sensitive activities, such as read, write, and operate, conform to respectively assigned edges.
Abstract: Using a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately longer durations for longer data transfers in an array processor of myriad processing elements. There is no need to allow sufficient time in every clock cycle for worst case data transfer between remote processing elements. The clock waveform has three recognizable edges (A,B,C) regardless of loss of sharpness during its travel to the various processing elements. The convention that three skew-sensitive activities, READ, WRITE and OPERAND SUPPLY conform to respectively assigned edges as follows: A=READ; B=OPERAND SUPPLY; C=WRITE (Read next) The processing elements synchronize with the clock waveform, which is optimized for the instructions of the program being executed. There is no time wasted allowing for worst case data transfers possible in certain instructions but not possible in other instructions.

Patent
25 Feb 1987
TL;DR: In this paper, a multi-stable stage and an output logic stage are introduced to enable two clock elements to produce a single stream of timing pulses, without interruption, when both elements are operating normally, and when one element fails.
Abstract: Computer timing apparatus enables two clock elements to produce a single stream of timing pulses, without interruption, when both elements are operating normally, and when one element fails. The apparatus incorporates a multi-stable stage and an output logic stage. The multi-stable stage detects state transitions in the input signals of each clock element and generates a corresponding clock-tracking signal which can disable the output of the corresponding clock from propagating through the output logic. The output logic stage logically combines each clock signal with its corresponding clock-tracking signal, and logically combines the resultant signal to produce a single stream of output signals responsive to a next transition produced by either of the two clock elements.

Patent
12 Jun 1987
TL;DR: In this article, a switching circuit for selecting between first and second clock signals is described, where the second clock signal is selected in synchronism with the beat of the first clock signal.
Abstract: A switching circuit is described, for selecting between first and second clock signals. When it is desired to switch from the first to the second clock signal, the first clock signal is de-selected in synchronism with the beat of the first clock and then, after a delay, the second clock signal is selected in synchronism with the beat of the second clock. Conversely, when it is desired to switch from the second to the first clock signal, the second clock signal is de-selected in synchronism with the beat of the second clock and then, after a delay, the first clock signal is selected in synchronism with the beat of the first clock. This avoids the possibility of a short pulse or "glitch" at the instant of switch-over.

Patent
29 Apr 1987
TL;DR: In this paper, a phase-locked loop divider is used to change the phase of the internal control signal to match the phases of the newly selected reference, thereby eliminating timing changes on the system clock bus.
Abstract: CLOCK CONTROL CIRCUIT FOR PHASE CONTROL Abstract There is disclosed a clock circuit for a PBX system that uses phase locked loop technology to perform synchronization between two input signals. The system can switch between different reference sources without introducing error and without requiring the entire circuit to become realigned with the phase of the newly selected reference signal. This is accomplished with a phase build-outcircuit that uses a phase locked loop divider to change the phase of the internal control signal to match the phase of the newly selected reference thereby eliminating timing changes on the system clock bus. The system can also be used to change between redundant clock circuits.

Patent
Sabine Stronski1
31 Aug 1987
TL;DR: A clock generator for CMOS circuits for producing two nonoverlapping internal clocks or timing cycles at two clock outputs is presented in this article, where the clock generator has a frequency divider energized by an oscillator and having an output side, and a bistable multivibrator connected to the output side of the frequency dividers and having complementary outputs includes an equal number of inverter-driver stages connected to each of the complementary outputs.
Abstract: A clock generator for CMOS circuits for producing two non-overlapping internal clocks or timing cycles at two clock outputs, the clock generator having a frequency divider energized by an oscillator and having an output side, and a bistable multivibrator connected to the output side of the frequency divider and having complementary outputs includes an equal number of inverter-driver stages connected to each of the complementary outputs and being controllable thereby, the driver stages being dimensioned asymmetrically

Patent
27 May 1987
TL;DR: In this article, a fundamental interval of time is derived from a clock signal of an inherent frequency emanating from an untrimmed crystal oscillator, which is used to control and modify the time interval between interrupt signals generated upon the occurrence of a specified count of clock cycles.
Abstract: A fundamental interval of time is derived from a clock signal of an inherent frequency emanating from an untrimmed crystal oscillator. Firmware and hardware of the time-of-day clock system are used to control and modify the time interval between interrupt signals generated upon the occurrence of a specified count of clock cycles of the clock signals emanating from the crystal oscillator.

Patent
28 Oct 1987
TL;DR: The clock signal generator for nonoverlapping polyphase clock pulses having no overlapping period of time where the clock pulses have a high level at the same time is described in this article.
Abstract: The clock signal generator for generating non-overlapping polyphase clock pulses having no overlapping period of time where the clock pulses have a high level at the same time, comprises a clock signal generation control means provided for each of the polyphase clock pulses so that a clock signal on a signal path where the largest delay is caused among at the signal paths of one phase is used to prevent clock signal generation in the other phases.

Journal ArticleDOI
TL;DR: In the letter, a new clock recovery circuit with self-correction of the position of the retiming clock is presented, which shows the reduction of the output jitter by deleting the phase difference of ?
Abstract: In the letter we present a new clock recovery circuit with self-correction of the position of the retiming clock, which shows the reduction of the output jitter by deleting the phase difference of π radians in the output of the phase detector existing in Hogge's scheme

Patent
19 Mar 1987
TL;DR: In this article, a possible surge current which can develop during power initialization of CMOS circuit arrangements (10) or at other instances, because of loss of an actual clock signal (from 15), is eliminated by controllably supplying an alternate clock signal to the CMOS devices in the circuit during intervals in which the real clock signal is absent.
Abstract: A possible surge current which can develop during power initialization of CMOS circuit arrangements (10) or at other instances, because of loss of an actual clock signal (from 15), is eliminated by controllably supplying an alternate clock signal (via 11, 14) to the CMOS devices in the circuit (10) during intervals in which the actual clock signal is absent. The presence or absence of the actual clock signal is monitored (via 12) continuously and when present, the actual clock signal (from 15) is controllably supplied (via 14) to the CMOS devices (10) in place of the alternate clock signal.

Patent
Takashi Ibi1
18 Dec 1987
TL;DR: In this paper, a gated clock signal is generated from a free-running clock signal having a predetermined constant period of time. But it is generated by a single pulse with an interval longer than the period of the free running clock signal in a single clock mode, and the trigger signal has the same timing synchronized with a specific phase of the gated signal at which a phase of an address register is switched to hold a new address.
Abstract: An apparatus for reading data from a memory in a computer system includes: an address register for holding an address to be supplied to the memory, a read data register for holding data read out from the memory and a device for generating a gated clock signal from a free-running clock signal having a predetermined constant period of time. The gated clock signal is free-running with the predetermined constant period of time in a normal clock mode but is generated by a single pulse with an interval longer than the period of the free-running clock signal in a single clock mode. A device, having serially connected plural registers for shifting a trigger signal in accordance with the free-running clock signal generates a read data clock signal. The trigger signal has a same timing synchronized with a specific phase of the gated clock signal at which a phase of the address register is switched to hold a new address to be supplied to the memory. The shifted trigger signal is fed to the read data register for hodling the data read out from the memory.

Patent
20 Jul 1987
TL;DR: In this article, a clock generator circuit for an integrated circuit which is controlled by clock signals obtained by frequency-dividing a standard clock is presented, where three flip-flops, two of which are connected in series, and two logical gates together form a synchronization circuit such that when a command signal is inputted to start testing the integrated circuit, frequency-divided clock signals in synchronism with the standard clock are outputted.
Abstract: A clock generator circuit of this invention is for an integrated circuit which is controlled by clock signals obtained by frequency-dividing a standard clock. Three flip-flops, two of which are connected in series, and two logical gates together form a synchronization circuit such that when a command signal is inputted to start testing the integrated circuit, frequency-divided clock signals in synchronism with a standard clock are outputted.

Patent
18 Aug 1987
TL;DR: In this article, a short-circuit monitor can be controlled by the clock generator and becomes effective during the clock-pulse generation in order to identify reliably a short circuit on the electrical load.
Abstract: In the case of a device for controlling the power of an electrical load, especially in motor vehicles having an electrical power source, having a clock generator, having an output stage which receives the clock pulses from the clock generator and has a switch in series with the electrical load, and having a short-circuit monitor which measures the voltage at the junction point of the electrical load and opens the switch if the voltage exceeds a predetermined threshold value, the short-circuit monitor can be controlled by the clock generator and becomes effective during the clock-pulse generation in order to identify reliably a short circuit on the electrical load.

Patent
09 Jun 1987
TL;DR: In this paper, the authors proposed to correct the phase dissidence due to external noise and to supply a clock pulse with less waveform distortion at the input by providing a frequency division circuit and a synchronizing section so as to make the duty ratio as 1:1 and making the phase coincident with each other.
Abstract: PURPOSE: To correct immediately the phase dissidence due to external noise and to supply a clock pulse with less waveform distortion at the input by providing a frequency division circuit and a synchronizing section so as to make the duty ratio as 1:1 and making the phase coincident with each other. CONSTITUTION: An original oscillation clock pulse with a prescribed period outputted from an original oscillation section 1 is given to frequency division circuits 2a∼2x provided closely to each of plural clock pulse supply destinations. The circuits 2a∼2x invert their outputs synchronously with the leading or trailing edge of the original oscillation clock pulse to be inputted and output a clock pulse having a period of prescribed multiple of the original oscillation clock pulse and duty ratio of 1:1. Then a phase dissidence detection section 3 detects the dissidence of the phase of the clock pulses outputted by the circuits 2a∼2x and the synchronizing section 4 in response to the detection brings the internal state of the circuits 2a∼2x into the same state at the same time thereby making the phase coincident. Thus, the clock pulse with less waveform distortion is supplied at the input and the phase dissidence due to an external noise is corrected immediately. COPYRIGHT: (C)1988,JPO&Japio

Patent
03 Jun 1987
TL;DR: In this paper, a switching circuit for selecting between first and second clock signals (CLKA,CLKB) is described, where the second clock signal is selected in synchronism with the beat of the first clock.
Abstract: A switching circuit is described, for selecting between first and second clock signals (CLKA,CLKB). When it is desired to switch from the first to the second clock signal, the first clock signal is de-selected in synchronism with the beat of the first clock and then, after a delay, the second clock signal is selected in synchronism with the beat of the second clock. Conversely, when it is desired to switch from the second to the first clock signal, the second clock signal is de-selected in synchronism with the beat of the second clock and then, after a delay, the first clock signal is selected in synchronism with the beat of the first clock. This avoids the possibility of a short pulse or "glitch" at the instant of switch-over.

Patent
18 Aug 1987
TL;DR: In this article, a clock voltage supply for electronic control circuits such as a computer system for generating four clock signals which are synchronous as to frequency and phase is presented. But the clock signals can continue to appear even if one of the four clocks is malfunctioning.
Abstract: A clock voltage supply for electronic control circuits such as a computer system for generating four clock signals which are synchronous as to frequency and phase. When n=4, the clock signals are generated with the help of four PLL clocks. So that the four clock signals can continue to appear even if one of the four clocks is malfunctioning, the clock signals of the four clocks are supplied to four (3:4) voters from whose outputs the clock signals are then supplied. Since each voter circuit brings about a certain delay time, which significantly limits the frequency of the clock signals, a delay element is connected downstream to each of the voter outputs respectively. The delay time of the respective delay element, plus the delay time of the respective voter connected therewith, is an integral multiple of the period of the intended clock frequency. For PLL control, the output of each delay element gives the nominal phase position and the output of each clock gives the actual phase position.

Patent
Leonard Jan Maria Esser1
23 Nov 1987
TL;DR: In this paper, a charge-coupled device of the accordion type provided with a shift register for supplying accordion clock voltages on the one hand and with clock lines for supplying conventiional clock voltage on the other hand is described.
Abstract: The invention relates to a charge-coupled device of the accordion type provided with a shift register for supplying accordion clock voltages on the one hand and with clock lines for supplying conventiional clock voltages on the other hand The electrodes are alternatively coupled to the shift register and to the clock lines The dissipation can be considerably reduced in this device Moreover, the transport direction can be reversed in a simple manner, which is of importance, for example, in image sensors for smear suppression

Patent
20 Mar 1987
TL;DR: The master clock signal MCLK in the selector 2 and the clock signal CLK being the result of frequency-dividing the master clock are switched synchronously in outputting them switchingly and no high frequency pulse is generated.
Abstract: PURPOSE: To prevent the production of a high frequency pulse at switching by synchronizing a switching signal to output switchingly a master clock signal and a clock signal being the result of frequency-dividing the master clock signal with the master clock signal. CONSTITUTION: A frequency divider circuit 1 frequency-dividing a master clock signal MCLK, a selector 2 switching the signal and a clock signal CLK being the result of frequency-dividing the master clock by the said circuit and a synchronizing circuit 3 synchronizing a switching signal INT with the master clock signal MCLK and applying the result to the selector 2 are provided. The switching signal INT is synchronized with the master clock signal MCLK by the circuit 3 and the result is fed to the selector 2. Thus, the master clock signal MCLK in the selector 2 and the clock signal CLK being the result of frequency-dividing the master clock are switched synchronously in outputting them switchingly. Thus, no high frequency pulse is generated. COPYRIGHT: (C)1988,JPO&Japio

Patent
01 May 1987
TL;DR: In this article, a synchronous timer anti-alias filter gain stage utilizing switched capacitor circuitry is described, where a high frequency sampling clock is used for a switched capacitor anti-aliasing filter.
Abstract: A synchronous timer anti-alias filter gain stage utilizing switched capacitor circuitry is described. A high frequency sampling clock is used for a switched capacitor anti-alias filter. In the preferred embodiment, a clock of approximately 921.6 kilohertz is utilized. This fast clock is divided down by a programmable timer into a low frequency sampling clock to drive a signal gain stage. The programmable divide values are integers so that the anti-alias filter clock and gain stage clock are in an integer relationship with each other for edge locking. The high frequency clock is divided down by a fixed divider to provide a clocking signal to an input band pass filter. The fixed divide value is also an integer so that the band pass filter clock and anti-alias filter clock are in integer relationship with each other. Switched capacitor anti-alias filters are used in place of continuous time, R-C anti-alias filters. The switched capacitor anti-alias filter has greater accuracy than R-C filters, approaching the range of 0.2% accuracy of the time constant. In addition, the switched caapcitor anti-alias filter requires less silicon area than equivalent R-C filters in integrated cirucit implementations. DC offsets are eliminated by preceding and following the gain stage by first order high pass filters. The programmability of the low frequency sampling clock rate, by changing the divide values, allows the received baud rate to be tracked in modem applications.

Patent
Adolf Ballweg1
08 Sep 1987
TL;DR: In this article, a comparator identifies the beginning and presence of a start of packet information after a series-to-parallel conversion of the data bit stream, whereby filler information are transmitted between the packets.
Abstract: In a terminal equipment connected to a packet-oriented, ring-shaped network, a comparator identifies the beginning and the presence of a start of packet information after a series-to-parallel conversion of the data bit stream, whereby filler information are transmitted between the packets. With the recognition of the beginning of the start of packet information, a counter arranged in a byte clock generator is arrested and is reset given the presence of the complete start of packet information so that an internal, current byte clock pulse is lengthened and, therefore, the packet byte clock is synchronized with the byte clock inherent in the terminal equipment.

Patent
29 Sep 1987
TL;DR: In this article, a GaAs register for storing digital data is configured with a plurality of "D" type flip-flops having a data terminal and an enable terminal connected to an enabled GaAs clock circuit.
Abstract: A GaAs register for storing of digital data is configured with a plurality of "D" type flip-flops having a data terminal and an enable terminal connected to an enabled GaAs clock circuit. The enabled GaAs clock circuit provides a load clock signal to enable the "D" type flip-flops during the loading of data into the plurality of "D" type flip-flops and to prohibit the loading of data without the load clock signal. The enabled GaAs clock circuit has "D" type flip-flop, a clock input circuit and a combining circuit. The clock input circuit receives a clock signal and delays the clock signal. The "D" type flip-flop loads the load enable signal with the rising edge of the clock signal and the delayed clock signal and the loaded enable signal are combined to obtained a combination signal which is used to load data into the plurality of "D" type flip-flops in the register.