Showing papers on "Clock gating published in 1989"

High-speed CMOS circuit technique

Abstract: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

High speed clock distribution system

Abstract: This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

Integrated logic circuit with clock skew adjusters

Abstract: In an integrated logic curcuit, a plurality of clock skew adjustors generate clocks having coincident phases in reaponse to frequency information and phase information fed from a clock source. These clock source and clock adjustors are arranged so that their individual signal delays may be substantially equalized.

Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits

Abstract: A reduced instruction set computer processor, having a rapid access, dual port register file for supplying operands to a high speed arithmetic logic unit, is implemented as a set of integrated circuits interconnected by constant impedance transmission lines and synchronized by a common clock signal. The transmission lines interconnecting the integrated circuits are formed by thin metallic foil conductors separated by dielectric polyimide membranes. The clock signal is adjustably delayed prior to transmission to each integrated circuit so that pulses of the clock signal arrive at each integrated circuit at the same time regardless of differences in inherent delays of the separate paths the clock signal must follow to each integrated circuit.

VLSI performance compensation for off-chip drivers and clock generation

Abstract: A major problem in VLSI system design is controlling off-chip driver characteristics and skew in clock generation as process parameters, temperature, and supply voltage vary. A control circuit methodology has been developed that senses the relative performance of a CMOS chip and transmits a digitally encoded state to off-chip driver and clock generation circuits to control their operating characteristics

Apparatus for low skew system clock distribution and generation of 2x frequency clocks

Abstract: A phase-locked loop clock regeneration circuit which removes board-to-board system skew and further provides a second order loop to adjust the cycle-to-cycle symmetry of a 2X frequency clock.

Optical clock system with optical time delay means

Abstract: An optical clock system for high-performance computing systems uses unique methods of clock generation, delay timing, and electrical clock conversion to eliminate clock skew due to passive circuit elements. There is provided a direct optical connection to active devices in the computing system thereby eliminating the transmission of electrical clock signals through passive transmission elements. The optical clock system eliminates several stages of clock drivers and, as a result, is capable of reducing clock skew due to active circuit skew as well. In one embodiment, an optical pulse timing operator (10) produces ultrashort pulses which are equally divided by an 1-by-N splitter (16) into N optical fibers (18), where N depends on the number of clock signals required. Each fiber has a different length, resulting in different propagation times for the optical pulses. The light from each of the N fibers are again split into M fibers by N 1-by-M splitters (20), where M depends upon the number of distribution points for the clock. The N×M fibers are regrouped to form a bundle of N fibers, and these M fiber bundles are then coupled to each module (22) where the delayed optical signals are converted into the appropriate electrical clock signals.

On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches

Abstract: An algorithm has been developed for the automatic determination of the optimal clock waveforms for synchronous circuits containing level-sensitive latches. From a specification of only the number of clock phases, the rise and fall times of the clock phase transitions, and the order in which they occur, the algorithm computes the minimum time interval between the transitions, while accounting for the clock skew. Timing errors, such as incorrect hold times, are also detected. Existing procedures, in contrast, either verify if a circuit meets a given specification of these clock intervals, or they work with a very restricted set of clocking schemes. The procedure is iterative, and can be formulated as a linear programming problem. It yields an upper bound on the shortest valid clock period at each iteration. Results are presented for a simplified form of this algorithm, implemented in the transistor-level timing analysis program TAMIA. >

Glitch free clock select

Abstract: Clock select circuitry is provided which allows CPU operation at the crystal frequency or one-half the crystal frequency. Frequency selection is accomplished under CPU control and circuitry is added to insure that the a glitch free clock change can be performed on the fly. The glitch free clock select insures that no half T state is less than what a full speed half T state would be. By gating the appropriate phases of the half speed clock and the full speed clock to control the clocking of a flip flop, the point at which the clock selection multiplexer is switched can be controlled. In speeding up the clock, the speed change occurs on the falling edge of the full speed clock provided that the half speed clock is low. When slowing down the clock, the speed change occurs on the rising edge of the half speed clock.

Clock signal switching circuit

Abstract: A clock signal switching circuit having input terminals to receive a first clock signal of a first frequency, a second clock signal of a second frequency, and a frequency switching signal and an output terminal to output one of the first clock signal and second clock signal, wherein the output of the clock signal switching circuit is selected to be one of the first and second clock signals by the frequency switching signal. The clock signal switching circuit includes a first switching circuit which receives the first clock signal and the frequency switching signal and which outputs the first clock signal when not received the frequency switching signal and which interrupts the first clock signal when received the frequency switching signal, with the output of the first switching circuit being switched in synchronization with the first clock signal, and a second switching circuit which receives the second clock signal and the freqnency switching signal and which outputs the second clock signal when received the frequency switching signal and which interrupts the second clock signal when not received the frequency switching signal, wherein the second switching circuit outputs the second clock signal after the first switching circuit has interrupted the first clock signal and interrupts the output of the second clock signal before the first switching circuit outputs the first clock signal, with the output of the second switching circuit being switched in synchronization with the second clock signal.

Service clock recovery circuit

Abstract: A clock recovery circuit serves to recover a clock signal from data which does not arrive at predetermined times and which may be bursty. The clock recovery circuit operates in conjunction with a buffer which receives the data. Illustratively, the clock recovery circuit maintains a first count of the bytes of data written into the buffer and a second count of the byte of data transferred from the buffer. A subtractor substracts the second count from the first and a decision circuit utilizes the result to provide a signal indicative of the current occupancy of the buffer. Depending on the current occupancy, the frequency of an output signal of the clock recovery circuit is increased, decreased, or maintained as constant. This output signal thus serves as the recovered clock signal.

High performance clock distribution for CMOS ASICs

Abstract: An effective clock distribution system is presented for high performance CMOS standard cell designs. The system can achieve clock skew of less than 500 ps with phase delay under 4 ns. The system is flexible, multitiered, netlist-specific, compatible with commercial routers, and accurately modeled. Clock tree structure, interconnect constraints, buffer design methodology, netlist-driven placement, localized clock assignment, simulated annealing, layout reintegration, and simulation modeling are discussed

Apparatus for synchronizing clock signals

Abstract: Apparatus for synchronizing a clock signal to a pulse comprises a clock signal generator (1) for generating a first clock signal having a frequency equal to that of a desired clock signal. A delay circuit (2) to which the first clock signal is fed generates a number of time delayed versions of the first clock signal, each time delay being less than the period of the first clock signals. Logic (9) compares the time delayed versions of the first clock signal and the original clock signal at the time of occurrence of the pulse and selects as the desired clock signal, a version of the first clock signal which has changed state close to the time of occurence of the pulse.

Computer system clock generator for generating tuned multiple clock signals

Abstract: A computer system clock generator generates several system clock signals which are in a tuned state at desired locations, thereby offsetting the effects of varying propagation delays among the system clock signals. A shift register ring has one of its taps selectively connected to its data input so that a series of logic high level and logic low level data is advanced through the shifting stages. A tap selector for each desired output signal logically combines the signals output from the appropriate taps to produce output clock signals having desired leading and trailing edges.

A clock distribution scheme for nonsymmetric VLSI circuits

Abstract: The authors propose a clock distribution scheme that minimizes the difference in the length of clock lines, which is the foremost factor responsible for clock skew in a VLSI circuit. The scheme uses the hierarchy created by the clock buffers to parallelize the distribution of the clock signal. At each hierarchical level, an exhaustive search of paths with intelligent pruning is used to determine the optimal layout of clock lines at that level. Unlike other related work in this area, both delay and skew are taken into account in determining the layout. >

Apparatus and method for assuring stable clock generator during oscillator start-up

Abstract: A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold. The pulse generator module (20) functions as a modified edge-triggered D flip-flop (21, 23) that triggers in response to paired transitions of CLOCK A and CLOCK B (indicating that the oscillator clock has cycled through both the high and low amplitude thresholds), generating a transition pulse. The pulse counter module (30) includes a pulse counter capacitor (C1) and a pulse detection transistor (31) that is turned on during each transition pulse to provide a charging path for the pulse counter capacitor, thereby incrementally charging the pulse counter capacitor in response to transition pulses. When the pulse counter capacitor (C1) is charged to a level corresponding to the receipt of a selected number of transition pulses, a Schmitt trigger circuit (34) is activated to provide a CLOCK STABLE signal, indicating that the oscillator clock has provided a selected number of stable clock cycles. The control logic module (40) provides ENABLE, /CHARGE and DISCHARGE signals that control operation of the clock stability circuit in a microcomputer during Halt, Start and Run modes.

Clock selection circuit

Abstract: A clock selection circuit having a single input terminal for receiving an external clock signal and including logic means for selectively passing an external clock signal and an internal clock signal to an output. A clock detector is connected to the input terminal for generating a voltage in response to an external clock signal. The generated voltage is utilized in controlling the logic circuitry in selectively passing the external clock signal or the internal clock signal. In a preferred embodiment, the logic circuitry includes a first two input NAND gate, a second two input NAND gate, and a third two input NAND gate. One input of the first NAND gate receives the external clock signal, and one input to the second NAND gate receive sthe internal clock. The two outputs of the first and second NAND gates are connected to the inputs of the third NAND gate. The output from the clock detector is connected to the other input of the first NAND gate and is connected through an inverter to the other input of the second NAND gate.

Autonomous N-modular redundant fault tolerant clock system

Abstract: A fault tolerant clock system in which synchronization of the clocks continuing to operate after a fault occurs is maintained within a skew limit. The clock system includes a plurality of clock channels (10), each including a clock unit (12) and an isolation port (14). A local clock signal produced by a crystal oscillator (16) is enabled to provide a clock channel output signal while a counter (24) in the clock unit accumulates a predetermined number of local clock pulses. After the predetermined number is reached, the counter disables the clock channel output signal and produces a sync pulse, which is input to a voter block (48). In response to the second sync pulse to be received from each of the clock channels, each voter block produces a load pulse signal that is input to the isolation port of that clock channel. Corresponding isolated load signals are produced by the isolation port and provided to voter blocks (72) in each of the clock units. The voter blocks respond to the second isolated load signal to be received, producing a load enable signal that is input to the counter. Upon receipt of the load enable signal, the counter resumes counting and again enables the clock channel output signal, in synchronization with the other clock channel output signals. Up to N simultaneous faults may be sustained in the clock system, without loss of synchronization in the clock channels that continue to operate properly, so long as 2N+1 clock channels are provided.

Repeater for regenerating frame-multiplexed signal

Abstract: A repeater which receives a frame-multiplexed signal, extracts a receiving clock from the signal, and detects a timing of frame synchronization. The receiving clock and a master clock are input into a selector, the output of the selector is supplied for frame regeneration through a clock phase gradual shift circuit, and the detected timing is supplied for frame synchronization in the regenerated frame-multiplexed signal through a gate. Normally, the receiving clock and the detected timing is supplied for the frame regeneration, however, when the detection of the timing of frame synchronization fails, the output of the selector is switched to the master clock and the gate becomes off, and when the detection of the timing of frame synchronization is recovered and the detected timing of frame synchronization and a timing of frame synchronization is regeneration, which is generated from the master clock, coincide, the output of the selector is switched back to the receiving clock and the gate simultaneously becomes on. Further, in the clock phase gradual shift circuit, normally, an output clock synchronizes with an input clock, and a phase shift resulting from an abrupt phase shift occurring in the input clock gradually appears in an output clock after the abrupt phase shift in the input clock.

Digital data transfer synchronization circuit and method

Abstract: A data transfer synchronization method and circuit allows data to be transferred between two synchronous systems running asynchronously with each other in a way that does not require the receiving system clock to be running twice as fast as the source system clock. Data is clocked into a first set of flip-flops by the clock signal of the source system. The source system clock signal is also used to toggle a toggle flip-flop. The receiving system clock signal is used to clock a first clock bit flip-flop coupled to detect the state of the toggle flip-flop. A delayed version of the receiving system clock signal is used to clock the output of the first set of flip-flops into a second set of flip-flops. The normal (undelayed) receiving system clock signal is used to clock the output of the second set of flip-flops into a third set of flip-flops. A data valid signal is generated when the third set of flip-flops have on their outputs the data received during receiving system clock cycles in which the toggle flip-flop toggled. If the toggle flip-flop did not toggle during a particular receiving system clock cycle, no data valid signal is produced because this data is either redundant or uncertain due to insufficient guaranteed setup time.

Clock distribution scheme for non-symmetric VLSI circuits

Abstract: The authors propose a clock distribution scheme that minimizes the difference in the length of clock lines, which is the foremost factor responsible for clock skew in a VLSI circuit. The scheme uses the hierarchy created by the clock buffers to parallelize the distribution of the clock signal. At each hierarchical level, an exhaustive search of paths with intelligent pruning is used to determine the optimal layout of clock lines at that level. Unlike other related work in this area, both delay and skew are taken into account in determining the layout.<>

CMOS clock generator having an adjustable overlap voltage

Abstract: A CMOS clock generator for generating internal CMOS phase clock signals having an adjustable overlap voltage includes a first circuit (18) having a first input responsive to an input clock signal for generating a first phase clock signal (01) on its output and a second circuit (22) having a first input responsive to the input clock signal for generating a second clock signal (02) on its output. The overlap voltage between the phase clock signals are adjustable either up or down to speed up or slow down a semiconductor chip after fabrication. This is achieved by the utilization of a laser to break or open up fuses connected to electrodes of transistor devices.

Counter employing exclusive NOR gate and latches in combination

Abstract: The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.

A monolithic 50-200 MHz CMOS clock recovery and retiming circuit

Abstract: A single-chip realization of a clock recovery and data retiming circuit is described. The circuit has been manufactured in a 0.9-mm digital CMOS technology and will recover a clock from NRZ (nonreturn-to-zero) random data. Features of the chip include built-in self-test, crystal of reference clock inputs, and differential or single-ended ECL (emitter-coupled logic) 100k I/O. A single inexpensive external crystal is required to stabilize operation over the frequency range. With the aid of a single external reference resistor, true ECL 100k compatibility is maintained without the cost and complexity of an added bipolar transistor process

Multi-year time clock having automatic daylight saving time compensator

Abstract: A clock circuit for driving a clock movement such as a bipolar clock contains a memory which is programmed to automatically adjust the clock movement for standard and daylight saving time adjustments. The circuit is normally powered from the AC power line but includes a battery backup and is designed to run the clock circuit uninterruptedly for its entire life without needing used initiated adjusting or actuating.

Standard cells with flip-flops located in a single region and having minimal-length clock lines

Abstract: Standard cells in which the accurate estimation of the clock routing length and the minimization of the clock routing are possible so that an optimal protection against the malfunctions due to the racing can be schemed. The standard cells includes flip-flop circuits collectively arranged in a region of the substrate; and clock routing for the flip-flop circuits with connections connecting the clock routing and each of the flip-flop circuits at shortest distance.

Method and apparatus for operating at fractional speeds in synchronous systems

Abstract: A synchronous digital system is disclosed which includes a system clock, a first and a second subsystem, each having a clock input, and a circuit for disabling the clock input to the second subsystem on a regular basis. The effective clock rate of the second subsystem is a fraction of the effective clock rate of the first subsystem.

Race-Free Clocking of CMOS Pipelines through a Single Global Clock

Abstract: To ease global clock distribution in a synchronous system extending over several levels of interconnect (for example between logic blocks within a chip, chips mounted on a printed circuit board and boards of chips across a backplane), a race-free clocking scheme for CMOS VLSI requiring a single clock line is presented. Since the technique is race-free, the clock line may be driven by a sinusoid, thereby avoiding the transmission of the higher frequency components associated with fast clock edges. In this way, clock signal distortion due to transmission line effects will be kept to a minimum.

Low power timekeeping

Abstract: Low-power timekeeping methods have been developed that provide improved accuracy over the full military temperature range. These methods provide tradeoffs of accuracy vs. power consumption dependent upon the application. The system achieves this performance by using a microcomputer-compensated crystal oscillator (MCXO) to periodically update a low-power oscillator clock system. This technique does not substantially increase the power dissipation because the MCSO is turned on for only a few seconds each time to recalibrate the clock oscillator frequency. Using this technique, a clock oscillator of +or-5*10/sup -6/ over the temperature range can be made to approach the +or-*10/sup -8/ accuracy of the MCXO. >

Clock signal supplying device

Abstract: A clock signal supplying device is provided with an automatic phase regulating function for preventing errors in the phase regulation due to noises. In the device is provided a refer­ence signal serving as a phase reference. Transmission lines (30) for clock signals and a transmission line (31) for the reference signal are disposed from a clock signal supplying source (10) to devices (20), which are destinations of dis­tribution of clock signals. The transmission line for the reference signal is adjusted in advance so as to produce no skew. In the device (20), which is the destination of distri­bution of the clock signal, there is disposed a variable delay circuit (51) for regulation of the phase of the clock signal and a phase comparing circuit (52) for comparing the output of the variable delay circuit (51) with the phase of the refer­ence signal to output the result of the comparison. The amount of delay by the variable delay circuit (51) is controlled, responding to the output of the phase comparing circuit (52). Further, a noise filter is provided, which detects phase re­gulation errors to effect correct phase regulation. The phase regulation is effected while avoiding a period of time, where noises are apt to be produced.