Showing papers on "Clock gating published in 1990"

Clock skew optimization

Abstract: Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS. >

Power saving arrangement for a clocked digital circuit

Abstract: A power saving arrangement for a microcomputer having a first clock signal operating at a predetermined frequency employs a reduced clock frequency to peripheral circuitry to limit power consumption during a disable or halt mode A control circuit disables a clock signal provided to the microcomputer, while a clock divider divides the predetermined frequency to generate a reduced frequency signal upon which the peripheral circuitry may operate After receiving an external wake-up signal, the peripheral circuitry interrupts the microcomputer in order to revert the microcomputer back to normal operation

Method and apparatus for transparently switching clock sources

Abstract: A method and apparatus for stably maintaining an output clock signal from a phase-locked loop (PLL) frequency multiplier when switching from one clock source to another clock source is described. This method and apparatus maintains the phase relationship between the external signal to the phase detector and the feedback signal from the divider to the phase detector.

Clock generator for a computer system

Abstract: A clock frequency multiplication circuit. A circuit is described for receiving a clock signal of a first frequency X and multiplying the frequency of the signal by a multiple N to produce a signal of frequency N times X. The circuit is particularly useful in, for example, computer systems in which it is desired to upgrade certain components such as a processor to operate at an increased clock speed without modifying the clock speed of the system clock and where it is further desired to provide synchronization between the system clock and the processor clock.

Implantable cardiac device with dual clock control of microprocessor

Abstract: A microprocessor (10) based implantable cardiac treatment device having first and second clocks (12,20). The first clock (12) is a continuously running external clock of a relatively low frequency for controlling low power, uncomplicated operations of the device. The second clock (20) runs at a much higher frequency for controlling the complex, high power operations of the microprocessor (10). Clock control circuitry (22) is provided for activating the second clock (20) only when it is determined that high power calculations are to be made by the microprocessor (10).

Dual dot clock signal generator

Abstract: A dual dot clock signal generator consisting of two similar programmable phase locked loops simultaneously generates a video clock signal and a memory clock signal. Both the video clock signal and the memory clock signal may have one of several different frequencies. The generator includes circuitry which detects when one of the selected frequencies is identical to or a submultiple of the other. The comparison circuitry which detects this condition acts to change the frequency of one of the clock signals, and supplies the other clock signal in its place. Both the video clock signal generator and the memory clock signal generator are programmable via their respective internal memories, and the internal memory of the video clock signal generator carries additional information which identifies those video frequencies which are identical to or a submultiple of the frequencies available from the memory phase locked loop. By substituting the memory clock signal or a divided version of the memory clock signal for the conflicting video clock signal and changing the frequency of the VCO within the video phase locked loop, the problem of cross-interference between the two clock signals is eliminated.

Fault-tolerant clock for multicomputer complex

Abstract: A quad oscillator fault-tolerant clock system for a computer complex comprises two clock sources at each of two computer locations, which are coupled by two duplex links. Each clock source supplies its own clock signal to the other clock source at the same location as well as to the clock sources at the other location over one of the duplex links coupling the two locations. Each clock source continually measures the phase difference between its clock signal and each of the other three clock signals. Periodically, the propagation delay for each link is calculated by taking the average of the phase differences measured by the clock sources driving the two ends of that link. These calculated propagation delays are supplied to each individual clock source, which corrects the phase differences measured by it for the propagation delays. Each clock source uses the median of the corrected phase differences to obtain a correction signal to control its own oscillator frequency so as to obtain phase lock with the other clock signals.

System and circuits using Josephson junctions

Abstract: An electronic clock has a single Josephson junction connected in parallel to a resonant circuit, which is a delay line with a matching resistance at the input end to provide series termination. The opposite end of the delay line is an open end to reflect pulses, and the pulse transit time on the line determines the clock rate. A zero crossing detector is provided to initiate the clock operation when an input signal rises above a given threshold, and a reset circuit is included to turn off the clock when the input signal falls below this threshold. A flip-flop circuit allows the clock to be turned on by alternate initiating signal pulses. A modification includes a pulse rejuvenating circuit at the end of the delay line to offset pulse degradation. All of the circuits are fabricated with Josephson junction elements, and the zero crossing detector, reset circuit, flip-flop circuit and pulse rejuvenator circuits include dc-SQUID's. The clock is capable of operation at frequencies up to 100 GHz and can sample input single frequencies as high as 15 GHz.

High resolution sample clock generator with deglitcher

Abstract: A digital controlled clock provides ultra fine resolution for a sampling clock signal for recovering data from a received signal, the phase jump of the sampling clock signal being determined the number of stages in a multiphase clock generator that generates a number of equally-spaced phase clock outputs based on a reference clock signal. Phase selection is performed through a very low overhead phase commutator in response to phase advance/retard inputs. A clock deglitcher matched to the stages of the ring oscillator eliminates spikes generated when the phase commutator switches.

Testing of integrated circuits using clock bursts

Abstract: A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

Floating point processor with internal free-running clock

Abstract: In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder (CSA) cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier and divider are pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include two-speed internal clocking for operation and testing, two-node clock stopping and distributed buffering of system clock signals.

Method for synchronizing the phase of clock signals of two clock generators in communications networks

Abstract: Method for synchronizing the phase of clock signals of two clock generators in communications networks. Using the present method, the phase relations of clock signals that are derived from oscillator clock signals in two clock generators are synchronized such that the phase relations of the clock signals coincide regardless of the distance between the two clock generators. To this end, one clock generator is defined as a reference clock generator and reference clock signals formed therein are communicated to the other further clock generator. In the latter, the generated further clock signals are synchronized with the incoming reference clock signals and the clock signals synchronized in this fashion are forwarded to the reference clock generator. In the latter, the phase deviation of the internally formed clock signals and of the incoming clock signals is measured and correction information is formed and forwarded to the other further clock generator. The phase relation of the clock signals is corrected in the other further clock generator in conformity with the correction information.

Circuit arrangement for clock regeneration in clock-controlled information processing systems

Abstract: Line terminal groups are redundantly present for reliability reasons. The connecting through of the input lines to the switching matrix network can thereby proceed via different signal paths. In order to avoid disturbances during switch-over between signal paths, the appertaining interfaces are provided with compensation memories. The data contained in the compensation memories are written in or read out in a phase-synchronized and frame-synchronized manner with a uniform clock. The uniform clock is acquired from the electronic switching device base clock of the system. Due to transient time distortions and component tolerances, the base clock must be regenerated with the circuit arrangement of the invention before it is applied to the compensation memories.

Shift register apparatus with improved clock supply

Abstract: A shift register apparatus comprising unit registers, clocks and gates. Only when data input to the apparatus is significant enough to shift the state of the unit registers, is the clock signal supplied selectively to the unit register of the applicable stage. The selective supplying of the clock signal reduces the power fed to clock lines. With a larger number of shift stages, a greater amount of power will be saved, especially in applications where the apparatus is used to generate multiphase pulses. Fewer drivers are needed to drive the clock signal, which may be supplied at the TTL level.

Clock recovery for serial data communications system

Abstract: In a serial data communications system, an embedded clock is recovered from a data signal by incrementally controlling the frequency (thus phase) of a voltage-­controlled oscillator (42) in response to the difference in phase between the incoming data signal (13) and the clock oscillator output (43). A transition of the data signal is detected and used to initiate a control pulse which is terminated upon the next transition in the clock oscillator output (43). A reference pulse is also generated which has a width about equal to a half cycle of the clock. These pulses are used to generate the voltage control for the oscillator, so that the phase relationship varies to seek an equilibrium where the pulses are of equal width and the transitions of the clock are at midpoint of potential transitions of the data signal. The control can tolerate relatively long periods where there is no transition of the data signal. The control circuitry includes a counter for counting transitions of the clock to inhibit another detect operation from starting until three transitions after one has begun.

One-shot circuit for use in a PLL clock recovery circuit

Abstract: A one-shot whose period is a fraction or multiple of the VCO period in a clock recovery circuit. In a clock recovery circuit using PLL, the one-shot is coupled to the PLL in order to enable/disable the phase detector for cases when the data stream does not consist of uniformly spaced pulses. Without a one-shot, the phase detector in the PLL generates a large error signal whenever a clock pulse occurs without a data pulse. During the times when the phase detector is enabled, a phase comparison is made between the next data edge and the next clock edge. When this comparison is completed, the phase detector is disabled again. In order for the PLL to average out the effects of noise and jitter, the phase detector is enabled one half clock period before the data edge. By doing this, the data edge can shift up to one half clock period. The one-shot of the present invention generates a delayed data signal whose rising edge is used to enable the phase detector, and whose falling edge is compared with the clock edge for disabling the phase detector.

Elastic buffer circuit

Abstract: An elastic buffer circuit for adjusting the timing between a satellite communication system of a time division multi-access (TDMA) type and a ground communication system is provided with a stable oscillator for generating a first clock signal whose frequency is N (N is an integer not smaller than 2) times the received clock frequency, a clock generating circuit for generating a second clock signal by frequency-dividing the first clock signal by N and, at the same time, setting the phase of the second clock signal on the basis of a sync code detection signal, and a data memory circuit for temporarily storing data signals in accordance with the second clock signal.

Apparatus and method for performing arithmetic functions in a computer system

Abstract: A computer having a processing unit with improved performance characteristics. The computer includes a floating point multiplier, a floating point arithmetic logic unit (ALU), a first clock generator for generating a first clock and a second clock generator for generating a second clock. The second clock is generated to have a fixed relationship with the first clock. Specifically, the first clock is delayed and inverted to produce the second clock. The multiplier includes an output port operating under control of the second clock and coupled to provide data to a first input port of the adder. The adder includes both the first input port and a second input port, both operating under control of the second clock. A first and second input port of the multiplier and an output port of the adder operate under control of the first clock. The described configuration allows operation with reduced latency.

Synchronous clock source selector

Abstract: A clock source selector provides at least one set of clock signals selected from a plurality of clock sources and a synchronized transition from an old clock source to a new clock source. The clock source selector includes a gate having an output for providing the clock signals, a selector coupled between the plurality of clock sources and the gate for providing the gate with clock signals from selected ones of the clock sources responsive to selection signals, a detector for detecting a change in the selection signals from an old clock source to a new clock source, and a synchronizing circuit responsive to the detector for disabling the gate in synchronism with the old clock source and thereafter enabling the gate in synchronism with the new clock source.

Adjustable clock chopper/expander circuit

Abstract: A clock chopper/expander circuit (10) includes a reset dominant latch circuit (20) which is set by a CLOCK IN signal (12) and reset by a delayed CLOCK IN signal labelled DELAY (26), provided by an asymmetrical delay circuit (22) which delays the CLOCK IN signal TD seconds. The delay circuit (22) utilizes an adjustable bias current source (64) to bias a half memory cell (50), which charges up a node (62) according to the write time of the cell (50). A sensing circuit triggers a DELAY transition when node (62) crosses a voltage predetermined by the bias provided to a second half memory cell (52) which is also controlled by the bias current source (64). A multiplexer (24) provides disablement of the clock chopping/expanding function and an OR gate (14) facilitates easy measurement of the actual delay introduced by circuit (22).

Clock system implementing divided power supply wiring

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Signal generator for generating a delayed clock signal

Abstract: A signal generator having a Johnson counter including a plurality of flip-flops having CLOCK inputs to which a clock signal is inputted; a logic gate to which the clock signal and Q outputs of the flip-flops are inputted, the logic gate being constructed such that the clock signal is passed therethrough each time 2n clock pulses of the clock signal occur and that the logic gate outputs its output as a first signal, n representing the number of the flip-flops of the Johnson counter; and delay means for delaying the clock signal by a time corresponding to an input-output delayed time of the logic gate and for outputting the delayed clock signal as a second signal.

Clock skew reduction approach for standard cell

Abstract: Five clock treatments are evaluated by SPICE simulation. The wide trunk-line with balanced output short sub-buffering scheme is the best way to reduce the clock skew and delay. In order to realize this scheme, a special clock treatment has been developed. This includes insertion of sub-buffers, regeneration of channel relation trees and special global routing. Maximum clock delay and skew are simulated to be 3.6 ns and 1.4 ns respectively under the condition of 2000 fanouts and 15-mm-square die size on 1.0 mu m design rule. This approach will be available on both TC24SC (1.0 mu m) and TC25SC (0.8 mu m) standard cell. >

Clock signal multiplier

Abstract: A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.

Optical clock system for computers

Abstract: An optical clock system for high-performance computing systems uses unique methods of clock generation, delay timing, and electrical clock conversion to eliminate clock skew due to passive circuit elements. There is provided a direct optical connection to active devices in the computing system thereby eliminating the transmission of electrical clock signals through passive transmission elements. The optical clock system eliminates several stages of clock drivers and, as a result, is capable of reducing clock skew due to active circuit skew as well. In one embodiment, an optical pulse timing generator (10) produces ultrashort pulses which are equally divided by an 1-by-N splitter (16) into N optical fibers (18), where N depends on the number of clock signals required. Each fiber has a different length, resulting in different propagation times for the optical pulses. The light from each of the N fibers are again split into M fibers by N 1-by-M splitters (20), where M depends upon the number of distribution points for the clock. The NxM fibers are regrouped to form a bundle of N fibers, and these M fiber bundles are then coupled to each module (22) where the delayed optical signals are converted into the appropriate electrical clock signals.

Timing signal delay circuit with high resolution or accuracy

Abstract: A timing signal delay circuit comprises a counter placed with first delay setting data (21-24) for counting a first clock signal (12) in response to an input timing pulse (11), and a first flip-flop circuit which has a D-input supplied with the output of the counter (1) and a clock input supplied with a second clock signal of the same timing frequency as the first clock signal. For doubling resolution of the delay which the input timing pulse undergoes, there are provided an exclusive-OR gate (4) supplied with a second dealy data signal (31) and a third clock signal (14) of the same timing as the second clock signal (13), an AND gate (5) supplied with the output of the exclusive-OR gate (4) and that of the first flip-flop (3), and a second flip-flop supplied with the output of the AND gate (5) and a fourth clock signal (15) having twice as high frequency as that of the first clock (12). The input timing pulse can be delayed with high resolution or accuracy.

Circuit arrangement for switching a digital service channel through a radio relay repeater

Abstract: A circuit arrangement for switching an externally accessible service channel, formed by additional bits within a digital data signal, contains an output circuit, which shifts the service-channel bits in time as soon as there is a threat of phase coincidence of a receive clock derived from the data signal with the transmit clock generated with an identical or slightly different frequency. Errors produced by an unclear assignment of the service-channel bit to the transmit clock are prevented in this way. The output circuit contains a buffer, a phase detector, and a changeover switch driven by the phase detector. To produce the time shift, the buffer clock is fed to the buffer via an inverter (I) interposed by the changeover switch. A second solution provides for a direct switching of the service signal and the interposition of the buffer clock with the inverted receive clock only during periods in which there is a threat of phase coincidence between the receive clock and the transmit clock.

Power supply reliability of portable electronic device

Abstract: A portable electronic device comprising a clock generator for generating a clock signal, a power supply for generating a first power supply voltage, a low-voltage generator for generating a second power supply voltage lower than the first power supply voltage in response to the clock signal, an instruction circuit for instructing start of the clock generator, and a supply circuit for, when a start instruction of the clock generator is generated by the instruction circuit, supplying the first power supply voltage to the clock generator, and after the clock generator is started by the first power supply voltage, supplying the second power supply voltage to the clock generator.

Charge coupled device having a circuit for handling a fundamental clock signal

Abstract: A charge coupled device has a circuit for handling a fundamental clock signal to produce a particular driving signal in the device, and independent power supply lines and/or ground lines. One power supply line and/or one ground line is exclusive for the circuit for handling the fundamental clock signal. The interference by the fundamental clock signal is prevented by the separation of power supply line and/or ground line.