Showing papers on "Clock gating published in 1991"

Exact zero skew

Abstract: An exact zero skew clock routing algorithm using the Elmore delay model is presented. Recursively in a bottom-up fashion, two zero-skewed subtrees are merged into a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multi-staged clock trees, and multi-chip system clock trees. It is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, and then interconnected with exact zero skew. Experimental results are presented. >

Computer with transparent power-saving manipulation of CPU clock

Abstract: A computer system having power management control features which include states of normal clock speed operation, slow clock speed operation, and stop-clock operation based on input/output activity, system bus activity, and program parameters. The system detects inactivity over a period of time and places the system in one of the states to provide for power conservation and accessibility by a user.

Digital clock buffer circuit providing controllable delay

Abstract: A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

Synchronous dynamic random access memory

Abstract: A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first control signal; a Y-address is latched following activation of a second control signal. Data selected by the latched X- and Y-addresses are held in a data latch and output through a tri-state output circuit in synchronization with the clock signal. Data output starts a certain number of clock cycles from activation of the first control signal. The data can be output for one clock cycle, the same data can be output for two or more consecutive clock cycles, or different data can be output in consecutive clock cycles in an order determined by certain bits in the X- and Y-addresses.

Double-edge-triggered D-flip-flops for high-speed CMOS circuits

Abstract: Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2- mu m technology. >

Low power consuming digital circuit device

Abstract: A method is provided for decreasing the power consumption of a sequential digital circuit having a plurality of states being determined from the current state and the input conditions and entered upon the assertion of a pulse from one or more clocks. The method consists of interrupting the switching created by the clock pulses and maintaining the system in a quiescent state. It is first determined whether a subsequent clock pulse will lead to a change in the state of the circuit. If it will, the circuit either waits for a change in the input conditions and state of the circuit, or changes some of the input conditions, depending on the embodiment of the invention. When a circuit configuration is reached in which further clock pulses will not lead to a change in the state of the circuit, the clock signal(s) are replaced by continuously asserted signals. The feedback loop thus created maintains the current state of the circuit in the absence of a clock signal and prevents further switching in the circuit.

Clock signal latency elimination network

Abstract: A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.

Apparatus for providing a system clock locked to an external clock over a wide range of frequencies

Abstract: A digital phase lock loop circuit for synchronizing the phase of clock signals delivered to devices through clock tree circuitry with the phase of input clock signals including a first delay line, a second delay line, a phase detector circuit, apparatus for transferring the input clock signals through the first delay line to the phase detector circuit, apparatus for transferring the input clock signals through the second delay line and the clock tree circuitry to the phase detector circuit, apparatus responsive to the difference in phase detected between the clock signals transferred through the first and second delay lines for varying the delay of one of the delay lines to bring the clock signals transferred through the first and second delay lines into phase with one another.

Variable chip-clocking mechanism

Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.

A clock buffer with adjustable delay and fixed duty cycle output

Abstract: A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching level of the differential input buffer is adjustable, either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e. g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input cloak signal, so that harmonic noise is reduced in the system.

Method and apparatus for controlling clock skew

Abstract: A circuit for controlling clock skew has a plurality of delay elements placed in each of the clock output paths in a clock distribution circuit. The delay elements may be selectively switched into or out of each clock output path in order to adjust the delays of each clock output path so that the skew between clock outputs is minimized. The delay in each clock output path is determined by measuring the frequency of a ring oscillator created by connecting a feedback loop across the delay elements. The frequency of oscillation is measured as delay elements are switched into or out of each clock output path until the frequency reaches close to a target frequency.

Clock switching apparatus and method for computer systems

Abstract: A clock switching apparatus is provided in a data processing system which includes a system clock for selectively switching the system clock from a first clock signal to a second clock signal and vice versa. The clock switching apparatus includes a multiplexer coupled to receive the first clock signal and the second clock signal for selectively switching the system clock from the first clock signal to the second clock signal. The multiplexer provides the system clock. A control logic circuit is coupled to receive the second clock signal and a control signal for controlling the multiplexer to switch the system clock from the first clock signal to the second clock signal, wherein the control signal is synchronized to the second clock signal in the control logic circuit to become a synchronized control signal. The multiplexer switches the system clock from the first clock signal to the second clock signal when receiving the synchronized control signal from the control logic circuit. A pass logic circuit is provided for outputting the system clock. The pass logic circuit receives the system clock from the multiplexer. The pass logic circuit is controlled by the control logic circuit to output the system clock such that a glitch-free and minimum transitional period within which the system clock is switched from the first clock signal to the second clock signal is ensured. A method of selectively switching the system clock from the first clock signal to the second clock signal in the data processing system is also described.

Method for self regulating CMOS digital microcircuit burn-in without ovens

Abstract: A burn-in heating circuit for an integrated circuit including a burn-in clock generator for producing a burn-in clock signal that is provided to the clock buffer of the clock distribution system of the integrated circuit. The operating frequency of the burn-in clock is at or close to the maximum frequency that the clock distribution system can reliably sustain with valid logic levels, so that the highest possible self-heating can be achieved by power dissipation in the clock distribution system. A comparator that is responsive to a temperature signal representative of the integrated circuit junction temperature and a signal indicative of the desired burn-in temperature modulates the clock generator so that the junction temperature of the integrated circuit resulting from self heating is close to the desired burn-in temperature.

PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor

Abstract: Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 mu m BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz. >

Stable high speed clock generator

Abstract: A clock generator which is provided with a circuit generating non-overlap clock from input clock, a frequency dividing circuit driven by the non-overlap clock and a latch disposed between the frequency dividing circuit and a clock driver, and whose critical pass being a cause of delay is shortened by sampling the frequency-divided output into the latch by the input clock and thereafter driving it by the clock driver, and a clock generator in which an internal clock at high speed in the internal clock logical value generating circuit is added with internal clock edge generating circuit required to operate at high speed and an output of initial stage of a buffer for inputting external clock is divided to supply to the internal clock edge generating circuit and to the other circuits, thereby capacity of the buffer required to operate at high speed in the circuit is decreased to reduce the delay of external clock.

Method of and circuit for synchronizing data

Abstract: Asynchronous DS-1 data is byte synchronized and converted to the SONET VT1.5 format by storing the DS-1 data in a store (20) from which it is read in dependence upon a gapped clock signal (40) which is produced by gapping a first gapped clock signal (48) with a ratio of 208/193, which is the ratio of VT SPE bits per frame to DS-1 bits per frame. The first gapped clock signal is produced by gapping a VT1.5 synchronous clock signal (46). A frequency difference between the first gapped clock signal and the asynchronous data rate, multiplied in a frequency multiplier (26) by the ratio of 208/193, is monitored by comparing the counts of modulo-208 counters (84, 86), and, in dependence upon the monitored frequency difference, the gapping of the synchronous clock signal is controlled to achieve positive or negative stuffing and hence to compensate for the frequency difference.

Placement for clock period minimization with multiple wave propagation

Abstract: A linear program is used to direct the placement of Standard Cells such that the clock period is minimized. Constraints upon the logic path delays and the clock signal arrival times at the flipflops allow multiple signals, corresponding to several clock cycles, to exist simultaneously on the logic signal paths during operation. The linear program constraints relate the clock period to the maximum and minimum logic path delays. Delays are achieved in the clock and logic paths by the use of delay elements and resistive polysilicon wires in the interconnection network.

Random number generator driven by independent clock pulses asynchronously with system clock pulses

Abstract: A random number generator built into an integrated circuit has at least one oscillator that generates clock pulses independent of the integrated circuit's system clock, at least two counters for counting those clock pulses, and read-out means for outputting the contents of the counters in response to a read signal. The random number generator accordingly has an extremely simple circuit configuration, but is capable of generating random numbers at a rapid rate.

Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems

Abstract: A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.

Design for testability and test generation with two clocks

Abstract: Proposes a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines. The scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan based methods. However, a sequential ATPG system is necessary for test generation. The basic idea is to use independent clock lines to control disjoint groups of flip-flops. No cyclic path is permitted among the flip-flops of the same group. During testing, a selected group can be made to hold its state by disabling its clock lines. In the normal mode, all clock lines carry the same system clock signal. With the appropriate partitioning of flip-flops, the length of the vector sequence produced by the test generator for a fault is drastically reduced. An n-stage binary counter is used for experimental verification of reduction in test length by the proposed technique. >

Built-in self-test global clock drive architecture

Abstract: A BIST clock driver for providing memory elements in a combinational and sequential logic circuit with a global clock signal during user mode and a test clock signal during testing. The clock driver also supplies clock signals to memory circuits that have clock inputs supplied by random logic. The clock driver supplies the random logic with a global clock signal. A clock multiplexor receives the generated clock and the test clock signal and provides the memory element with the generated clock signal during user mode and the test clock during testing of the memory element.

Glitch reduction in integrated circuits, systems and methods

Abstract: An integrated circuit has a clock input pad and circuitry operative in response to a clock signal. Clock transitions at the clock input pad are potentially subject to glitches due to noise and ringing. Further provided is a glitch remover circuit having a logic gate having first and second inputs. The glitch remover circuit has a series of circuits coupled to the clock input pad with differing delays for positive edges than for negative edges. The series of circuits has an output connected to the first input of the logic gate, with the second input coupled to the series of circuits intermediately. Other devices, systems and methods are also disclosed.

Digital processor clock circuit

Abstract: A clock circuit (12) normally couples clock pulses to a microprocessor (11), which is capable of accessing memory devices (13,14) having different access times. Access of a "slow" memory device 14 is detected by the clock circuit, and in response thereto, one or more clock pulses are not coupled to the microprocessor. This suspends operation of the microprocessor for a suitable amount of time so that the microprocessor reads valid data from the slow memory device. The number of clock pulses blocked from reaching the microprocessor can be set in a delay circuit in the clock circuit.

Radio pager with high speed clock of controlled rise time

Abstract: A radio pager having means for automatically adjusting the rising time of a high-speed clock. The pager includes a plurality of circuit elements for adjusting the rising time of the high-speed clock, i.e., for compensating the degree of stability of a high-speed clock generating circuit. On the start of a low-speed clock, the high-speed clock generating circuit sequentially selects and connects the circuit elements to thereby count the resulting rising times of the high-speed clock. One of the circuit elements having resulted the shortest rising time is written to a storage. When the high-speed clock is needed, e.g., when a message should be displayed, the stored circuit element is connected to the high-speed clock generating circuit.

Two-fail-operational fault-tolerant multiple clock system

Abstract: A multiple-fail-operational fault-tolerant clock having a plurality of interconnected and identical clock modules, that provides a fault tolerant clock signal despite some clock module failures. The clock incorporates fault-tolerant operational diagnostics so that a working clock module may be voted for supplying the output clock signal.

Clock tree synthesis for high performance ASICs

Abstract: Using clock tree synthesis to create a high performance clocking network during layout requires the implementation of an active buffer distribution that is a design and technology specific trade-off between skew sensitivity, clock insertion delay, and simultaneously switching power dissipation. >

Integrated circuit with reduced clock skew

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Boundary-scan input cell for a clock pin

Abstract: A boundary-scan circuit for a system clock input pin of an integrated circuit which prevents the transmission of undesirable pulses into the clock inputs of the core logic circuits during switching to or from the test clock. This is accomplished by synchronizing the signal that controls the switching from or to the system clock to provide such switching during the inactive portion of the system clock cycle. The boundary-scan circuit uses plural switching elements to provide sufficient current drive to prevent degradation of a rise time of any clock pulse transmitted thereby without the use of additional current buffers.

Clock recovery enhancement circuit

Abstract: An improved clock recovery enchancement circuit is provided that is particularly adapted for solving the problem caused by an incoming signal that is asymmetric and comprises a sub-harmonic tone of the bit rate clock, that is 180° out of phase with the recovering clock, thereby causing the data edges to appear to be locked. The clock recovery enhancement circuit, according to the invention, provides a window signal near a predefined edge of the recovering clock which creates a disable signal such that clock adjustments may be biased towards one direction.

Fault isolation for multiphase clock signals supplied to dual modules which are checked by comparison using residue code generators

Abstract: A clock error detection system is provided for a data processing system that employs multiphase clock signals and dual, substantially identical electronic modules. The clock error detection system employs one clock error detection circuit on one module and a second clock error detection circuit on the other electronic module. An error collector is coupled to the first and second clock error detection circuits on both modules to receive the fault signals. Two complementary residue code generators with different moduli are used in each electronic module to generate clock phase error detection signals, which may be used to detect either missing or extra clock phases.