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Showing papers on "Clock gating published in 1995"


Patent
Mitsuyoshi Yamamoto1, Ikuya Kawasaki1, Hideo Inayoshi1, Susumu Narita1, Masaharu Kubo1 
14 Dec 1995
TL;DR: In this paper, it is shown that if the instruction is to increase the frequency of the clock signal and the operating voltage in its absolute value, the clock signals having the increased frequency is outputted prior to the increase of the operating voltages in the absolute value.
Abstract: A microcomputer has a clock generator capable of changing the frequency of an output clock signal: and a power circuit capable of changing the level of an operating voltage to be outputted. The frequencies of clock signals and the levels of operating voltages to be individually fed to a plurality of circuit modules can be dynamically changed according to the content of a packaged register. If the content of the register instructs the reduction of the clock signal frequency and the operating voltage in its absolute value, the operating voltage is lowered in its absolute value prior to the change in the clock signal frequency. On the contrary, if the instruction is to increase the frequency of the clock signal and the operating voltage in its absolute value, the clock signal having the increased frequency is outputted prior to the increase of the operating voltage in the absolute value. As a result, it is possible to prevent in advance the malfunctions of the circuit at the time of switching the operation frequency and the operating voltage of the circuit module.

204 citations


Patent
16 Oct 1995
TL;DR: In this paper, a clock signal distribution system using a delay lock loop with specific digital circuits is presented. But the system is not suitable for the use of a single clock signal.
Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

160 citations


Proceedings ArticleDOI
18 Jun 1995
TL;DR: In this paper, high-frequency resonant DC/AC inverters are proposed as power clock generators where all power switches and control circuitry are integrated on the same chip with low-energy logic.
Abstract: Low-energy (adiabatic) logic families have been proposed to reduce energy consumption of VLSI logic devices. Instead of the conventional DC power supply, these logic families require AC power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. In this paper, high-frequency resonant DC/AC inverters are proposed as power clock generators where all power switches and control circuitry are integrated on the same chip with low-energy logic. This results in better system efficiency and simpler power distribution. Closed-form results are derived to facilitate efficiency-optimized design of the proposed power clock generators. To illustrate system integration and energy savings, the optimized power clock is used to supply a novel clocked CMOS adiabatic logic (CAL). >

125 citations


Proceedings ArticleDOI
01 Dec 1995
TL;DR: This paper proposes an approximation algorithm based on recursive matching to solve the clock tree construction problem and solves the gate insertion problems with an exact algorithm employing the dynamic programming paradigm.
Abstract: In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree can be turned on/off by gating the clock signals during the active/idle times of the clocked elements. We propose a method of obtaining the switching activity patterns of the clocked circuits during the high level design process. We formulate three novel activity-driven problems. The objective of these problems is to minimize system's dynamic power consumption. We propose an approximation algorithm based on recursive matching to solve the clock tree construction problem. We solve the gate insertion problems with an exact algorithm employing the dynamic programming paradigm. Finally, we present experimental results that verify the effectiveness of our approach. Our work in this paper is a step in understanding how high level decisions (e.g. behavioral design) can affect a low level design (e.g. clock design).

117 citations


Book
01 Jan 1995
TL;DR: This book shows one of recommendation of the book that you need to read, which is a kind of precious book written by an experienced author about clock distribution networks in vlsi circuits and systems.

103 citations


Patent
22 Dec 1995
TL;DR: In this paper, a clock signal generator can prevent unnecessary power consumption and can lower the power consumption of a system or a chip as a whole, and a clock selector selects a clock signals which have a required frequency according to a status signal STS from each of the functional locks.
Abstract: A clock signal generator can prevent unnecessary power consumption and can lower the power consumption of a system or a chip as a whole. A clock generator has a plurality of multipliers having variable multiplying factors and multiplying a single input reference clock signal by a designated multiplying factor. A plurality of frequency dividers have variable divide factors and divide a clock signal by a designated dividing factor. A clock selector selects a clock signal which has a required frequency according to a status signal STS from each of the functional locks from among the clock signals having a plurality of frequencies generated by the clock generator. The clock selectors stops the operation of the multipliers or the frequency dividers which are generating unused frequencies by switching clock signals.

71 citations


Patent
David Harris1, Sunny C. Huang1, James Nadir1, Ching-Hua Chu1, J. Stinson1, Alper Ilkbahar1 
03 Mar 1995
TL;DR: In this paper, an opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals.
Abstract: An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal. Odd-numbered half-cycles begin with a domino gate of the second type controlled by the second clock signal, followed by domino gates of the first type controlled by the fourth clock signal.

70 citations


Patent
18 Dec 1995
TL;DR: In this paper, a clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU -- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signals.
Abstract: A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU -- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU -- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

69 citations


Patent
Mamoru Kitamura1
02 Oct 1995
TL;DR: In this paper, the internal clock timing control circuit of a synchronized semiconductor memory device comprises a memory cell array, address input circuit, an address set circuit, a command input circuit and a data reading/writing control circuit.
Abstract: A synchronized semiconductor memory device comprises a memory cell array, an address input circuit, an address set circuit, a command input circuit, a data reading/writing control circuit, a data output circuit, a data input circuit, a clock input circuit, an internal clock generating circuit, and an internal clock timing control circuit The internal clock timing control circuit includes a delay circuit to receive a reference internal clock generated in the internal clock generating circuit, a plurality of level signals set in accordance with a given mode register set cycle, and a plurality of row address enable signals, and for generating at least an internal clock signal for timing-controlling the data reading/writing circuit The internal clock timing control circuit also includes a logic circuit to receive the reference internal clock generated in the internal clock generating circuit and the plurality of row address enable signals, and for generating another internal clock signal for timing-controlling the data input circuit

69 citations


Patent
Shekhar Borkar1, Stephen R. Mooney1
26 Jun 1995
TL;DR: In this paper, a daisy chained clock distribution scheme for distributing a clock signal from a central communications clock driver to the nodes of a massively parallel multi-processor computer or supercomputer is presented.
Abstract: A daisy chained clock distribution scheme for distributing a clock signal from a central communications clock driver to the nodes of a massively parallel multi-processor computer or supercomputer. The daisy chained clocking scheme is implemented using point-to-point clock distribution of a differential clock signal to the communication nodes of a plurality of processors in a multicomputer system or to components connected to a common bus in a high speed microprocessor system. Differential signaling is employed wherein the differentiality is maintained including through silicon. In an alternate embodiment, the clock pulse is also regenerated in each node component.

64 citations


Patent
26 Jul 1995
TL;DR: In this article, a dynamic clock mode switch (11) is provided for switching clock frequencies while allowing continuing operation of a depending system, which includes an enable circuit for transmitting an enable signal, a phase-locked loop circuit (PLL) (15) for locking onto an input clock frequency in response to said enable circuit, a PLL lock indicator for receiving a pLL lock signal (29) from said PLL, and a clock multiplexer with a multiplier for multiplying the input clock frequencies by a predetermined factor in order to respond to enable circuit and PLL clock signals
Abstract: A dynamic clock mode switch (11) is provided for switching clock frequencies while allowing continuing operation of a depending system. The switch includes an enable circuit for transmitting an enable signal, a phase-locked loop circuit (PLL) (15) for locking onto an input clock frequency in response to said enable circuit, a PLL lock indicator for receiving a PLL lock signal (29) from said PLL, and a clock multiplexer with a multiplier for multiplying said input clock frequency by a predetermined factor in response to said enable circuit and PLL clock signals.

Patent
08 Sep 1995
TL;DR: In this paper, a H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across a VLSI chip.
Abstract: A clock distribution network for distributing a clock signal across a VLSI chip. A H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across the chip. The H-tree distributes a plurality of repower buffer levels above a final repower buffering level. The output of the final level are coupled by the x-y grid to minimizes clock skew caused by the chip and by local loading variations in the circuits.

Patent
26 Dec 1995
TL;DR: In this article, a hierarchical clocking arrangement for CPLD is described, where a synchronous clock multiplexer is provided within each logic block for reducing an input set of N synchronous and M asynchronous clock signals to a reduced set of M synchronous signals.
Abstract: A complex programmable logic device (CPLD) is disclosed which includes a set of logic blocks each containing a product term array and a set of macrocells. A clocking arrangement is provided which allows selection between synchronous and asynchronous clock signals for input to each macrocell. The clocking arrangement is hierarchical. More specifically, a synchronous clock multiplexer is provided, within each logic block, for reducing an input set of N synchronous clock signals, and their complements, to a reduced set of M synchronous clock signals. The selected synchronous clock signals, and J product term asynchronous clock signals, or their complements, provided by the corresponding product term array, are routed into each of the macrocells of the logic block. An additional multiplexer is provided within each macrocell for selecting one clock signal from among the M synchronous clock signals and the J product term signals. The hierarchical clocking arrangement provides considerable flexibility for selecting clocking signals, both on a block by block basis, and on a macrocell by macrocell basis yet requires relatively modest chip resources for implementation. A specific example is described herein where in N is six, M is three and J is one.

Patent
15 Dec 1995
TL;DR: In this paper, an improved SRTS clock recovery system of a network node comprising a novel adaptifier arrangement that continually monitors the flow of data through a data FIFO and briefly assumes control over the SRTS recovery system to permanently adjust the phase and/or temporarily adjust the frequency of a transmit clock to avoid dataflow errors.
Abstract: An improved SRTS clock recovery system of a network node comprising a novel adaptifier arrangement that continually monitors the flow of data through a data FIFO and briefly assumes control over the SRTS clock recovery system to permanently adjust the phase and/or temporarily adjust the frequency of a transmit clock to avoid dataflow errors. Specifically, the adaptifier includes a phase controller that permanently adjusts a target phase offset utilized by the SRTS clock recovery system to effect a permanent change in the transmit clock phase. A frequency controller of the adaptifier temporarily overrides an error signal generated by the SRTS clock recovery system prior to it being utilized by a clock generator to effect a temporary adjustment of the transmit clock frequency. Clock perturbations are minimized, including graceful entry and exit of adaptifier action. The adaptifier implements either or both adjustments to avoid an impending dataflow error based upon a number of predetermined conditions. Once such an error is no longer anticipated, control is returned to the SRTS clock recovery system. Advantageously, data FIFO overflow and underflow conditions are prevented, thereby enabling the clock recovery system to provide error-free transmission through the implementing network node. The novel SRTS clock recovery system may make either temporary phase and/or permanent frequency adjustments to the transmit clock to recover from reference clock deviations without loss of data, without causing substantial perturbations in the transmit line frequency, while maintaining interoperability with existing SRTS equipment.

Patent
30 May 1995
TL;DR: In this article, the maximum fill level of undelayed cells Lxj is extracted from successive series of a predetermined whole number M of buffer-fill samples Li and a frequency adjustment logic unit provides at its output a bit stream at a given clock frequency fj.
Abstract: A clock recovery unit provides a clock recovery function in the receiving entity of a system to implement adaptation of constant bit-rate (CBR) services over an asynchronous transfer mode (ATM) or ATM-like network. Incoming cells are periodically sampled for buffer fill level Li. The maximum fill level of undelayed cells Lxj is extracted from successive series of a predetermined whole number M of buffer-fill samples Li. A frequency adjustment logic unit provides at its output a bit stream at a given clock frequency fj. The frequency adjustment logic unit makes incremental adjustments to the clock frequency fj tending to cause the steady state mean of the fill level Lxj, or its derivative, to move toward zero.

Proceedings ArticleDOI
01 Jan 1995
TL;DR: It is shown that the power minimization problem is NP-hard and a greedy heuristic for power-optimal clock network design is proposed that utilizes the opportunities provided by buffer insertion.
Abstract: We propose a new problem formulation for low power clock network design that takes rise time constraints imposed by the design into account. We evaluate the utility of inserting buffers into the clock route for satisfying rise time constraints and for minimizing the area of the clock net. In particular, we show that the classical H-tree is sub-optimal in terms of both area and power dissipation when buffers may be inserted into the tree. We show that the power minimization problem is NP-hard and propose a greedy heuristic for power-optimal clock network design that utilizes the opportunities provided by buffer insertion. Our algorithm inserts buffers and designs the topology simultaneously. The results we obtain on benchmarks are significantly better than previous approaches in terms of power dissipation, wire length, rise times and buffer area. Power dissipation is typically reduced by a factor of two, rise times are four times better and buffer area requirements are an order of magnitude smaller.

Patent
Jeffrey L. Rabe1, Zohar Bogin1, Ajay V. Bhatt1, James P. Kardach1, Nilesh V. Shah1 
06 Jan 1995
TL;DR: In this paper, the power consumption controller generates an interrupt signal in response to a low power event or a fully operational event, and the processor transmits the internal clock signal to at least one functional block within the processor.
Abstract: A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.

Patent
24 Apr 1995
TL;DR: In this article, a programmable phase shift clock generator is described, including a phase comparator, an up-down counter, a ring oscillator and an adjustable delay line for determining a digital signature of an input clock and precisely generating a phase shifted clock signal.
Abstract: A programmable phase shift clock generator is disclosed including a phase comparator, an up-down counter, a ring oscillator, and an adjustable delay line for determining a digital signature of an input clock and precisely generating a phase shifted clock signal.

Proceedings Article
01 Sep 1995
TL;DR: Energy savings comparable to adiabatic logic families that require multi-phase power clocks have been verified by simulation tests of the CAL supplied by the integrated power clock generator.
Abstract: This paper describes a low-power clocked CMOS adiabatic logic (CAL) with only one ac power supply that serves as the power clock. Each CAL stage performs true and complementary logic functions, and presents a constant capacitive load to the power clock generator. A simple and efficient resonant power clock is integrated with the logic to generate the required ac supply waveform and facilitate adiabatic energy transfers. Energy savings comparable to adiabatic logic families that require multi-phase power clocks have been verified by simulation tests of the CAL supplied by the integrated power clock generator.

Patent
David R. Evoy1
11 Oct 1995
TL;DR: A thermal management method for controlling the temperature of a computer processor chip includes sensing a temperature with a temperature dependent circuitry integrally formed in a packaged clock chip, in which the sensed temperature is a function of the temperature as mentioned in this paper.
Abstract: A thermal management device for controlling the temperature of a computer processor chip, by controlling the operating speed of the processor, including a temperature sensitive circuitry incorporated within a packaged clock chip for connection to a processor. A thermal management method for controlling the temperature of a computer processor chip includes sensing a temperature with a temperature dependent circuitry integrally formed in a packaged clock chip, in which the sensed temperature is a function of the temperature of the computer processor chip, generating a clock control signal with the temperature dependent circuitry and sending the clock control signal to a clock generator also integrally formed in the clock chip, and sending a clock signal from the clock generator to the computer processor chip in order to control the operating frequency, and thus the temperature, of the processor.

Patent
29 Jun 1995
TL;DR: In this paper, an interface circuit for interfacing an electronic device, such as a microprocessor (102), operating at a device clock speed and a finite synchronous state machine (104), comprised of a D-type flip-flop (106) and a SVM (108), which are operating at state clock speed, is provided.
Abstract: An interface circuit (100) for interfacing an electronic device, such as a microprocessor (102), operating at a device clock speed and a finite synchronous state machine (104) comprised of a D-type flip-flop (106) and a synchronous state machine (108), which are operating at a state clock speed, is provided. The device clock speed being capable of being greater than the state clock speed. The interface circuit° (100) comprises an input circuit, which may comprise a first NAND gate (120), connected to a latch circuit which may comprise interconnected second and third NAND gates (124) and (126). The input circuit and latch circuit store an input signal (121) received from the electronic device and transmit the input signal (121) to the flip-flop (106) when the synchronous state machine (108) is ready to accept further input signals. A system for operating the finite synchronous state machine (104) associated with a state clock speed and a method for interfacing an electronic device operating at a device clock speed and a synchronous state machine (108) operating at a state clock speed are also provided.

Patent
02 Jun 1995
TL;DR: In this paper, a block clock/control circuit with multiple clock signals (CK1-CKN) for programmable logic devices was proposed. But the multiple clock signal was not provided to the multiplexer to enable the storage element to function in a latch mode.
Abstract: Output logic macrocells (504) for a programmable logic device as well as a block clock/control circuit (502) which allocates multiple clock signals (CK1-CKN) to each macrocell. Each macrocell includes a multiplexer (506) selectively providing one of the multiple clock signals to a clock input of a storage element (508), which operates similar to a latch. The storage element further receives a sum of product terms output from an OR gate at its data input. Vcc may be provided through the multiplexer to enable the storage element to function in a combinatorial mode. The multiple clock signals may include a clock signal provided to the multiplexer to enable the storage element to function in a latch mode. The clock signal may also be provided through a pulse generator in the block clock/control circuit to provide pulses having a pulse width δ to enable the storage element to function in a D-type flip-flop mode. For the D flip-flop mode, the storage element may be configured to operate as a P-type flip-flop so that its output will change states to follow its data input at a leading edge of its clock input, then does not change states for a period e, wherein e > δ, and then its output will change states to match its data input after the period e if a signal received at the clock input has a period greater than e. To provide reset or preset, a reset or preset signal may be provided at the data input of the storage element, as well as through a second pulse generator in the block clock/control circuit to the clock input of the storage element. The block clock/control circuit may be further configured to provide a dual edge clock mode, a mixed clock mode wherein two signals are provived on a single clock line, or other clocking modes.

Journal ArticleDOI
15 Feb 1995
TL;DR: A digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs is described.
Abstract: This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs. For a computer system consisting of nine PC boards ("modules") plugged into a back plane with two clock chips per board and six ASICs per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns.

Patent
Gottfried Goldrian1
10 Aug 1995
TL;DR: In this paper, a first circuit with a first clock signal (CLOCK1) at a first-round rate and a second-round signal at a secondround rate, coupled to an input circuit coupled to the first circuit and receiving signals therefrom, is described.
Abstract: According to the invention an apparatus is provided comprising a first circuit with a first clock signal (CLOCK1) at a first clock rate and a second circuit with a second clock signal (CLOCK2) at a second clock rate, the second circuit comprising an input circuit coupled to the first circuit and receiving signals therefrom. The apparatus further comprises a control circuit for controlling possible metastability situations in a communication between the first circuit and the second circuit. The control circuit receives as input the first clock signal and the second clock signal and comprises means for providing a shifting of at least one of the both clock signals, or parts thereof, in such a way that a possible metastable state of the input circuit is avoidable. A possible metastability situation in an apparatus according to the invention is controlled by monitoring the first clock signal and the second clock signal. When a possible metastability situation has been detected, at least one of the both clock signals, or parts thereof, is shifted, preferably advanced or delayed, in such a way that a possible metastable state of the input circuit can be avoided.

Patent
29 Mar 1995
TL;DR: In this article, the first and second parallel processors operate in one of several modes including synchronous and stand-alone modes, and each processor includes a clock for selectively providing a first high frequency clock signal to both processors.
Abstract: First and second parallel processors operate in one of plural modes including synchronous and stand-alone modes. Each processor includes a clock for selectively providing a first high frequency clock signal to both processors. Each processor also includes electronic circuitry operating at a second frequency lower than the first frequency which generates a clock selection signal that selects one of the clocks from the first and second processors to clock both processors. The electronic circuitry, in response to mode change signals, generates clock switching control signals at the lower frequency. The lower frequency clock control signals are reclocked so that they are synchronous with the first frequency clock signals before being used to select one of the clocks.

Patent
Robert Paul Masleid1
08 Sep 1995
TL;DR: In this paper, a split clock buffer provides separate control of a pull-up transistor and a pulldown transistor between clock edge transitions, which is used to improve clock edge transition speed and phase accuracy.
Abstract: A system and method for increasing clock edge transition speed and edge phase accuracy. A split clock buffer provides separate controls of a pull-up transistor and a pull-down transistor. The buffer is off (high impedance) between clock edge transitions. Clock edge transition speed is improved by avoiding the transient condition of a conventional clock buffer where both of the pull-up and pull-down transistors are both on during clock edge transition.

Patent
George W. Conner1
01 May 1995
TL;DR: In this paper, a system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period was proposed, where each local generator including local programmable means to count clock signals and provide local outputs upon receiving predetermined clock signals.
Abstract: A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to count clock signals and provide local outputs upon receiving predetermined clock signals and local programmable delay means for providing a timing signal after a delay interval following each local output, the resolution of the local delay means being greater than that of the clock

Patent
Lawrence D. Cepuran1
18 Sep 1995
TL;DR: In this paper, the clock signal generator generates a clock signal alternately of at least two frequencies, namely a low frequency and a high frequency, when information is not transmitted upon the bus, and the circuit is operated at the low frequency level.
Abstract: At least two circuit elements are interconnected by a bus which permits transmission of information between the circuit elements. A clock signal generator generates a clock signal alternately of at least two frequencies, namely, a low frequency and a high frequency. When information is not transmitted upon the bus, the clock signal generator generates the clock signal of the low frequency, and the circuit is operated at the low frequency level. When information is generated upon the bus, the clock signal generator generates a clock signal of the high frequency and the circuit is operated at the high frequency. Detection of a start bit, for example, forming a first bit of a word transmitted upon the bus, once detected, causes the clock signal generator to generate the clock signal of the increased frequency. Because the power consumption of an electrical circuit is proportional to the frequency at which the circuit is operated, the circuit is operated at minimal power levels except during times in which information is transmitted.

Patent
25 Sep 1995
TL;DR: In this paper, a controller chip has dynamic logic which is driven by a suspendable clock, and power is reduced in a standby mode when the clock to the dynamic logic is stopped.
Abstract: A controller chip has dynamic logic which is driven by a suspendable clock. Power is reduced in a standby mode when the clock to the dynamic logic is stopped. However, power is still applied to the dynamic logic in standby mode so that the dynamic logic can be quickly resumed without the delay of re-charging the power-supply capacitances in the dynamic logic. Stopping the clock to dynamic logic can eventually cause loss of data. A more severe problem than data loss is power consumption. When the clock is stopped to dynamic logic, the isolated nodes leak and eventually their voltages change. When their voltages change by more than a transistor threshold voltage then both the p-channel and n-channel transistors in dynamic logic cells can turn on, forming a direct current paths between power and ground. Thus power consumption can increase dramatically in suspend mode. The isolated dynamic nodes of the dynamic logic are instead recharged periodically during suspend mode. A timer triggers generation of intermittent clock pulses which are applied to the clock to the dynamic logic, recharging the isolated nodes. When data loss can be tolerated, the intermittent pulses ensure that power consumption does not jump due to the voltage changes on the isolated dynamic nodes.

Patent
12 Apr 1995
TL;DR: In this article, a clock generator with complementary FET switches coupled between the output of the generator and power supply rails, and an inductor is presented. But the generator is operated at a frequency approximately equal to the resonant frequency of the inductor combined with the capacitance of the load.
Abstract: High-efficiency clock generator (10) circuits are disclosed having single or complementary outputs (Q) for driving capacitive loads (11). The clock generator has therein at least one pair of complementary FET switches (14,15) coupled between the output of the generator and power supply rails, and an inductor (13). The generator is operated at a frequency approximately equal the resonant frequency of the inductor combined with the capacitance of the load. Energy normally stored in the load and dissipated in the FETs as in conventional clock generators is instead stored in the inductor and returned to the loads for reuse.