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Showing papers on "Clock gating published in 1998"


Patent
04 Feb 1998
TL;DR: In this paper, a delay-locked loop (320, 350) was proposed for generating a predetermined phase relationship between a pair of clocks (300, 310), where a phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560) based on the phase comparison.
Abstract: Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

323 citations


Journal ArticleDOI
TL;DR: A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip- flop which embodies the leakage current cutoff mechanism.
Abstract: A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half.

278 citations


Journal ArticleDOI
05 Feb 1998
TL;DR: In this paper, the clock is generated from an 80-200 MHz reference clock multiplied by an on-chip phase-locked loop (PLL) to a nominal frequency of 600 MHz and the clock distribution network up to and including the global clock is included in the feedback loop of the PLL to control phase alignment.
Abstract: The clocking methodology for the 600 MHz Alpha microprocessor allows increased performance goals to be met through multi-level buffering. In addition power savings are realized through reduced metal usage and conditional clocks. Two distinct analysis methods are required to verify the clock design. One is used for large, globally distributed clocks and the other is applied to small, locally distributed clocks. The clock is generated from an 80-200 MHz reference clock multiplied by an on-chip phase-locked loop (PLL) to a nominal frequency of 600 MHz. The clock distribution network up to and including the global clock (GCLK) is included in the feedback loop of the PLL to control phase alignment. GCLK is the primary timing reference for the chip. The generation of GCLK begins at the PLL and is routed through a high-gain buffer network to a central point on the die. From there the clock is driven through buffered X, H and RC trees to distributed GCLK drivers located in a windowpane pattern across the chip. The final physical stage of the global clock distribution network is a grid of upper-level low-impedance metal that covers the entire die.

186 citations


Patent
09 Oct 1998
TL;DR: In this article, a memory device with multiple clock domains is presented, where the different domains are sequentially turned on as needed to limit the power consumed, overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core.
Abstract: A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

166 citations


Patent
26 Jun 1998
TL;DR: In this paper, an optical source is configured to emit optical pulses at a desired clock frequency and the optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die.
Abstract: A method and an apparatus for providing an optical clock distribution network. In one embodiment, an optical source is configured to emit optical pulses at a desired clock frequency. The optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die. In one embodiment, each clock receiver node locally generates a photocurrent in response to the split optical beams. Each of the photocurrents is locally converted into voltage and thus into local clock signals, which are used to clock the local area of the integrated circuit. In one embodiment, the semiconductor die includes an additional clock receiver node used to clock a clock generation circuit included in the semiconductor die. The clock generation circuit generates clock signals that are in phase with each other and the other clock signals generated throughout the semiconductor die. In one embodiment, the clock signals generated by the clock generation circuit are used to clock and phase lock input/output communications on the semiconductor die as well as off chip input/output communications between the semiconductor die and other external semiconductor dice of the system.

154 citations


Journal ArticleDOI
01 Nov 1998
TL;DR: This MPEG4 video codec implements essential functions in the MPEG4 committee draft by using a 16b RISC processor that provides software programmability and three-step hierarchical motion estimation reduces power dissipation.
Abstract: A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-/spl mu/m CMOS with double-well and triple-metal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.

122 citations


Patent
15 Jun 1998
TL;DR: In this paper, a clock signal at a first location in the processor is compared with a reference clock signal and the first clock signal is corrected based on the results of this comparison with the reference signal.
Abstract: A method and apparatus to compensate for skew in a processor clock signal. A first clock signal at a first location in the processor is compared with a reference clock signal. The first clock signal is corrected based on the results of this comparison with the reference clock signal. The clock signal may be corrected by using a programmable delay compensator. A second clock signal at a second location in the processor may be compared with the corrected first clock signal and the second clock signal may be corrected based on the results of the comparison. The compensators may be permanently programmed as required using fuses associated with compensator control bits.

111 citations


Patent
04 Dec 1998
TL;DR: In this article, an oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature, and it includes an oscillation generator, two independent current generators, a transition detector and a clock inhibitor.
Abstract: An oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature, and it includes an oscillation generator, two independent current generators, a transition detector and a clock inhibitor. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current that is independent of temperature. The oscillator is capable of three modes of operation: fast mode, slow/low power mode and sleep mode, which are controlled by the transition detector in response to external control signals. When the transition detector transitions from one mode to another, it controls the clock inhibitor to block a clock output of the oscillator generator for a predetermined number of clock cycles to allow the clock output to stabilize. The oscillator is implemented on a single, monolithic integrated circuit.

98 citations


Patent
Kohlschmidt Peter1
03 Mar 1998
TL;DR: In this article, a mobile communications terminal includes a high accuracy clock for providing a timebase in a normal operating mode, a "slow clock" for providing the time base in a low power mode of operation, and at least one processor coupled to the high-accuracy clock and the slow clock for controlling the modes of operation.
Abstract: According to the present invention, a mobile communications terminal includes a high accuracy clock for providing a timebase in a normal operating mode, a "slow clock" for providing the timebase in a low power mode of operation, and at least one processor coupled to the high accuracy clock and the "slow clock" for controlling the modes of operation. In a preferred embodiment, the mobile communications terminal includes a conversion signal processor (CSP), a digital signal processor (DSP), a communications protocol processor, and a radio frequency (RF) segment. The CSP, which includes a plurality of registers, interfaces with the DSP to execute the timing control functions for the terminal. In the normal operating mode, the timebase is maintained from the high accuracy clock. During inactive periods of terminal operation (e.g., in a paging mode), a sleep mode is enabled wherein the high accuracy clock source is disabled, the DSP, CSP, and communications protocol processor are shut down, and the "slow clock" provides the timebase for the terminal while a sleep counter is decremented for a given sleep interval. Upon expiration of the sleep interval or in response to an intervening external event (e.g., a keypad is depressed), a terminal wake-up is initiated so that the high accuracy clock resumes control of the timebase. Because the high accuracy clock and the "slow clock" are not synchronized, the CSP and DSP calibrate the "slow clock" to the high accuracy clock prior to the terminal entering the sleep mode.

97 citations


Patent
Valluri R. Rao1
13 Apr 1998
TL;DR: In this paper, a method and an apparatus for optically clocking an integrated circuit in a semiconductor is presented, where the laser pulses are separated into a plurality of split laser pulses, each of which are focused through the back side of a C4 packaged integrated circuit die into P-N junctions distributed throughout the integrated circuit.
Abstract: A method and an apparatus for optically clocking an integrated circuit in a semiconductor. In one embodiment, a laser is configured to emit infrared laser pulses at a desired clock frequency. The laser pulses are separated into a plurality of split laser pulses, each of which are focused through the back side of a C4 packaged integrated circuit die into P-N junctions distributed throughout the integrated circuit die. Each P-N junction locally generates a photocurrent in response to the split laser beams. Each of the photocurrents are locally converted into voltages and thus into local clock signals, which are used to clock the local area of the integrated circuit. With the presently described optical clocking technique, the local clock signals have extremely low clock skew. The presently described technique may be employed in integrated circuits system-wide, in multi-chip modules, or in an individual integrated circuit. By removing the global clock distribution network from the silicon, the present invention allows chip area used in the prior art for a global clock distribution networks to be used instead for signal routing or allows overall die sizes to be reduced.

86 citations


Patent
21 Jul 1998
TL;DR: In this article, a clock tree circuit using a transistor having a threshold voltage variable well structure for a clock element is proposed to reduce power consumption and reduce clock skew of clock tree circuits.
Abstract: PROBLEM TO BE SOLVED: To provide a clock tree circuit capable of controlling clock skew of a clock tree circuit, reduced in power consumption and low in clock skew SOLUTION: This clock tree circuit uses a transistor having a threshold voltage variable well structure for a clock element Here, it has phase comparator circuits 31 to 33 which perform comparison observation of skew values among respective elements 21 to 24 and output differential voltage and charge pump circuits 41 to 43 which make the differential voltage of the circuits 31 to 33 inputs and supply them as well potential to each well terminal of the elements 21 to 24, controls the switching speed of a clock tree circuit by adjusting the threshold voltage of each element 21 to 24 and reduces clock skew

Patent
09 Jan 1998
TL;DR: In this article, a rotational state machine is used to select a clock for rotation in a non-whole number divider, where M is the integer part and N is the fractional part of the divisor.
Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock. Any phase difference charges a loop filter and changes an adjustment voltage. The adjustment voltage changes the delays in the delay line so that the sum of all delays in the delay line matches the clock period. Since smaller count values can be used when fractional rather than whole-number divisors are used, phase comparisons in a PLL are increased, reducing jitter and smoothing the output.

Patent
Jean-Marc Dortu1, Albert M. Chu1
09 Jun 1998
TL;DR: In this article, a clock latency circuit, method and system is provided which allows the synchronization of data according to the rising and falling edges of a system clock. But the clock latency is not considered in this paper.
Abstract: A clock latency circuit, method and system is provided which allows the synchronization of data according to the rising and falling edges of a system clock.

Patent
01 Apr 1998
TL;DR: In this paper, a method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input.
Abstract: A method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input. The data associated with the read cycle propagates asynchronously through the memory to produce data which is then input to the pipeline circuit. The apparatus includes steering circuitry with precise timing for steering the data produced in the read cycle into an asserted one of several branches of a register. Selection circuitry is used to select for output the data which has been stored in the asserted branch upon receipt of a subsequent clock. The subsequent clock is one which occurs a programmable number of clocks after the first clock.

Patent
22 Jul 1998
TL;DR: In this paper, a clock dividing section receives a system clock and generates and outputs clock signals of two or more types, and selectors select any of the clock signals and feed it to a printing control block or reading control block.
Abstract: A clock dividing section receives a system clock and generates and outputs clock signals of two or more types. Selectors select any of the clock signals of two or more types outputted by the clock dividing section and feed it to a printing control block or reading control block. A decision divider monitors operational states of each block and gives control so that a frequency to be supplied to a functional block in an idle state where any operation is not required is lower than that to be supplied to a functional block being in an active state. Power consumption of the whole custom IC can be more reduced compared with a configuration wherein a clock of fixed frequency is constantly supplied to each functional block and a noise can be controlled.

Patent
11 Aug 1998
TL;DR: In this article, the authors propose a power-down control circuit that outputs an internal clock signal such that an output signal of a command decoder can be latched, and a period of time from the latching of the command to the time when the command can be transferred will be reduced.
Abstract: When a clock enable signal asynchronous with a clock signal is set at a high level, a power-down control circuit sets a power-down signal at a high level to release a power-down mode. When the power-down mode is released, a clock control circuit outputs an internal clock signal such that an output signal of a command decoder can be latched. According to such a constitution, a period of time from the latching of the command after releasing the power-down mode to the time when the command can be transferred will be reduced, and a high-speed operation can be attained.

Patent
21 Oct 1998
TL;DR: In this article, an apparatus and method for distributing a clock signal within circuitry disposed on a number of separate system cards includes a first system card that generates a reference clock signal representative of a fixed delay of a system clock signal.
Abstract: An apparatus and method for distributing a clock signal within circuitry disposed on a number of separate system cards includes a first system card that generates a reference clock signal representative of a fixed delay of a system clock signal. A number of variable clock signals are produced using the system clock signal. Each of a number of system cards separate from the first system card receive one of the variable clock signals. A delay associated with the reference clock signal is typically longer than a delay associated with each of the variable clock signals. The phase of each of the variable clock signals is adjusted to a substantially in-phase relationship with respect to the reference clock signal in response to a phase difference between the reference clock signal an output signal received from each of the separate system cards. Producing each of the variable clock signals may involve selecting between a first delay line and a second delay line, and then producing the variable delay signal using the selected first or second delay line. A delay factor of the non-selected first or second delay line may be changed by varying a resistance and a current of one or more delay elements of the non-selected first or second delay lines. The circuitry is selectably operable in a slave or buffer-type clock repowering mode or an adaptive mode. The variable clock signals and the output signals may respectively comprise low voltage differential signals (LVDS) or CMOS level signals.

Patent
Carl A. Schu1
30 Apr 1998
TL;DR: In this paper, a power switch, such as a power gating transistor, is coupled to a digital logic circuit element to selectively control the application of power to the circuit element.
Abstract: An apparatus and method for controlling power in digital logic circuitry is disposed in a body implantable biomedical device disclosed. A power switch, such as a power gating transistor, is coupled to a digital logic circuit element to selectively control the application of power to the circuit element. During each system clock cycle, power is supplied to the circuit element only for a duration of time required to effect switching of logic states. Power is removed from the circuit element during each system clock cycle when no switching of logic states occurs. A clock signal applied to the gate of a power gating transistor selectively controls the supply of power to the digital circuit logic element during each system clock cycle so as to appreciably reduce static power consumption of the circuit element. The power control apparatus and method may be implemented in any digital logic design, and is well suited for use in digital circuitry that employs combinatorial logic of any complexity and any number of registers or latches. The appreciable reduction in static power consumption realized by employing the power control apparatus and method according to the present invention is particularly useful in digital logic circuitry applications designed to operate at relatively low switching frequencies and low power, such as implantable biomedical device applications.

Patent
David L. Thompson1
28 Oct 1998
TL;DR: In this paper, the authors proposed a power consumption reduction in medical and battery powered devices through the use and operation of multiple digital signal processing systems and through the application of different supply voltages to analog and digital circuits, respectively.
Abstract: Power consumption in medical and battery powered devices is reduced through the use and operation of multiple digital signal processing systems and through the application of different supply voltages to analog and digital circuits, respectively. Each processor of the multiple systems performs at least one particular function in a predetermined time period. The multiple digital signal processors of such systems can be operated at lower clock frequencies relative to those that would be required by one of such processors to complete the multiple functions within the predetermined time period. With reduced clock frequency, power consumption is reduced. Further, with reduced clock speed, supply voltages applied to such digital signal processors may also be reduced. A source applies a first fixed supply voltage to the digital circuits of the medical or battery powered device and a voltage generation circuit (e.g., a charge pump circuit) having the first fixed supply voltage applied thereto is used for generating a second fixed supply voltage to be applied to analog circuits of the device. Power consumption may also be reduced through the operation of circuits at clock speeds of lower levels to adequately complete desired functions during predetermined time periods (e.g., blanking interval, upper rate interval, etc.) just-in-time prior to subsequent required functional processes; by providing supply voltages tailored for various circuits of an integrated circuit; by operating two or more circuits of an integrated circuit at different clock frequencies; by changing the supply voltage level “on the fly” as required by specific circuit timing functions required for various circuitry based on clock frequencies used to control operation of such circuitry; and/or by tailoring back gate bias or adjusting back gate bias “on the fly” for circuits based on the supply voltage level applied to the circuits.

Patent
12 Aug 1998
TL;DR: In this article, the authors present a clock driver providing a clock signal from an input clock signal that has instantaneously selectable phase and methods for synchronizing data transfers in a multi-signal bus communication system.
Abstract: A clock driver providing a clock signal, from an input clock signal, that has instantaneously selectable phase and methods for synchronizing data transfers in a multi-signal bus communication system. A clock driver of the present invention generates an output clock signal from an input clock signal having a periodic wave form and provides the flexibility for selecting or changing the magnitude of the phase-offset of the output clock signal, in relationship to the input clock signal, for desired clock periods and optionally desired half-clock periods. A method is provided for the self-calibration of critical delay elements. The present invention also includes a method for synchronizing data transfers between a bus master device that is clocked by a system clock and a plurality of synchronous DRAM devices (SDRAM) that are clocked by a local clock; the local clock has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles. A Dual In Line Module (DIMM) of the present invention receives a system clock signal and provides a local clock signal to an array of SDRAM devices, wherein the local clock signal has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles. Optionally the magnitude of the phase-offset of the local clock signal is selectable through software providing the flexibility to support a method for determining the optional phase-offsets by software using an iterative process involving trial and error.

Patent
02 Oct 1998
TL;DR: In this article, a clock synchronization circuit is used to synchronize a reference or system clock signal in a programmable logic device or field programmable gate array (FPG array).
Abstract: A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase-locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.

Patent
17 Apr 1998
TL;DR: In this article, a multi-phase clock generator is implemented by a delay circuit that receives an input clock signal, and the clock generator couples the input clock signals to a first clock output terminal and to a delay circuits.
Abstract: A multi-phase clock generator is implemented by a delay circuit that receives an input clock signal. The clock generator couples the input clock signal to a first clock output terminal and to a delay circuit. The delay circuit delays the input clock signal to produce a delayed clock signal, and the delayed clock signal is coupled to a second clock output terminal. The first and second clock signals coupled to the first and second clock output terminals are applied to a logic circuit that generates two clock signals and their compliments. These clock signals are used to clock a shift register on both the rising and falling edge of the input clock signal. The shift register may be used in a command buffer for a packetized DRAM, and one or more of the resulting packetized DRAMs may be used in a computer system.

Patent
02 Jan 1998
TL;DR: In this paper, a method for synchronizing clocks includes sensing currents at multiple terminals, exchanging current and time stamp data between local and remote terminals, estimating a frequency deviation between local clock and power system frequencies; estimating a time-based phase deviation with the time-stamped data; and using the frequency, time based phase, and current based phase deviations to synchronize the local clock.
Abstract: A method for synchronizing clocks includes: sensing currents at multiple terminals; exchanging current and time stamp data between local and remote terminals; estimating a frequency deviation between local clock and power system frequencies; estimating a time based phase deviation with the time stamp data; estimating a current based phase deviation between the currents at the local and remote terminals; and using the frequency, time based phase, and current based phase deviations to synchronize the local clock. An integer counter value of the clock can be controlled by adjusting the integer counter value based on a sum of fractional counter values to increase clock resolution.

Patent
25 Mar 1998
TL;DR: In this article, a dynamic clocking computer system for a processor is described, which consists of a clock divider circuit, a multiplexer, and a state machine circuit.
Abstract: A dynamic clocking computer system for a processor. The dynamic clocking computer system comprises a clock divider circuit, a multiplexer, and a state machine circuit. The clock divider circuit receives a first clock and outputs the first clock and generates a second clock. The second clock is supplied to external circuitry. The state machine circuit is coupled to the clock divider circuit and receives the first and second clocks from the clock divider circuit. The state machine circuit also receives an external access signal indicating an internal clock to select from the first and second clocks. In response to the external access signal, the state machine circuit generates a select signal to enable the multiplexer to select an internal clock. When the selected internal clock is the second clock, the internal clock is synchronized to the second clock. The multiplexer is coupled to the clock divider circuit and receives the first and second clocks through the clock divider circuit. In response to the select signal generated by the state machine circuit, the multiplexer selects an internal clock from the first and second clocks. The internal clock is then provided to the processor. By thus providing a lower clock frequency to the processor for external access operations, the present invention reduces power dissipation.

Patent
Youji Terauchi1
30 Mar 1998
TL;DR: In this paper, the frequency-dividing circuit for dividing external clock supplied from a clock supply terminal, and a plurality of peripheral circuits which are operated by frequency-divided clocks.
Abstract: A semiconductor integrated circuit incorporating therein a clock supply circuit drives a plurality of peripheral circuits using different frequency-divided clocks. In order to avoid enlargement of switching current there is provided a frequency-dividing circuit for dividing external clock supplied from a clock supply terminal, and a plurality of peripheral circuits which are operated by frequency-divided clocks. There is provided a first clock supply circuit which is capable of generating frequency-divided clock with the highest frequency among frequency-divided clocks required by the peripheral circuits, and a plurality of second clock supply circuits for generating frequency-divided clocks from frequency-divided clock of the first clock supply circuit. Wiring to connect the first clock supply circuit to second clock supply circuits becomes short, and the number of wiring is reduced. Therefore it becomes possible to reduce the switching current.

Patent
18 May 1998
TL;DR: In this article, a phase interpolator is used to create a number of delay steps evenly spaced between the gross phase steps of the phase multiplexer to provide the required phase resolution.
Abstract: A clock recovery architecture for recovering clock and serial data from an incoming data stream of a local area network station. A phase picker architecture augmented by a phase interpolator is used as part of the clock recovery architecture to enhance phase resolution. A single clock generation module (CGM) and N phase multiplexers, one for each clock recovery channel on a chip, is used to select one of M phases of a 250 Mhz clock signal from the CGM for each clock recovery channel. To provide the required phase resolution, a phase interpolator is used. The phase interpolator is used to create a number of delay steps evenly spaced between the gross phase steps of the phase multiplexer. Each phase multiplexer is advanced or retarded in response to the pump-up (pumpup) or pump-down (pumpdn) signals from each clock recovery channel (CRM).

Patent
04 Aug 1998
TL;DR: In this paper, an interlocked clock multiplexer is used for acquiring a clock source which is provided as clock signal 102 to the data processing system, which can be connected to one or more clock sources 110 and 120.
Abstract: A clock acquisition subsystem for a data processing system has an interlocked clock multiplexer 100 for acquiring a clock source which is provided as clock signal 102 to the data processing system. Multiplexer 100 has at least two inputs 104 and 106 for clock source signals. Each clock source signal can be connected to one or more clock sources 110 and 120. Control register 130 specifies which clock source is to be selected by the multiplexer. The multiplexer has an interlocked synchronizer on each clock signal input so that when the multiplexer is switched, output clock signal 102 transitions cleanly from a first clock source to a second clock source without glitches or runt pulses.

Patent
Jung-Bae Lee1
08 Oct 1998
TL;DR: In this paper, an internal clock signal generator is provided which includes a synchronized delay circuit which receives an external clock signal and outputs a clock signal which is coarsely synchronized with the external clock signals.
Abstract: An internal clock signal generator is provided which includes a synchronized delay circuit which receives an external clock signal and outputs a clock signal which is coarsely synchronized with the external clock signal. A delay locked loop (DLL) or phase locked loop (PLL) receives the coarsely synchronized clock signal and generates an internal clock signal which is more finely synchronized with the external clock signal.

Patent
27 Oct 1998
TL;DR: Pulses are generated using an edge of a clock signal applied from a low speed tester as a trigger, and internal clock signals are generated utilizing the pulses as mentioned in this paper, which can be used to test a synchronous semiconductor device operating at high speed.
Abstract: Pulses are generated using an edge of a clock signal applied from a low speed tester as a trigger, and internal clock signals are generated utilizing the pulses. Internal circuitry is operated in synchronization with the internal clock signals. Thus a synchronous semiconductor device operating at high speed can be tested using a low speed tester.

Patent
Atsufumi Shibayama1
10 Sep 1998
TL;DR: In this article, a global clock forming circuit is set up on an LSI, and global clock signal is distributed on LSI by the double global clock distribution circuits cycled on the LSI in parallel with and in the inverse direction to one another.
Abstract: A global clock forming circuit for forming a global clock signal is set up on an LSI, and global clock signal is distributed on LSI by the double global clock distribution circuits cycled on the LSI in parallel with and in the inverse direction to one another. Based on the time point at the middle point of the transition point of each of the two clock signals transmitted by the global clock distribution circuit, the local clock signals are generated by the local clock generating circuits 4-(i+1), 4-(i+2), 4-j, 4-(k+1), 4-(l+1). The resulting local clock signals are distributed by the local clock distribution circuits 5-(i+1), 5-(i+2), 5-j, 5-(k+1), 5-(l+1). By this procedure, the clock signal distribution circuit can distribute low skew and high speed clock signals on a large scale integrated circuit.