Showing papers on "Clock gating published in 2000"

Clock generation and distribution for the first IA-64 microprocessor

Abstract: The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.

Clock-gating and its application to low power design of sequential circuits

Abstract: This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip flops to generate a derived clock for each flip flop in the circuit. A technique for clock gating is also presented, which generates a derived clock synchronous with the master clock. Design examples using gated clocks are provided next. Experimental results show that these designs have ideal logic functionality with lower power dissipation compared to traditional designs.

Continuous clock synchronization in wireless real-time applications

Abstract: Continuous clock synchronization avoids unpredictable instantaneous corrections of clock values. This is usually achieved by spreading the clock correction over the synchronization interval. In the context of wireless real time applications, a protocol achieving continuous clock synchronization must tolerate message losses and should have a low overhead in terms of the number of messages. The paper presents a clock synchronization protocol for continuous clock synchronization in wireless real time applications. It extends the IEEE 802.11 standard for wireless local area networks. It provides continuous clock synchronization, improves the precision by exploiting the tightness of the communication medium, and tolerates message losses. Continuous clock synchronization is achieved with an advanced algorithm adjusting the clock rates. We present the design of the protocol, its mathematical analysis, and measurements of a driver level implementation of the protocol on Windows NT.

Active GHz clock network using distributed PLLs

Abstract: Most modern microprocessors use a balanced tree to distribute the clock. However, at gigahertz clock speeds an increasing fraction of skew and jitter comes from random variations in gate and interconnect delay. The majority of jitter in a clock tree is introduced by buffers and inter-line coupling to the clock wires. A relatively small amount comes from noise in the source oscillator. This distributed clock network generates the clock signal with phase locked loops (PLLs) at multiple points (nodes) across a chip, and distributes each only to a small section of the chip (tile). Phase detectors (PD) at the boundaries between tiles produce error signals that are summed by an amplifier in each tile and used to adjust the frequency of the node oscillator.

Synchronous dynamic random access memory device

Abstract: A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

Clock skew verification in the presence of IR-drop in the power distribution network

Abstract: Clocks are perhaps the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of clock signals directly impact the performance of a very large scale integrated chip. Clock skew verification requires high accuracy and is typically performed using circuit simulators. However in high-performance deep-submicrometer digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher current load on the power distribution network with the potential for substantial power grid voltage (IR)-drop. This IR-drop affects the clock timing and must be taken into account in the verification process. Since IR-drop is a full-chip phenomenon, the use of standard circuit simulation on both the clock circuitry and the power-grid is not practical. In this paper, we present a new methodology for the verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full-chip dynamic IR-drop. The effect of IR-drop on the timing of clock signals is quantified on a small example, and demonstrated on a large chip.

Method and apparatus for testing circuits with multiple clocks

Abstract: A method of testing a circuit having two or more clock domains at respective domain test clock rates and under control of a main test clock signal, the circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to an output of the core logic and/or an output connected to an input to the core logic, and configurable in scan mode in which the memory elements are connected to define one or more scan chains in each domain and in normal mode in which the memory elements are connected to the core logic in normal operational mode, the method comprising configuring the memory elements in scan mode; concurrently clocking a test stimulus into each scan chain of each clock domain including, for each clock domain having a domain test clock signal which is synchronous with respect to the main test clock signal, clocking the test stimulus at a shift clock rate derived from the main test clock signal and, for each clock domain having a domain test clock signal which is asynchronous with respect to the main test clock signal, clocking all but a predetermined number of bits of the test stimulus at a first domain shift clock rate derived from the main test clock signal followed by clocking the predetermined number of bits of the test stimulus at a second domain shift clock rate corresponding to the domain test clock rate; configuring the memory elements of each scan chain in normal mode in which the memory elements of each scan chain are interconnected by the core logic in the normal operational mode; clocking each memory element in each scan chain at its respective domain test clock rate for at least one clock cycle thereof; configuring the memory elements in scan mode; and clocking a test response pattern out of each of the scan chains at its respective domain shift clock rate during a respective scan-out interval, all respective scan-out intervals overlapping in time for a plurality of clock cycles at the highest of the respective clock rates.

Power consumption reduction in medical devices employing multiple supply voltages and clock frequency control

Abstract: Power consumption in medical devices is reduced through the operation of circuits at clock speeds of lower levels to adequately complete desired functions during predetermined time periods (e.g., blanking interval, upper rate interval, etc.) just-in-time prior to subsequent required functional processes; by providing supply voltages tailored for various circuits of an integrated circuit; by operating two or more circuits of an integrated circuit at different clock frequencies; by changing the supply voltage level “on the fly” as required by specific circuit timing functions required for various circuitry based on clock frequencies used to control operation of such circuitry; and/or by tailoring back gate bias or adjusting back gate bias “on the fly” for circuits based on the supply voltage level applied to the circuits.

Low skew differential receiver with disable feature

Abstract: A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be “disabled” by an inactive enable signal so they output a constant “0” level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

Emulation system with multiple asynchronous clocks

Abstract: An emulation system includes a clock generation logic for generating multiple asynchronous clocks, where each generated clock's relative phase relationship with respect to all other generated clocks is strictly controlled to speed up the emulation logic evaluation. Unlike statically designed emulator systems known in the prior art, the speed of the logic evaluation in the emulator need not be slowed down to the worst possible evaluation time since the clocking is generated internally in the emulator and carefully controlled. The emulation system does not concern itself with the absolute time duration of each clock, because only the phase relationship among the multiple asynchronous clocks is important. By retaining the phase relationship (and the initial values) among the multiple asynchronous clocks, the speed of the logic evaluation in the emulator can be increased. The RCC clock generation logic comprises a clock generation scheduler and a set of clock generation slices, where each clock generation slice generates a clock. The clock generation scheduler compares each clock's next toggle point from the current time, toggles the clock associated with the winning next toggle point, determines the new current time, updates the next toggle point information for all of the clock generation slices, and performs the comparison again in the next evaluation cycle. In the update phase, the winning slice updates its register with a new next toggle point, while the losing slices merely updates their respective registers by adjusting for the new current time.

A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM

Abstract: A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-/spl mu/m CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm/spl times/10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% of that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 /spl mu/A, which is only 17% of that for the conventional CMOS design.

Integrated circuits with optical signal propagation

Abstract: An integrated circuit is presented in which optical signal propagation replaces or supplements conventional electrical signal propagation. Optical lasers, waveguides, beam splitters, and photodetectors are fabricated on top of or below conventional electrical semiconductor circuits to propagate data, clock, and control signals. Such optical signal propagation is generally more rapid than electrical signal propagation, and can free conventional electrical semiconductor circuit area by eliminating at least some conventional data busses and global clock and control wiring. Furthermore, optical clock signal propagation substantially eliminates clock skewing problems and reduces power consumption by significantly eliminating clock signal re-buffering.

Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance

Abstract: The large address space needs of many current applications have pushed processor designs toward 64-bit word widths. Although full 64-bit addresses and operations are indeed sometimes needed, arithmetic operations on much smaller quantities are still more common. In fact, another instruction set trend has been the introduction of instructions geared toward subword operations on 16-bit quantities. For examples, most major processors now include instruction set support for multimedia operations allowing parallel execution of several subword operations in the same ALU. This article presents our observations demonstrating that operations on “narrow-width” quantities are common not only in multimedia codes, but also in more general workloads. In fact, across the SPECint95 benchmarks, over half the integer operation executions require 16 bits or less. Based on this data, we propose two hardware mechanisms that dynamically recognize and capitalize on these narrow-width operations. The first, power-oriented optimization reduces processor power consumption by using operand-value-based clock gating to turn off portions of arithmetic units that will be unused by narrow-width operations. This optimization results in a 45%-60% reduction in the integer unit's power consumption for the SPECint95 and MediaBench benchmark suites. Applying this optimization to SPECfp95 benchmarks results in slightly smaller power reductions, but still seems warranted. These reductions in integer unit power consumption equate to a 5%-10% full-chip power savings. Our second, performance-oriented optimization improves processor performance by packing together narrow-width operations so that they share a single arithmetic unit. Conceptually similar to a dynamic form of MMX, this optimization offers speedups of 4.3%-6.2% for SPECint95 and 8.0%-10.4% for MediaBench.Overall, these optimizations highlight an increasing opportunity for value-based optimizations to improve both power and performance in current microprocessors.

New clock-gating techniques for low-power flip-flops

Abstract: Two novel low power flip-flops are presented in the paper. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if the input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.

Optimizing performance of a clocked system by adjusting clock control settings and clock frequency

Abstract: A method of adjusting the operating or timing margin of a clocked system, such as a digital computer or a memory controller, is disclosed. The method may be automated to occur upon every initial program load or can be manually adjusted for changes in frequency, operating voltages, or applications in which the timing margin is not so critical. An initial or default frequency of the clock is set. Clock control settings, such as duty cycle, VCO range and gain, etc, are also initialized and set as some default. Test, such as ABIST, LBIST or other functional tests, are performed on the clocked system and the clock frequency is incrementally increased until the tests fail. Upon failure of the tests, one or more clock control settings are adjusted and the tests are run again at the failing frequency. If the tests successfully complete, indicating no errors, the clock frequency is incremented again until the test fail. Again, the clock control settings are adjusted and the tests are repeated at increasing frequency until failure of the tests or until a desired timing margin is reached.

Self calibrating clocks for globally asynchronous locally synchronous systems

Abstract: We present a local clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global clock. After initial tuning, the local clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local clock domain is made possible by stretching the local clock if a metastable condition could be encountered. Stretching the clock just requires the rising clock edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.

Core clock correction in a 2/N mode clocking scheme

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Energy-Efficient Register Access

Abstract: We present and evaluate seven techniques to reduce energy dissipation for accesses to a processor register file: modified storage cell avoids bitline discharge for zero bits, precise read control avoids fetching unused operands, latch clock gating disables latch clocks when operands are not needed, bypass skip turns off regfile reads when bypass circuitry will supply the value, bypass RO treats accesses to RO separately, split bitline reduces access energy for frequently-used registers, and read caching avoids regfile reads when the same register is read twice in succession. For a 0.25 /spl mu/m CMOS three-port regfile, we find individual energy savings of 27%, 21%, 8%, 16%, 14%, 12%, and 1% respectively and a combined saving of 59% when all seven techniques are used in combination. The total area overhead is around 17% and the total delay overhead is around 3%.

Clock generator with programmable non-overlapping-clock-edge capability

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Method of testing at-speed circuits having asynchronous clocks and controller for use therewith

Abstract: A method of testing the care logic in a digital system, the method having a sequence of test operations including a shift-in operation in which a test stimulus is shifted into scanable memory elements in the core logic, a capture operation in which data in the memory elements is captured, and a shift-out operation in which captured data is shifted out of the core logic for analysis, comprises the improvement of, for each the test operation, concurrently enabling the domain clock of each clock domain in the core logic at the beginning of each test operation, performing the test operation in each domain and disabling the domain clock at the end of each test operation in each domain. The method allows all of the clock domains, including signal paths which traverse domain boundaries and/or have multi-cycle paths to be tested concurrently and at their respective functional clock rate of each clock.

Zero-delay buffer circuit for a spread spectrum clock system and method therefor

Abstract: A clock recovery circuit and a method for reduced electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generate an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock

Abstract: There is disclosed, for use in an x86-compatible processor, an interface circuit for synchronizing the transfer of signals between different clock domains derived from a common core clock, where the phase and frequency relationships between the different domain clocks are known. The interface circuit comprises 1) a first latch having a data input for receiving a data signal from the first clock domain, a clock input for receiving the first clock signal, and an output; 2) a second latch having a data input coupled to the first latch output, an enable input for receiving a gating signal, a clock input for receiving the first clock signal, and an output; 3) a third latch having a data input for receiving the data signal, an enable input for receiving a gating signal, a clock input for receiving the first clock signal, and an output; and 4) a multiplexer having a first data input coupled to the second latch output, a second data input coupled to the third latch output, and a selector input for selecting one of the first data input and the second data input for transfer to an output of the multiplexer.

Dynamic clock management for low power applications in FPGAs

Abstract: Low power techniques employing dynamically controlled clock rates offer potentially powerful energy saving capabilities. In this paper, we consider the application of this low power technique to FPGAs, where we reduce energy waste in clock distributions. We show that current FPGA clock managers are inadequate for use in dynamically controlled systems. We provide an architectural block, the dynamic clock divider, that can be added either internally to clock managers or as user logic, to allow dynamic clock management.

Variable clock cycle for processor, bus and components for power management in an information handling system

Abstract: A computer system that is able to switch processor and bus frequencies, along with processor voltage, when the system is placed into AC from battery power mode, and when the system is placed into battery from AC power mode. The computer system includes transitioning a processor (CPU) into a low performance mode using a clock generator that provides different clock frequencies, a high performance clock frequency and a low performance clock frequency depending on whether battery or AC power is used. The processor and interconnecting busses use the lower clock frequency in order to save battery power.

Digital phase-locked loop circuit with reduced phase jitter frequency

Abstract: A digital phase-locked loop (DPLL) ( 22 ) for use in one or more integrated circuits ( 20 ) that may be combined within an electronic system is disclosed. The DPLL ( 22 ) includes a phase detector ( 30 ) that generates a shift clock and a shift direction signal responsive to a phase difference between a system clock and a feedback clock. The shift direction signal is stored in a latch ( 32 ), applied to one input of an exclusive-NOR gate ( 34 ), and to shift direction inputs (R/{overscore (L)}) of first and second digital delay lines ( 38, 42 ). The first digital delay line ( 38 ) receives the system clock and generates a delayed clock that is distributed within the integrated circuit ( 20 ) by clock distribution circuitry, and that is applied to an input of the second digital delay line ( 42 ); the second digital delay line ( 42 ) generates the feedback clock that is received by the phase detector ( 30 ). The shift clock is gated from application to the first and second digital delay lines according to the comparison of the current shift direction with that stored in the latch ( 32 ), such that the shift clock is applied to the shift clock input of the first digital delay line ( 38 ) to adjust its delay only upon the phase detector ( 30 ) detecting a phase differential of the same polarity at least twice in a row; the shift clock is applied to the shift clock input of the second digital delay line ( 42 ) upon the phase detector ( 30 ) detecting opposite phase differentials in the current and previous phase detection events.

Low power flip-flop with clock gating on master and slave latches

Abstract: A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity.

Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit

Abstract: A hierarchical power control system for an integrated circuit may be integrated into a clocking system that includes a global clock generator, a clock distribution network in communication with the global clock generator and a plurality of functional unit blocks each in communication with the global clock generator. The hierarchical power control system may include a first power controller provided in a communication path between the global clock generator and the clock distribution network, and a plurality of second power controllers, one provided in each communication path between the clock distribution network and a functional unit block.

Glitch-free clock selector

Abstract: A pair of synchronized clock sources provides phase and frequency synchronous first and second clocks accompanied by first and second control signals to a clock selection circuit having a data selector comprising a first synchronizer and a second synchronizer which re-times the first and second control signals, and these re-timed outputs that are coupled to an asynchronous state machine. The asynchronous state machine changes state by logically operating on the re-timed control signals in conjunction with a state bit. This state bit is used to control the multiplexer, which achieves glitch-free switching between the first clock source and the second clock source.

Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel

Abstract: Precompensated NRZ-encoded data for writing to magnetic storage medium operates with multiple NRZI-to-NRZ decoders that are each supplied with a selectably-variable version of a master clock. The delayed versions of the master clock are stably produced by delay elements operating with D-flip flops and charge pumps in a delay-locked feedback loop. The direction of current supplied to or from a capacitor by the charge-pump during a cycle of delayed clock signal is controlled by the delayed clock signal for shaping the feedback signal to trigger appropriately the next cycle of the delayed clock signal. The duration of the selectable delay is adjusted by setting the amplitudes of the charge and discharge currents supplied by the charge-pump. Stable delayed versions of the master clock promote reliable conversions of NRZI data to write precompensated NRZ recordable data.

Clock generation and distribution in an emulation system

Abstract: A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.