Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Power Gating with Multiple Sleep Modes

Abstract: This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. Our simulations and data traces show that multiple sleep mode capability provides an extra 17% reduction in overall leakage as compared to single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit.

High speed clock distribution system

Abstract: This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

Method and system for multi-protocol clock recovery and generation

Abstract: A method and system for synchronizing a receiver's clock to the clock of a transmitter is disclosed herein. The disclosed system employs a digital clock synthesizer that uses patterns superimposed upon a receiver oscillator to synthesize a clock rate that approximates the clock rate of the transmitter. The pattern superimposed upon the receiver oscillator can be varied to allow for tracking of the variation in the transmitter clock.

Clock distribution network

Abstract: A method and an apparatus for providing an optical clock distribution network. In one embodiment, an optical source is configured to emit optical pulses at a desired clock frequency. The optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die. In one embodiment, each clock receiver node locally generates a photocurrent in response to the split optical beams. Each of the photocurrents is locally converted into voltage and thus into local clock signals, which are used to clock the local area of the integrated circuit. In one embodiment, the semiconductor die includes an additional clock receiver node used to clock a clock generation circuit included in the semiconductor die. The clock generation circuit generates clock signals that are in phase with each other and the other clock signals generated throughout the semiconductor die. In one embodiment, the clock signals generated by the clock generation circuit are used to clock and phase lock input/output communications on the semiconductor die as well as off chip input/output communications between the semiconductor die and other external semiconductor dice of the system.

Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications

Abstract: Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.