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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


Papers
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Patent
06 May 2003
TL;DR: In this article, a power factor correction (PFC) circuit includes a pulse width modulator (PWM) operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct the power factor at a node.
Abstract: A power factor correction (PFC) circuit (10) includes a pulse width modulator (31) operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct a power factor at a node (32). The coil current discharges over a discharging period (TDSCHG) to develop an output voltage (VOUT) at an output (30). An oscillator (35) generates the clock signal to have a clock period (TCLK) longer than the sum of the charging and discharging periods, thereby operating in a discontinuous mode, and has an input (39) for sensing the input signal to modify the clock period.

43 citations

Patent
13 Jan 2003
TL;DR: In this article, a circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least conductor therein, where at least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuits.
Abstract: A circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit. By operating the clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

43 citations

Patent
24 Jun 2008
TL;DR: In this article, a charge pump system is formed on an integrated circuit that can be connected to an external power supply, and a clock circuit is coupled to provide a clock output, at whose frequency the charge pump operates and generates output voltage from an input voltage.
Abstract: A charge pump system is formed on an integrated circuit that can be connected to an external power supply. The system includes a charge pump and a clock generator circuit. The clock circuit is coupled to provide a clock output, at whose frequency the charge pump operates and generates an output voltage from an input voltage. The clock frequency is a decreasing function of the voltage level of the external power supply. This allows for reducing power consumption in the charge pump system formed on a circuit connectable to an external power supply.

43 citations

Patent
07 Aug 1997
TL;DR: In this paper, a programmable digital filter includes multiple sampling stages that sample an input signal and a detection circuit has inputs coupled to the outputs of the multiple stages and changes the logic state of an output signal when no glitches are detected in the samples of the input signal.
Abstract: A synchronizer circuit manages signals in different clock domains by generating clock pulses synchronized with a system clock. The clock pulses are generated at a rate proportional to the frequency of a clock operating in a first clock domain. Digital circuitry is then driven at the frequency of the first clock and in the time domain of the system clock. A hand-shaking protocol prevents the synchronizer circuit from going into a metastable condition when passing clock or data signals into different time domains. A programmable digital filter includes multiple sampling stages that sample an input signal. A detection circuit has inputs coupled to the outputs of the multiple sampling stages and changes the logic state of an output signal when no glitches are detected in the samples of the input signal. A control circuit selectively varies a time period used by the filter for sampling the input signal.

43 citations

Patent
18 Dec 2001
TL;DR: In this paper, the authors propose a system and method of compensating for voltage droop in an integrated circuit, where the integrated circuit is driven by a clock signal, determining an optimum frequency change to compensate for the voltage drop, and adapting cycle time of the clock signal in an incremental manner.
Abstract: A system and method of compensating for voltage droop in an integrated circuit. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop detector. The clock control system adapts cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected. The method may include detecting a voltage droop in an integrated circuit where the integrated circuit is driven by a clock signal, determining an optimum frequency change to compensate for the voltage droop, and adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.

43 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884