Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Data synchronizing system

Abstract: A system is described for acquiring incoming serial data, particularly of PCM code types, and establishing synchronization between the incoming data and a local clock generator. The system includes input signal conditioning circuits which applies the incoming data to a phase lock loop containing the local clock generator. The phase lock loop includes circuits for acquiring the input data and synchronizing the local clock generator therewith in spite of low signal-to-noise ratios and the loss of a large percentage of the input data bits in transmission. The local clock generator circuits include circuits which compare the phase of the clock generator output with the phase of the incoming data bits on a maximum likelihood phase estimate basis. The local clock generator outputs are applied to detect the incoming bits and reconstruct them into a noise-free output data stream.

Clock pulse signal generator system

Abstract: A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output.

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

Abstract: In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.

A novel synthesis approach for active leakage power reduction using dynamic supply gating

Abstract: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode. We present a novel low-cost design methodology with associated synthesis flow for reducing both switching and active leakage power using dynamic supply gating. A logic synthesis approach based on Shannon expansion is proposed that dynamically applies supply gating to idle parts of general logic circuits even when they are performing useful computation. Experimental results on a set of MCNC benchmark circuits in a predictive 70nm process exhibits improvements of 15% to 88% in total active power compared to the results obtained by a conventional optimization flow.

Synchronizing clock pulse generator for logic derived clock signals with synchronous clock suspension capability for a programmable device

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created. Further, the programmable device includes circuit for suspending a clock signal. In one embodiment, an asynchronous logic derived clock signal is generated and synchronized with a synchronous clock signal provided to the programmable device to produce a synchronized logic derived clock signal. The synchronized logic derived clock signal is logically combined with the synchronous clock signal to produce a suspended clock signal.