Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Fault tolerant clock distribution system

Abstract: A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.

Clock distribution method and apparatus for high speed circuits with low skew using counterpropaging true and complement re-generated clock signals with predetermined ramp shapes

Abstract: There is disclosed herein a method and apparatus for distributing high speed clock signals on an integrated circuit while eliminating clock skew. The invention is particularly useful in field programmable gate arrays where the signal paths are defined by the user after the integrated circuit leaves the place of manufacture and enables field programmable gate arrays to operate at clock speeds in excess of 200 MHz, a speed not previously attainable. Clock skew is eliminated by generating differential clock signals at each of four corners of the array from master differential clock signal delivered simultaneously to each of the four corners. The differential clock signals generated at each corner have ramps the rise time of which slightly exceeds the propagation delay of a clock signal traversing the array. The true signal is propagated across both the top and bottom of the array of cells in the same direction and the complement clock signal is propagated across both the top and bottom of the array of cells in the opposite direction. At the top and bottom of each column, secondary clock receivers receive the true and complement clock signals and generate new differential column clock signals with ramps that are triggered at the time at each column when the true and complement clock signals "crossover", i.e., are equal in amplitude. The ramps of these column clock signals also have rise times which slightly exceed the propagation delay of a clock signal propagating down a column. The differential clock signals are generated at the top and bottom of each column. The true clock signal generated at the top of each column is propagated down each column and the complement clock signal generated at the bottom of each column is propagated up the column. Each cell uses as its clock marker the crossover point between the counter-propagating true and complement clock signals.

System for the manipulation of secure data

Abstract: This invention concerns a system for the manipulation of secure data which includes electronics or software, or both, that are designed to operate within a specific clock speed range. The system is provided with a clock frequency limiter in the clock signal line, upstream of elements that are to be protected. The limiter involves an enable gate having an input port, an output port and a control port, and is located in the clock signal line to pass the clock signal from the input port to the output port only when it is enabled by a signal at the control port. Clock signal taps are connected to pass clock signals from upstream and downstream of the enable gate to an edge detector, and the output of the edge detector is passed through a delay to the control port of the enable gate.

Clock offset compensator

Abstract: A device communicates with a host and includes a transmitter, a receiver and a clock generator that generates a signal having a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from the host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the clock frequency and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset. The host and the device may communicate using a serial ATA standard. Frequency compensation can be performed during spread spectrum operation.

Timing signal generation circuit

Abstract: A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.